CN107017248A - A kind of low trigger voltage SCR structure triggered based on floating trap - Google Patents
A kind of low trigger voltage SCR structure triggered based on floating trap Download PDFInfo
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- CN107017248A CN107017248A CN201710149961.2A CN201710149961A CN107017248A CN 107017248 A CN107017248 A CN 107017248A CN 201710149961 A CN201710149961 A CN 201710149961A CN 107017248 A CN107017248 A CN 107017248A
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- 230000001960 triggered effect Effects 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 17
- 230000004224 protection Effects 0.000 abstract description 7
- 230000024241 parasitism Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
Abstract
The invention belongs to the electrostatic discharge (ESD) protection field of integrated circuit, a kind of low trigger voltage SCR structure triggered based on floating trap protected for ESD is specifically provided, the trigger voltage to further reduction LVTSCR devices.The present invention introduces a floating well structure by internal structure design in device inside；The equivalent structure into a diode of floating well structure, its anode is connected with PMOS polysilicon gate, and negative electrode is connected with SCR anode；When esd pulse arrives, the potential of floating trap is low relative to the anode potential of SCR device, when electrical potential difference between the two opens PMOS enough；After P-channel MOSFET is opened, the parasitic NPN transistor inside triggering SCR device is opened, and then triggers parasitic-PNP transistor unlatching, and last SCR device opens ESD electric currents of releasing.Therefore, the trigger voltage of device is determined by the gate-source capacitance of floating well structure He parasitism PMOS, you can realize the purpose for reducing SCR device trigger voltage, and the trigger voltage is modulated.
Description
Technical field
The invention belongs to the static discharge (ESD of integrated circuit：Electro-Static discharge) protection field, relate to
And a kind of esd protection structure device, and in particular to a kind of thyristor of the new low trigger voltage for being used for ESD protections
(SCR：SemiconductorControl Rectifier) device architecture.
Background technology
Static discharge is one of important branch of IC reliability, from chip manufacturing to production and assembly, from product fortune
It is defeated to arrive routine use, all along with the generation of static discharge phenomenon during the whole life cycle of electronic product.According to statistics,
It is as caused by ESD/EOS problems that electronic product failure, which has more than 1/3rd,.In view of so big quantity, design performance is excellent
ESD protective device more is increasingly paid close attention to by people.
In order to reach that protection chip resists the purpose of electrostatic strike, existing a variety of electrostatic protection devices are suggested at present.
In integrated circuit, diode, MOSFET, SCR etc. may serve to serve as ESD protective device, and wherein SCR is most efficient
One of ESD protective device.The voltage that SCR enters after conducting state on device drops to rapidly a very low value, it is ensured that device
Relatively low thermal power loss itself, therefore SCR has extremely strong current drain ability.Moreover, other ESD protective devices are compared,
The unit area ESD protective capabilities of SCR device are most strong.
The defencive function of the ESD protective device under a particular semiconductor technique is realized, ESD protective device is except real
Beyond now stronger current drain ability, in addition it is also necessary to the ESD work that the trigger voltage and maintenance voltage of ESD protection device are constituted
Window is within ESD design windows.In general, the safe range of device operation window should be less than conventional in integrated circuit
The gate oxide breakdown voltage BV of MOSFET elementox.This requires the cut-in voltage V of ESD protective devicet1It must be smaller than
BVox.Moreover, as 21 century integrated circuit fabrication process constantly improves, cmos circuit formally enters nanoscale, ultra-thin
Gate oxide is very fragile before ESD stress planes.Under this trend, the SCR device of low trigger voltage carrys out static electricity discharge electric charge
To protect grid oxic horizon to seem particularly significant.
In CMOS technology, it is typically employed in SCR device structure an embedded PMOS to reduce SCR trigger voltage
Device architecture reduces the cut-in voltage V of SCR devicet1.The device is referred to as LVTSCR (low voltage triggering
SCR), its device architecture and equivalent circuit diagram are as shown in Figure 3；The device architecture includes：
P-type silicon substrate 110；
Form well region on the substrate 110, the well region includes the well region 120 of n-type and the well region 130 of a p-type,
And the well region 120 abuts the well region 130；
The doped region 122 of heavily doped region 121 and p-type in the n-type well region 120 provided with n-type, and the He of the region 121
Region 122 is connected with anode；
The heavily doped region 132 of heavily doped region 131 and p-type in the p-type well region 130 provided with n-type, and region 131 and area
Domain 132 is connected with negative electrode；
The heavily doped region 123 of p-type is bridged between the n-type well region 120 and p-type well region 130；
Silicon face Shang Youyige gate oxides area 140 between the p-type heavily doped region 122 and p-type heavily doped region 123,
And the gate oxide area 140 is connected by polysilicon thereon with anode.
The SCR device is by the parasitic P-channel of a parasitic PNP transistor, a parasitic NPN transistor and one
MOSFET element is constituted.Wherein, p-type heavily doped region 122, n-type well region 120, p-type well region 130 and p-type heavily doped region 132 are constituted
One PNP transistor；N-type heavily doped region 131, p-type well region 130, one NPN of n-type well region 120 and the formation of n-type heavily doped region 121
Transistor；P-type heavily doped region 122, p-type heavily doped region 123 and gate oxide 140 constitute a P-channel MOSFET；RNWFor n
The resistance of type well region 120；RPWFor the resistance of p-type well region 130.It is interim when esd event, the drain-source p-n junction of parasitic P-channel MOSFET pipes
It is reverse-biased.The p-n junction is set to occur to produce substantial amounts of electricity near avalanche breakdown, the source region of P-channel MOSFET element when ESD voltage is arrived greatly
Sub- hole pair, hole enters p-type well region 130 by p-type heavily doped region 123 and forms electric current, and in RPWUpper generation pressure drop, makes p-type
The emitter junction positively biased of well region 130 and the p-n junction positively biased, i.e. parasitic NPN pipe of the formation of n-type heavily doped region 131.Meanwhile, electron stream stream
Cross the resistance R of n-type well region 120NW, make the p-n junction positively biased of p-type heavily doped region 122 and the formation of n-type well region 120, i.e. hair in PNP pipe
Knot positively biased is penetrated, PNP pipe is opened.Afterwards, the collector current of NPN pipes provides base current, and the current collection of PNP pipe for PNP pipe
Electrode current provides base current for NPN pipes, and positive feedback, SCR conductings are formed between parasitic NPN pipe and PNP pipe.Therefore,
The trigger voltage of LVTSCR devices by P-channel MOSFET element drain-source breakdown voltage BVDSDetermine；For the low pressure process triggering
Voltage is still excessive.
The content of the invention
It is an object of the invention to provide a kind of new low trigger voltage SCR structure triggered based on floating trap, it is used to
Further reduce the trigger voltage of LVTSCR devices.Structure of the present invention introduces one by internal structure design in device inside
Floating well structure, based on the triggering of floating trap, effectively lowers the trigger voltage of SCR device, and trigger voltage is modulated.
To achieve the above object, the technical solution adopted by the present invention is：
A kind of low trigger voltage SCR structure triggered based on floating trap, including：
The first conduction type silicon substrate；
Second of the conduction type deep-well region formed on the first conduction type silicon substrate；
Second adjacent of the conduction type well region formed on second of conduction type deep-well region and the first conductive-type
Provided with second of the conduction type heavily doped region and one being connected with anode in type well region, second of conduction type well region
The first individual conduction type heavily doped region, leads for second provided with one be connected with negative electrode in the first described conduction type well region
Electric type heavily doped region and the first conduction type heavily doped region, second of conduction type well region and the first conduction
Between type well region bridge the first conduction type heavily doped region, the first conduction type heavily doped region of the bridging and
Silicon face in the first conduction type well region between second of conduction type heavily doped region provided with a gate oxide area and
Covered with polysilicon in gate oxide area；
Characterized in that, be formed with second of conduction type deep-well region another the first conduction type well region,
The opposite side of second of conduction type well region is adjacent to, provided with the first conduction in the first conduction type well region
Type heavily doped region, and the first conduction type heavily doped region is connected by metal level with the polysilicon.
Further, in the SCR structure, second of conduction type well region, the first conduction type well region and
The domain of the heavily doped region of the first conduction type in well region and second of conduction type heavily doped region is distributed in strip, institute
The domain for stating gate oxide area is distributed or segmentation distribution in proportion in strip.
The beneficial effects of the present invention are：
The present invention provides a kind of low trigger voltage SCR structure triggered based on floating trap, by internal structure design, in device
A floating well structure is introduced inside part；The equivalent structure into a diode of floating well structure, its anode and PMOS's is more
Polysilicon gate is connected, and negative electrode is connected with SCR anode；When esd pulse arrives, the potential of floating trap is relative to SCR device
Anode potential is low, when electrical potential difference between the two opens PMOS enough；After P-channel MOSFET (PMOS) is opened, SCR is triggered
The parasitic NPN transistor of device inside is opened, and then triggers parasitic-PNP transistor unlatching, and last SCR device opens the ESD that releases
Electric current.Compared to by drain-source breakdown voltage BVDSThe common LVTSCR determined, the SCR triggered using floating trap makes P-channel MOSFET
The grid of pipe obtains a relatively low current potential and it is opened under lower trigger voltage.Meanwhile, can be with according to application conditions
Adjust the element layout parameter and realize that trigger voltage is modulated, such as Fig. 2 changes the transverse width of heavily doped region 151 and the adjustment of p-type
The ration of division of gate oxide 160.Therefore, the trigger voltage of SCR structure of the present invention is by floating well structure and parasitic P-channel MOSFET
The gate-source capacitance of pipe is determined, you can realize the purpose for reducing SCR device trigger voltage, and the trigger voltage is modulated.
Brief description of the drawings
Low trigger voltage SCR structure schematic diagram and equivalent circuit that Fig. 1 is triggered for the present invention based on floating trap.
The domain schematic diagram for the low trigger voltage SCR structure that Fig. 2 is triggered for the present invention based on floating trap.
Fig. 3 is existing LVTSCR structural representations and equivalent circuit.
Embodiment
The present invention is described in detail with reference to the accompanying drawings and detailed description.
The present embodiment provides a kind of low trigger voltage SCR structure triggered based on floating trap, as shown in figure 1, its structure bag
Include：
P-type silicon substrate 110；
N-type deep-well region 140 is formed on the substrate 110；
An adjacent n-type well region 120 and the well region 130 of a p-type are formed on the n-type deep-well region 140；
The heavily doped region 122 of heavily doped region 121 and p-type in the n-type well region 120 provided with n-type, and the region 121
It is connected with region 122 with anode；
The heavily doped region 132 of heavily doped region 131 and p-type in the p-type well region 130 provided with n-type, and region 131 and area
Domain 132 is connected with negative electrode；
The heavily doped region 123 of p-type is bridged between the n-type well region 120 and p-type well region 130；
Silicon face Shang Youyige gate oxides area 160 between the p-type heavily doped region 122 and p-type heavily doped region 123,
And there is polysilicon layer covering on the surface of gate oxide area 160；
It is also formed with being adjacent to another p-type well region 150 of the opposite side of n-type well region 120, institute on the n-type deep-well region 140
The heavily doped region 151 that p-type is provided with p-type well region 150 is stated, the heavily doped region 151 of p-type passes through metal level and gate oxide area 160
On polysilicon layer be connected.
The equivalent circuit diagram of the above-mentioned low trigger voltage SCR structure triggered based on floating trap is as shown in figure 1, the SCR device
It is by a parasitic PNP transistor, parasitic NPN transistor, a parasitic P-channel MOSFET element (PMOS) and one
Individual floating well structure is constituted.Wherein, p-type heavily doped region 122, n-type well region 120, p-type well region 130 and the structure of p-type heavily doped region 132
Into a PNP transistor；N-type heavily doped region 131, p-type well region 130, n-type well region 120 and the formation of n-type heavily doped region 121 one
NPN transistor；P-type heavily doped region 122, p-type heavily doped region 123 and gate oxide area 160 constitute a P-channel MOSFET；p
Type well region 150 and p-type heavily doped region 151 constitute a floating well structure；RNWFor in n-type well region 120 from n-type heavily doped region
121 start to the trap resistance between the region of n traps 120 and the adjoiner of p traps 130；RPWFor the resistance of p-type well region 130；P-type trap
Area 150 is floating trap, can be regarded as a diode structure, the anode of the diode and PMOS polysilicon gate pole plate 160
It is connected, negative electrode is connected with SCR anode.When esd event comes interim, because voltage changes with time, the potential of floating trap is low
In the anode voltage of SCR device, and then P-channel MOSFET gate voltage is less than anode voltage, and open P-channel MOSFET
Open.When P-channel MOSFET element is opened, just there is hole to enter P-channel MOSFET channel area by p-type heavily doped region 122, then
P-type well region 130 is flowed into by p-type heavily doped region 123, hole current passage is formed.The electric current is in RPWUpper generation pressure drop, makes p-type
The emitter junction positively biased of well region 130 and the p-n junction positively biased, i.e. parasitic NPN pipe of the formation of n-type heavily doped region 131, turns on the NPN pipes.
Meanwhile, the collector current of parasitic NPN pipe flows through the resistance R of n-type well region 120NW, make p-type heavily doped region 122 and the shape of n-type well region 120
Into p-n junction positively biased, i.e., the emitter junction positively biased in PNP pipe opens PNP pipe.Afterwards, the collector current of NPN pipes is PNP pipe
Base current is provided, and the collector current of PNP pipe provides base current for NPN pipes, the shape between parasitic NPN pipe and PNP pipe
Into positive feedback, SCR conductings.Therefore, the trigger voltage of device of the present invention is by floating well structure and the grid of parasitic P-channel MOSFET pipes
Source electric capacity is determined, can be achieved to reduce the purpose of SCR device trigger voltage, and the trigger voltage is modulated.
Fig. 2 realizes the domain schematic diagram of SCR device of the present invention；
It is the domain of strip SCR device, deep n well region 140 therein, p-type well region 150, n-type well region shown in domain 100
120th, p-type well region 130, p-type heavily doped region 151, n-type heavily doped region 121, p-type heavily doped region 122, p-type heavily doped region 123, n
The domain of type heavily doped region 131 and p-type heavily doped region 132 is distributed in strip, and it is in strip that the domain of gate oxide area 160, which is also,
Distribution.
It is the domain of strip SCR device shown in domain 200, deep n-well region 140 therein, p-type well region 150, n-type well region
120th, p-type well region 130, p-type heavily doped region 151, n-type heavily doped region 121, p-type heavily doped region 122, p-type heavily doped region 123, n
Type heavily doped region 131, the domain of p-type heavily doped region 132 are distributed in strip, and the domain in gate oxide area 160 is by certain
The segmentation distribution of ratio.Adjusted by the ration of division of the domain, the grid source of the parasitic P-channel MOSFET element of adjustment can be reached
The purpose of capacitance size, so that the trigger voltage of SCR device is adjustable.
The foregoing is only a specific embodiment of the invention, any feature disclosed in this specification, except non-specifically
Narration, can alternative features equivalent by other or with similar purpose replaced；Disclosed all features or all sides
Method or during the step of, in addition to mutually exclusive feature and/or step, can be combined in any way.
Claims (2)
1. a kind of low trigger voltage SCR structure triggered based on floating trap, including：
The first conduction type silicon substrate；
Second of the conduction type deep-well region formed on the first conduction type silicon substrate；
Adjacent second of the conduction type well region and the first conductive type of trap formed on second of conduction type deep-well region
Area, provided with second of conduction type heavily doped region being connected with anode and one the in second of conduction type well region
Provided with second of conductive-type being connected with negative electrode in a kind of conduction type heavily doped region, the first described conduction type well region
Type heavily doped region and the first conduction type heavily doped region, second of conduction type well region and the first conduction type
The first conduction type heavily doped region, the first conduction type heavily doped region and first of the bridging are bridged between well region
Plant the silicon face in conduction type well region between second of conduction type heavily doped region and be provided with a gate oxide area and grid oxygen
Covered with polysilicon in Hua Ceng areas；
Characterized in that, being formed with another the first conduction type well region, adjoining on second of conduction type deep-well region
Provided with the first conduction type in the opposite side of second of conduction type well region, the first conduction type well region
Heavily doped region, and the first conduction type heavily doped region is connected by metal level with the polysilicon.
2. the low trigger voltage SCR structure triggered as described in claim 1 based on floating trap, it is characterised in that the SCR structure
In, the first conduction type heavy doping in second of conduction type well region, the first conduction type well region and well region
Area and the domain of second conduction type heavily doped region are distributed in strip, the domain in the gate oxide area be distributed in strip or
Person splits distribution in proportion.
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| CN201710149961.2A CN107017248B (en) | 2017-03-14 | 2017-03-14 | Low trigger voltage SCR structure based on floating trap triggering |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680965A (en) * | 2017-11-10 | 2018-02-09 | 江南大学 | A kind of ESD protective device of double MOS auxiliary triggerings based on SCR structure |
| CN107833884A (en) * | 2017-11-02 | 2018-03-23 | 杰华特微电子（杭州）有限公司 | Ghyristor circuit and its device architecture for electrostatic protection |
| CN109314131A (en) * | 2018-09-05 | 2019-02-05 | 香港应用科技研究院有限公司 | Low capacitance ESD (ESD) with double suspension joint traps protects structure |
| US10504886B1 (en) | 2018-09-05 | 2019-12-10 | Hong Kong Applied Science and Technology Research Institute Company, Limited | Low-capacitance electro-static-discharge (ESD) protection structure with two floating wells |
| CN110571214A (en) * | 2019-08-28 | 2019-12-13 | 电子科技大学 | Silicon controlled rectifier structure with multiple trigger channels |
| CN112071835A (en) * | 2020-09-25 | 2020-12-11 | 上海华力微电子有限公司 | Gate-constrained silicon controlled rectifier and implementation method thereof |
| CN112071834A (en) * | 2020-09-25 | 2020-12-11 | 上海华力微电子有限公司 | Gate-constrained silicon controlled rectifier and implementation method thereof |
| CN112447705A (en) * | 2019-09-04 | 2021-03-05 | 智原科技股份有限公司 | Electrostatic discharge protection device |
| CN113380786A (en) * | 2021-08-11 | 2021-09-10 | 江苏应能微电子有限公司 | Thyristor transient voltage suppression protection device structure integrated with reverse conducting diode |
| CN113571513A (en) * | 2021-09-23 | 2021-10-29 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
| TWI791325B (en) * | 2021-11-15 | 2023-02-01 | 旺宏電子股份有限公司 | Electrostatic discharge protection apparatus and its operating method |
| US11837600B2 (en) | 2021-11-15 | 2023-12-05 | Macronix International Co., Ltd. | Electrostatic discharge protection apparatus and its operating method |
| WO2024041082A1 (en) * | 2022-08-24 | 2024-02-29 | 无锡华润上华科技有限公司 | Silicon controlled rectifier and esd protection device |
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| CN112071835B (en) * | 2020-09-25 | 2024-03-15 | 上海华力微电子有限公司 | Grid-constrained silicon controlled rectifier and implementation method thereof |
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| WO2024041082A1 (en) * | 2022-08-24 | 2024-02-29 | 无锡华润上华科技有限公司 | Silicon controlled rectifier and esd protection device |
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