CN107680965B - ESD protection device based on SCR structure and triggered in double MOS assistance - Google Patents
ESD protection device based on SCR structure and triggered in double MOS assistance Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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Abstract
An ESD protection device based on double MOS auxiliary triggering of an SCR structure can be used for ESD protection of an on-chip IC. The device mainly comprises a P substrate, an N-type buried layer, an N well, a P well, a drift region, a first N+ injection region, a first P+ injection region, a second N+ injection region, a third N+ injection region, a second P+ injection region, a third P+ injection region, a fourth N+ injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate. Under the action of ESD stress, on one hand, the device is provided with an auxiliary trigger path formed by serially connecting the grounded gate NMOS and the PMOS, so that the trigger voltage of the ESD protection device can be reduced, the maintenance voltage can be improved, the voltage hysteresis range of the ESD protection device after being started is reduced, the voltage clamping capability of the device is enhanced, and on the other hand, the device is provided with a double SCR trigger path positioned on the surface and the buried layer, and the ESD robustness of the device can be enhanced.
Description
Technical Field
The invention belongs to the field of electrostatic discharge protection of integrated circuits, relates to an ESD protection device, and in particular relates to a double MOS auxiliary triggering ESD protection device based on an SCR structure, which can be used for improving the ESD reliability of an on-chip IC.
Background
Researchers in the electronics industry have increasingly focused on the problem of static-induced failure or damage to circuit functions, which has become important, particularly after transistors have been widely used in electronic products. Different types of electrostatic discharge (ESD) protection methods, ESD protection device designs, and related test techniques have all evolved rapidly. With the diversification of process flows and related application materials of electronic products, the production links are gradually increased, the feature size of the IC manufacturing process is gradually reduced, and the ESD protection design of the on-chip IC faces a serious challenge. Currently, ESD protection devices commonly used for on-chip ICs mainly include diodes, MOS transistors, and Silicon Controlled Rectifiers (SCR). The diode has simple structure and less parasitic effect, is commonly used for ESD protection of a low-voltage IC, but has larger leakage current; the MOS tube has good process compatibility, is widely applied to the ESD protection of the on-chip IC, and particularly NMOS, and is more applied to the ESD protection of each IO port in the IC because the comprehensive performance of the MOS tube in the ESD protection is relatively compromised. The biggest defect of the MOS device is represented by poor ESD robustness and larger occupied chip area. Compared with two devices, namely a diode and a MOS, the SCR device has enhanced ESD robustness under the condition of consuming the same chip area. However, since the SCR structure has a deep hysteresis characteristic under the ESD stress, latch-up is easily generated. Therefore, the conventional SCR structure cannot be directly used for ESD protection of the on-chip IC, and improvement, layout optimization design, and the like are generally required to be performed based on the conventional SCR structure according to the working requirements of different circuits.
The embodiment of the invention mainly aims at the deep hysteresis problem of the traditional SCR structure in ESD protection, and provides a technical scheme with small voltage hysteresis amplitude and strong ESD robustness by utilizing the auxiliary triggering of NMOS and the strong voltage clamping capability of PMOS. On one hand, the device is provided with an auxiliary trigger path formed by serially connecting the gate grounding NMOS and the PMOS, wherein the gate grounding NMOS can reduce the trigger voltage of the device, the gate grounding PMOS can improve the maintaining voltage of the device, and the deep hysteresis problem existing before and after the ESD protection device is started can be solved; on the other hand, along with the enhancement of ESD stress, the double SCR trigger paths of the device on the surface and the buried layer can be started successively, so that the ESD current discharging capability of the device is enhanced, and the ESD robustness of the device is improved.
Disclosure of Invention
Aiming at the problem of high trigger voltage and low maintenance voltage commonly existing in the ESD protection of the traditional SCR structure, the embodiment of the invention designs the double-MOS auxiliary trigger ESD protection device based on the SCR structure, fully utilizes the characteristic of strong ESD robustness of the SCR structure, reasonably controls the channel length of the PMOS tube by embedding the NMOS and the PMOS tube, and enables the device to form an auxiliary trigger path of serially connected gate grounding NMOS and PMOS and a double-SCR trigger path positioned on the surface and the buried layer under the action of ESD pulse, thereby realizing an ESD protection design scheme with low trigger, high maintenance voltage and strong ESD robustness.
The invention is realized by the following technical scheme:
the utility model provides an ESD protection device based on supplementary trigger of two MOS of SCR structure, its includes the supplementary trigger path of gate ground NMOS and PMOS series connection and is located the surface and the two SCR trigger paths of buried layer to reduce the trigger voltage of ESD protection device, improve the maintenance voltage, reduce the voltage hysteresis margin after the ESD protection device starts, strengthen the ESD robustness of device, its characterized in that: the device mainly comprises a P substrate, an N-type buried layer, an N well, a P well, a drift region, a first N+ injection region, a first P+ injection region, a second N+ injection region, a third N+ injection region, a second P+ injection region, a third P+ injection region, a fourth N+ injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate;
the surface area of the P substrate is provided with the N-type buried layer, the left edge of the P substrate is connected with the left edge of the N-type buried layer, and the right edge of the P substrate is connected with the right edge of the N-type buried layer;
the surface area of the N-type buried layer is sequentially provided with the N-type well and the P-type well from left to right, the left edge of the N-type buried layer is connected with the left edge of the N-type well, the right side of the N-type buried layer is connected with the left side of the P-type well, and the right side of the P-type buried layer is connected with the right edge of the N-type buried layer;
the first N+ injection region and the first P+ injection region are sequentially arranged in the surface region of the N well from left to right;
the second N+ injection region spans the N well and the P well surface area;
the surface area of the P well is sequentially provided with the first polysilicon gate, the first thin gate oxide layer covered by the first polysilicon gate, the third N+ injection region, the drift region and the fourth N+ injection region from left to right, the left side edge of the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate are connected with the right side edge of the second N+ injection region, the right side edge of the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate are connected with the left side edge of the third N+ injection region, and the right side edge of the third N+ injection region is connected with the left side edge of the drift region;
the surface area of the drift region is sequentially provided with the second P+ injection region, the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate from left to right, the left side edge of the second P+ injection region is connected with the left side edge of the drift region, the right side edge of the second P+ injection region is connected with the left side edge of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, and the right side edge of the second thin gate oxide layer covered by the second polysilicon gate is connected with the left side edge of the third P+ injection region;
the third P+ injection region spans the drift region and the P well surface region;
the first N+ injection region is connected with a first metal, the first P+ injection region is connected with a second metal, the first polysilicon gate is connected with a third metal, the third N+ injection region is connected with a fourth metal, the second P+ injection region is connected with a fifth metal, the second polysilicon gate is connected with a sixth metal, the third P+ injection region is connected with a seventh metal, and the fourth N+ injection region is connected with an eighth metal;
the first metal and the second metal are connected with a ninth metal, and a first electrode is led out of the ninth metal and is used as a metal anode of the device;
the fourth metal and the fifth metal are connected with the tenth metal;
the third metal, the sixth metal, the seventh metal and the eighth metal are all connected with the eleventh metal, and a second electrode is led out from the eleventh metal and used as a metal cathode of the device.
The beneficial technical effects of the invention are as follows:
(1) In this embodiment of the present invention, the first n+ injection region, the N well, the second n+ injection region, the first polysilicon gate and the first thin gate oxide covered by the first polysilicon gate, the third n+ injection region, the P well, the second p+ injection region, the second polysilicon gate and the second thin gate oxide covered by the second polysilicon gate, the third p+ injection region and the drift region form a current drain path connected in series between the gate-grounded NMOS and PMOS, under the action of ESD stress, the second n+ injection region, the first polysilicon gate and the first thin gate oxide covered by the first polysilicon gate, and the third n+ injection region form a gate-grounded NMOS, the second p+ injection region, the second polysilicon gate and the second thin gate oxide covered by the second polysilicon gate, the drift region and the third p+ injection region form a gate-grounded NMOS, and when the gate-grounded PMOS is turned on, the gate-grounded PMOS can be quickly turned on, and the gate-grounded NMOS can be quickly turned on, and the voltage can be maintained by adjusting the channel-to-channel voltage.
(2) In this embodiment of the present invention, the third p+ injection region spans the surface areas of the drift region and the P-well, so that on one hand, the third p+ injection region can be used as a source electrode of the grounded-gate PMOS, and on the other hand, the third p+ injection region can be used as an ohmic contact of a parasitic well resistor of the P-well, so that the trigger voltage of the device can be reduced, the first n+ injection region, the first p+ injection region, the N-well, the second n+ injection region, the P-well, the fourth n+ injection region and the third p+ injection region form a surface SCR current drain path, the first n+ injection region, the first p+ injection region, the N-well, the N-type buried layer, the P-well, the fourth n+ injection region and the third p+ injection region form an SCR current drain path, and under the action of ESD stress, when the gate grounded-gate NMOS is opened, the surface SCR current drain path is first conducted, and as the ESD stress is enhanced, the N-type and the P-type avalanche breakdown occurs, the buried layer and the SCR current drain path is enhanced, and the SCR current drain path is enabled.
Drawings
FIG. 1 is a schematic cross-sectional view of an exemplary device structure of the present invention;
FIG. 2 is a circuit diagram of an example device of the present invention for ESD protection;
FIG. 3 is an equivalent circuit diagram of an auxiliary trigger path of an example device of the present invention under ESD stress;
fig. 4 is an equivalent circuit diagram of a dual SCR trigger path of an example device of the present invention under ESD stress.
Detailed Description
The invention is described in further detail below with reference to the attached drawings and detailed description:
the embodiment of the invention designs an ESD protection device with double MOS auxiliary triggering based on an SCR structure, wherein the design device utilizes a gate grounded NMOS tube to reduce the triggering voltage of the device and improve the starting speed of the device; the embedded gate grounding PMOS tube is utilized, and the requirements on the voltage clamping capability of the device in different ESD protection are realized by adjusting the length of a PMOS channel; in addition, the advantage of stronger ESD robustness of the SCR structure is combined, so that under the action of ESD stress, the device provided by the embodiment of the invention not only can form an auxiliary trigger path of which the gate grounding NMOS is connected in series with the PMOS so as to reduce the voltage hysteresis amplitude of the ESD protection device after being started, but also can form a double SCR trigger path positioned on the surface and the buried layer so as to enhance the ESD robustness of the device.
The cross-sectional view of the internal structure of the device of the embodiment of the invention shown in fig. 1 is specifically an ESD protection device based on double MOS auxiliary triggering of an SCR structure, which includes an auxiliary triggering path with a grounded gate NMOS and a PMOS in series and a double SCR triggering path located on the surface and a buried layer, so as to reduce the triggering voltage of the ESD protection device, improve the maintaining voltage, reduce the voltage hysteresis amplitude after the ESD protection device is turned on, and enhance the ESD robustness of the device, and is characterized in that: the device mainly comprises a P substrate 101, an N-type buried layer 102, an N well 103, a P well 104, a drift region 105, a first N+ injection region 106, a first P+ injection region 107, a second N+ injection region 108, a third N+ injection region 109, a second P+ injection region 110, a third P+ injection region 111, a fourth N+ injection region 112, a first polysilicon gate 114, a first thin gate oxide layer 113 covered by the first polysilicon gate 114, a second polysilicon gate 116, and a second thin gate oxide layer 115 covered by the second polysilicon gate 114;
the surface area of the P substrate 101 is provided with the N-type buried layer 102, the left edge of the P substrate 101 is connected with the left edge of the N-type buried layer 102, and the right edge of the P substrate 101 is connected with the right edge of the N-type buried layer 102;
the surface area of the N-type buried layer 102 is sequentially provided with the N-well 103 and the P-well 104 from left to right, the left edge of the N-type buried layer 102 is connected with the left edge of the N-well 103, the right side of the N-well 103 is connected with the left side of the P-well 104, and the right side of the P-well 104 is connected with the right edge of the N-type buried layer 102;
the surface area of the N well 103 is provided with the first n+ injection region 106 and the first p+ injection region 107 in sequence from left to right;
the second n+ implantation region 108 spans the surface areas of the N well 103 and the P well 104;
the surface area of the P-well 104 is provided with the first polysilicon gate 114, the first thin gate oxide layer 113 covered by the first polysilicon gate 114, the third n+ injection region 109, the drift region 105 and the fourth n+ injection region 112 in sequence from left to right, the left side edge of the first polysilicon gate 114 and the first thin gate oxide layer 113 covered by the first polysilicon gate 114 are connected with the right side edge of the second n+ injection region 108, the right side edge of the first polysilicon gate 114 and the first thin gate oxide layer 113 covered by the first polysilicon gate 114 are connected with the left side edge of the third n+ injection region 109, and the right side edge of the third n+ injection region 109 is connected with the left side edge of the drift region 105;
the second p+ injection region 110 and the second polysilicon gate 116 and the second thin gate oxide 115 covered by the second polysilicon gate 116 are sequentially arranged on the surface region of the drift region 105 from left to right, the left edge of the second p+ injection region 110 is connected with the left edge of the drift region 105, the right edge of the second p+ injection region 110 is connected with the left edge of the second polysilicon gate 116 and the second thin gate oxide 115 covered by the second polysilicon gate 116, and the right edge of the second thin gate oxide 115 covered by the second polysilicon gate 116 is connected with the left edge of the third p+ injection region 111;
the third p+ implantation region 111 spans the drift region 105 and the surface region of the P well 104.
As shown in fig. 2, the first n+ implant region 106 is connected to a first metal 201, the first p+ implant region 107 is connected to a second metal 202, the first polysilicon gate 114 is connected to a third metal 203, the third n+ implant region 109 is connected to a fourth metal 204, the second p+ implant region 110 is connected to a fifth metal 205, the second polysilicon gate 116 is connected to a sixth metal 206, the third p+ implant region 111 is connected to a seventh metal 207, and the fourth n+ implant region 112 is connected to an eighth metal 208;
the first metal 201 and the second metal 202 are connected with a ninth metal 209, and a first electrode 212 is led out of the ninth metal 209 and is used as a metal anode of the device;
the fourth metal 204 and the fifth metal 205 are connected to a tenth metal 210;
the third metal 203, the sixth metal 206, the seventh metal 207, and the eighth metal 208 are all connected to an eleventh metal 211, and a second electrode 213 is drawn from the eleventh metal 211 and serves as a metal cathode of the device.
As shown in fig. 3, when ESD stress acts on the device of the embodiment of the present invention, a gate grounding NMOS is formed by the second n+ injection region 108, the first polysilicon gate 114 and the first thin gate oxide layer 113 covered by the first polysilicon gate and the third n+ injection region 109, and a gate grounding PMOS is formed by the second p+ injection region 110, the second polysilicon gate 116 and the second thin gate oxide layer 115 covered by the second polysilicon gate 116, the drift region 105 and the third p+ injection region 111, where the first polysilicon gate 114 and the first thin gate oxide layer 113 covered by the second polysilicon gate 116 and the second thin gate oxide layer 115 covered by the second polysilicon gate are connected with the metal cathode, and when the device is in a critical on state, a downward longitudinal electric field is formed at the interface between the second n+ injection region 108 and the P-well 104, so as to promote electrons in the P-well 104 to accumulate under the first polysilicon gate 114 and the first thin gate oxide layer 113 covered by the second polysilicon gate 116 and form a weak channel, which is beneficial to reduce the trigger voltage of the device. Parasitic well resistance R in the P-well 104 if avalanche current is generated by grounded gate NMOS P When the parasitic NPN triode of the grounded-gate NMOS is turned on, the hole channel formation of the grounded-gate PMOS is promoted due to ohmic contact between the third n+ injection region 109 and the second p+ injection region 110, and the grounded-gate PMOS is rapidly turned on, so that a series auxiliary trigger path of the grounded-gate NMOS and the grounded-gate PMOS is formed, and ESD current is discharged. The grid-grounded PMOS is beneficial to improving the maintaining voltage of the device and reducing the risk of latch-up effect of the device; the requirements of different ESD protection application fields on the voltage clamping capability of the device can be met by adjusting the channel length of the grounded gate PMOS.
As shown in fig. 4, when avalanche breakdown occurs in the reverse biased PN junction formed by the second n+ injection region 108 and the P-well 104, ESD current flows from the N-well 103 into the P-well 104 if atThe parasitic well resistance R P The voltage drop is gradually increased to 0.7V, and the parasitic NPN tube T is formed by the first N+ injection region 106, the N well 103, the P well 104, the third P+ injection region 111 and the fourth N+ injection region 112 3 Emitter forward bias, parasitic NPN tube T 3 Operating in the amplification region. A parasitic PNP tube T is formed by the first P+ injection region 107, the first N+ injection region 106, the N well 103, the second N+ injection region 108, the P well 104 and the third P+ injection region 111 1 The parasitic NPN tube T 3 And the parasitic PNP tube T 1 Forming a positive feedback network and amplifying the parasitic NPN tube T 3 Under the action of (1), the parasitic PNP tube T is accelerated 1 Is turned on by the parasitic NPN tube T 3 And the parasitic PNP tube T 1 The formed surface SCR current bleed path is conductive. With further enhancement of ESD stress, when avalanche breakdown occurs in the reverse bias PN junction formed by the N-type buried layer 102 and the P-well 104, a parasitic PNP transistor T is formed by the first p+ implantation region 107, the first n+ implantation region 106, the N-well 103, the N-type buried layer 102, the P-well 104, and the third p+ implantation region 111 2 Rapidly opening by the parasitic NPN tube T 3 And the parasitic PNP tube T 2 The formed buried layer SCR current discharge path is conducted. At the same time because of the parasitic PNP tube T 1 And the parasitic PNP tube T 2 The base electrode of (a) is all connected with the parasitic NPN tube T 3 The surface SCR current discharge path and the positive feedback network of the buried layer SCR current discharge path have certain mutual weakening effect, which is beneficial to improving the maintenance voltage of the device and enhancing the current discharge capability and ESD robustness of the device.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.
Claims (3)
1. The utility model provides an ESD protection device of supplementary trigger of two MOS based on SCR structure, its includes the supplementary trigger path of gate ground NMOS and gate ground PMOS series connection and is located the surface and the two SCR trigger paths of buried layer to reduce the trigger voltage of ESD protection device, improve the maintenance voltage, reduce the voltage hysteresis margin after the ESD protection device starts, strengthen the ESD robustness of device, its characterized in that: the device mainly comprises a P substrate (101), an N-type buried layer (102), an N well (103), a P well (104), a drift region (105), a first N+ injection region (106), a first P+ injection region (107), a second N+ injection region (108), a third N+ injection region (109), a second P+ injection region (110), a third P+ injection region (111), a fourth N+ injection region (112), a first polysilicon gate (114), a first thin gate oxide layer (113) covered by the first polysilicon gate, a second polysilicon gate (116) and a second thin gate oxide layer (115) covered by the second polysilicon gate;
the surface area of the P substrate (101) is provided with the N-type buried layer (102), the left side edge of the P substrate (101) is connected with the left side edge of the N-type buried layer (102), and the right side edge of the P substrate (101) is connected with the right side edge of the N-type buried layer (102);
the surface area of the N-type buried layer (102) is sequentially provided with the N-type well (103) and the P-type well (104) from left to right, the left edge of the N-type buried layer (102) is connected with the left edge of the N-type well (103), the right side of the N-type buried layer (103) is connected with the left side of the P-type well (104), and the right side of the P-type well (104) is connected with the right edge of the N-type buried layer (102);
the first N+ injection region (106) and the first P+ injection region (107) are sequentially arranged in the surface region of the N well (103) from left to right;
the second N+ injection region (108) spans the N well (103) and the P well (104) surface area;
the surface area of the P well (104) is sequentially provided with the first polysilicon gate (114) and the first thin gate oxide layer (113), the third N+ injection region (109), the drift region (105) and the fourth N+ injection region (112) which are covered by the first polysilicon gate (114), the left side edge of the first thin gate oxide layer (113) which is covered by the first polysilicon gate is connected with the right side edge of the second N+ injection region (108), the right side edge of the first polysilicon gate (114) and the first thin gate oxide layer (113) which is covered by the first polysilicon gate is connected with the left side edge of the third N+ injection region (109), and the right side edge of the third N+ injection region (109) is connected with the left side edge of the drift region (105);
the surface area of the drift region (105) is sequentially provided with the second P+ injection region (110) and the second polysilicon gate (116) and the second thin gate oxide layer (115) covered by the second polysilicon gate from left to right, the left side edge of the second P+ injection region (110) is connected with the left side edge of the drift region (105), the right side edge of the second P+ injection region (110) is connected with the left side edge of the second polysilicon gate (116) and the second thin gate oxide layer (115) covered by the second polysilicon gate (116), and the right side edge of the second thin gate oxide layer (115) covered by the second polysilicon gate is connected with the left side edge of the third P+ injection region (111);
the third P+ injection region (111) spans the drift region (105) and the surface area of the P well (104);
the first N+ injection region (106) is connected with a first metal (201), the first P+ injection region (107) is connected with a second metal (202), the first polysilicon gate (114) is connected with a third metal (203), the third N+ injection region (109) is connected with a fourth metal (204), the second P+ injection region (110) is connected with a fifth metal (205), the second polysilicon gate (116) is connected with a sixth metal (206), the third P+ injection region (111) is connected with a seventh metal (207), and the fourth N+ injection region (112) is connected with an eighth metal (208);
the first metal (201) and the second metal (202) are connected with a ninth metal (209), and a first electrode (212) is led out of the ninth metal (209) and is used as a metal anode of the device;
the fourth metal (204) and the fifth metal (205) are both connected to a tenth metal (210);
the third metal (203), the sixth metal (206), the seventh metal (207) and the eighth metal (208) are all connected with an eleventh metal (211), and a second electrode (213) is led out of the eleventh metal (211) and is used as a metal cathode of the device.
2. The dual MOS assisted triggered ESD protection device of claim 1 wherein: the first n+ injection region (106), the N well (103), the second n+ injection region (108), the first polysilicon gate (114) and the first thin gate oxide layer (113) covered by the first polysilicon gate, the third n+ injection region (109), the P well (104), the second p+ injection region (110), the second polysilicon gate (116) and the second thin gate oxide layer (115) covered by the second polysilicon gate, the third p+ injection region (111) and the drift region (105) form a current drain path between the gate grounding NMOS and the PMOS, under the action of ESD stress, the second n+ injection region (108), the first polysilicon gate (114) and the third n+ injection region (109) form a gate grounding NMOS, the trigger voltage of the device can be reduced, the second polysilicon gate (116) and the second thin gate oxide layer (115) covered by the second polysilicon gate (116) can be rapidly adjusted, and the gate grounding NMOS can be quickly opened when the requirements of the integrated circuit is met, the channel grounding MOS is not met, and the channel grounding region (105) can be rapidly opened.
3. The dual MOS assisted triggered ESD protection device of claim 1 wherein: the third p+ injection region (111) spans the surface regions of the drift region (105) and the P-well (104), on one hand, the third p+ injection region (111) can serve as a source electrode of the grounded-gate PMOS, can improve the maintenance voltage, on the other hand, the third p+ injection region (111) can serve as an ohmic contact of parasitic well resistance of the P-well (104), can reduce the trigger voltage of a device, the first n+ injection region (106), the first p+ injection region (107), the N-well (103), the second n+ injection region (108), the P-well (104), the fourth n+ injection region (112) and the third p+ injection region (111) form a surface SCR current drain path, the first n+ injection region (106), the first p+ injection region (107), the N-well (103), the N-type buried layer (102), the P-well (104), the fourth n+ injection region (112) and the third p+ injection region (111) form an SCR current drain path, and under the action of the ESD stress, when the buried layer is grounded, the surface of the buried layer is in the ESD current drain path, the surface of the buried layer and the SCR current drain path is enhanced, and the surface of the buried layer is opened, and the surface of the ESD current drain path is enhanced.
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| CN108735733B (en) * | 2018-05-30 | 2021-04-13 | 湖南大学 | Silicon controlled electrostatic protector |
| CN112563261B (en) * | 2020-12-11 | 2023-06-27 | 江南大学 | High-voltage protection integrated circuit of Complementary Metal Oxide Semiconductor (CMOS) auxiliary trigger Selective Catalytic Reduction (SCR) structure |
| CN112599522B (en) * | 2020-12-15 | 2023-06-27 | 江南大学 | Quick-opening uniform-conduction bidirectional electrostatic surge protection IC |
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