CN106876389B - ESD protection device with auxiliary trigger SCR structure of resistance-capacitance diode - Google Patents
ESD protection device with auxiliary trigger SCR structure of resistance-capacitance diode Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Abstract
An ESD protection device with a resistance-capacitance diode auxiliary trigger SCR structure can be used for improving the ESD resistance of a chip. The device mainly comprises a P substrate, an N well, a P well, a first N+ injection region, a first P+ injection region, a second N+ injection region, a third N+ injection region, a second P+ injection region, a fourth N+ injection region, a third P+ injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate. Under the action of ESD stress, when the device is subjected to zener breakdown, a parasitic resistance-capacitance coupling auxiliary trigger path formed by a parasitic well resistor, an MOS capacitor and a grid-controlled diode can be formed on one hand so as to reduce the trigger voltage and the starting time of the device, and two SCR structure current discharge paths formed by a parasitic PNP and two NPNs can be formed on the other hand so as to reduce the positive feedback degree of a typical SCR structure and improve the maintaining voltage of the device.
Description
Technical Field
The invention belongs to the field of electrostatic discharge protection of integrated circuits, relates to an ESD protection device, and in particular relates to an ESD protection device with a resistance-capacitance diode auxiliary trigger SCR structure, which can be used for improving the ESD reliability of an on-chip IC.
Background
In daily life, along with the rapid development of multimedia technology, the demands for versatility and portability of electronic systems continue to increase, which forces the electronic systems to have higher integration. Although the integration technology is continuously improved, the high integration of the IC chip greatly improves the circuit performance and the energy consumption efficiency of the system, the reliability problem of the IC chip becomes increasingly serious with the improvement of the integration technology. Particularly, electrostatic discharge (ESD) generated during artificial or machine contact of the IC chip seriously impairs stability and performance of the IC chip. Transient ESD pulses can cause complete loss of chip function and can damage local circuitry of the chip, causing electronic system dysfunction. Moreover, such potential damage is difficult to detect in the inspection, severely affecting the yield of the product. As such, ESD protection circuits for IC chips are increasingly attracting attention of industry and have become a hotspot in the current ESD research field.
At present, some IC chips have been provided with ESD protection circuits, which enhance the ESD protection capability of the IC chip and increase the chip area of the IC, thereby increasing the manufacturing cost of the chip. Compared with common protection structures such as diodes, gate-grounded N-type metal oxide semiconductors (GGNMOS), and the like, the unit area ESD current discharge capability of the Silicon Controlled Rectifier (SCR) structure is stronger, layout area saving and manufacturing cost reduction are facilitated, and therefore the SCR device gradually becomes a research hot spot in the field of on-chip ESD protection of IC chips. However, the SCR structure has the problems of high triggering voltage, low maintenance voltage, easy latch-up generation and the like, and severely restricts the ESD protection application of the SCR structure in the IC chip. In 1993, a.d.w.miller proposed a method of externally connecting a resistor-capacitor coupling circuit to reduce the trigger voltage and on time of an ESD protection device, and improve the on uniformity of the device, thereby improving the ESD protection capability of the device. However, the external resistor-capacitor coupling circuit can greatly increase the layout area of the IC chip, which is unfavorable for the IC chip with increasingly high density integration. The embodiment of the invention provides an ESD protection device with a resistance-capacitance diode auxiliary triggering SCR structure, on one hand, the device is provided with a parasitic resistance-capacitance coupling auxiliary triggering path formed by a parasitic trap resistor, an MOS capacitor and a grid-control diode, so that the extra layout area is not consumed, the advantages of low triggering voltage and short starting time of a resistance-capacitance coupling circuit can be fully utilized, the potential of the N trap parasitic trap resistor can be improved through the conduction of the grid-control diode, and the starting of a current discharging path of the SCR structure is accelerated; on the other hand, the device is also provided with two SCR structure current discharge paths consisting of a parasitic PNP and two NPNs, so that the strong robustness characteristic of the SCR structure can be fully utilized, the current splitting effect of the multiple current discharge paths on the parasitic PNP collector current can be utilized, the positive feedback degree of the SCR structure is reduced, and the maintenance voltage of the device is improved.
Disclosure of Invention
Aiming at the problem that the ESD protection device with the SCR structure has higher trigger voltage and lower maintenance voltage generally, the embodiment of the invention designs the ESD protection device with the resistance-capacitance diode auxiliary trigger SCR structure, fully utilizes the advantages of low trigger voltage and high starting speed of a resistance-capacitance coupling circuit, combines the advantage of strong ESD robustness of the SCR structure, and effectively shunts ESD pulse by forming a multi-current discharging path, so that the design device can form a parasitic resistance-capacitance coupling auxiliary trigger path formed by parasitic well resistance, MOS capacitance and a grid-control diode and two SCR structure current discharging paths formed by a parasitic PNP and two NPNs under the action of ESD stress, thereby reducing the trigger voltage and starting time of the device and improving the maintenance voltage of the device.
The invention is realized by the following technical scheme:
an ESD protection device with a resistive-capacitive diode auxiliary trigger SCR structure, comprising a parasitic resistive-capacitive coupling auxiliary trigger path formed by a parasitic well resistor, a MOS capacitor and a gate-controlled diode and two SCR structure current bleed paths formed by a parasitic PNP and two NPN, to reduce the trigger voltage and the on time of the device and improve the maintenance voltage of the device, characterized in that: the device mainly comprises a P substrate, an N well, a P well, a first N+ injection region, a first P+ injection region, a second N+ injection region, a third N+ injection region, a second P+ injection region, a fourth N+ injection region, a third P+ injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate;
the surface area of the P substrate is sequentially provided with the N well and the P well from left to right, the left side edge of the P substrate is connected with the left side edge of the N well, the right side of the N well is connected with the left side of the P well, and the right side of the P well is connected with the right side edge of the P substrate;
the surface area of the N well is sequentially provided with a first N+ injection region, a first P+ injection region, a second N+ injection region, a first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate from left to right, the left side of the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate is connected with the right side of the second N+ injection region, and the right side of the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate is connected with the left side of the third N+ injection region;
the third N+ injection region spans the N well and the P well surface region, and the right side of the third N+ injection region is connected with the left side of the second P+ injection region;
the surface area of the P well is sequentially provided with the second P+ injection region, the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, the fourth N+ injection region and the third P+ injection region from left to right, the left side of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate is connected with the right side of the second P+ injection region, and the right side of the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate is connected with the left side of the fourth N+ injection region;
the first N+ injection region is connected with the first metal 1, the first P+ injection region is connected with the second metal 1, the second N+ injection region is connected with the third metal 1, the first polysilicon gate is connected with the fourth metal 1, the second polysilicon gate is connected with the fifth metal 1, the fourth N+ injection region is connected with the sixth metal 1, and the third P+ injection region is connected with the seventh metal 1;
the first metal 1 and the second metal 1 are connected with an eighth metal 1, and a first electrode is led out of the eighth metal 1 and is used as a metal anode of the device;
the third metal 1, the fourth metal 1 and the fifth metal 1 are all connected with the ninth metal 1;
the sixth metal 1 and the seventh metal 1 are connected with the tenth metal 1, and a second electrode is led out of the tenth metal 1 and is used as a metal cathode of the device.
The beneficial technical effects of the invention are as follows:
(1) In the embodiment of the invention, the parasitic resistance-capacitance coupling auxiliary trigger path formed by the parasitic well resistance, the MOS capacitor and the gate-controlled diode is formed by the first N+ injection region, the N well, the second N+ injection region, the first polysilicon gate and the first thin gate oxide layer covered by the first polysilicon gate, the third N+ injection region, the second P+ injection region, the second polysilicon gate and the second thin gate oxide layer covered by the second polysilicon gate, the fourth N+ injection region and the P well, and under the action of ESD stress, when the reverse bias PN junction formed by the third N+ injection region and the second P+ injection region breaks down, the parasitic resistance-capacitance coupling auxiliary trigger path is conducted, so that the parasitic resistance R of the N well can be increased n And the trigger current of the ESD protection device with the rc diode-assisted trigger SCR structure, thereby reducing the trigger voltage and on-time of the device.
(2) In the embodiment of the invention, the first n+ injection region, the first p+ injection region, the N well and the third p+ injection region form a parasitic PNP transistor T1, the first n+ injection region, the P well, the fourth n+ injection region and the third p+ injection region form an NPN transistor T2, the third n+ injection region, the second p+ injection region, the P well and the fourth n+ injection region form an NPN transistor T3, the PNP transistor T1, the NPN transistor T2, the NPN transistor T3 and the parasitic well resistor form two SCR structure current drain paths, specifically, an SCR structure current path C1 formed by the PNP transistor T1, the NPN transistor T2 and the parasitic well resistor, and another SCR structure current path C2 formed by the PNP transistor T1, the NPN transistor T3 and the parasitic well resistor are included, and the SCR structure current path C2 can reduce the current path C1, thereby maintaining the positive feedback device.
Drawings
FIG. 1 is a schematic cross-sectional view of an exemplary device structure of the present invention;
FIG. 2 is a circuit diagram of an example device of the present invention for ESD protection;
FIG. 3 is an equivalent circuit diagram of an example device of the present invention when partially turned on under ESD stress;
fig. 4 is an equivalent circuit diagram of an example device of the present invention when fully turned on under ESD stress.
Detailed Description
The invention is described in further detail below with reference to the attached drawings and detailed description:
the embodiment of the invention designs an ESD protection device with a resistance-capacitance diode auxiliary trigger SCR structure, and by utilizing the characteristics of high response speed of a resistance-capacitance coupling circuit, strong ESD robustness of the SCR structure, effective shunt of multiple current discharge paths and the like, the design device can form a parasitic resistance-capacitance coupling auxiliary trigger path formed by parasitic well resistance, MOS capacitance and a grid-control diode and two SCR structure current discharge paths formed by a parasitic PNP and two NPNs under the action of ESD stress, so that the trigger voltage and the starting time of the device are reduced, and the maintenance voltage of the device is improved.
The cross-sectional view of the internal structure of the device of the embodiment of the present invention shown in fig. 1 is a cross-sectional view of the internal structure of the device, specifically an ESD protection device with a rc diode-assisted triggering SCR structure, which includes a parasitic rc coupling auxiliary triggering path formed by a parasitic well resistor, a MOS capacitor and a gate-controlled diode, and two SCR structure current discharging paths formed by a parasitic PNP and two NPN, so as to reduce the triggering voltage and the on time of the device, and improve the maintaining voltage of the device, and is characterized in that: the device mainly comprises a P substrate 101, an N well 102, a P well 103, a first N+ injection region 104, a first P+ injection region 105, a second N+ injection region 106, a third N+ injection region 107, a second P+ injection region 108, a fourth N+ injection region 109, a third P+ injection region 110, a first polysilicon gate 111, a first thin gate oxide layer 112 covered by the first polysilicon gate 111, a second polysilicon gate 113, and a second thin gate oxide layer 114 covered by the second polysilicon gate 111;
the surface area of the P substrate 101 is provided with the N well 102 and the P well 103 in sequence from left to right, the left edge of the P substrate 101 is connected with the left edge of the N well 102, the right side of the N well 102 is connected with the left side of the P well 103, and the right side of the P well 103 is connected with the right edge of the P substrate 101;
the surface area of the N well 102 is provided with the first n+ injection region 104, the first p+ injection region 105, the second n+ injection region 106, the first polysilicon gate 111 and the first thin gate oxide 112 covered by the first polysilicon gate 111 in sequence from left to right, the left side of the first polysilicon gate 111 and the first thin gate oxide 112 covered by the first polysilicon gate are connected with the right side of the second n+ injection region 106, and the right side of the first polysilicon gate 111 and the first thin gate oxide 112 covered by the first polysilicon gate is connected with the left side of the third n+ injection region 107;
the third n+ implantation region 107 spans the surface areas of the N well 102 and the P well 103, and the right side of the third n+ implantation region 107 is connected to the left side of the second p+ implantation region 108;
the surface area of the P-well 103 is sequentially provided with the second p+ injection region 108, the second polysilicon gate 113, the second thin gate oxide 114 covered by the second polysilicon gate 113, the fourth n+ injection region 109 and the third p+ injection region 110 from left to right, wherein the left side of the second polysilicon gate 113 and the second thin gate oxide 114 covered by the second polysilicon gate are connected to the right side of the second p+ injection region 108, and the right side of the second polysilicon gate 113 and the second thin gate oxide 114 covered by the second polysilicon gate are connected to the left side of the fourth n+ injection region 109.
As shown in fig. 2, the first n+ implantation region 104 is connected to the first metal 1 201, the first p+ implantation region 105 is connected to the second metal 1 202, the second n+ implantation region 106 is connected to the third metal 1 203, the first polysilicon gate 111 is connected to the fourth metal 1 204, the second polysilicon gate 113 is connected to the fifth metal 1 205, the fourth n+ implantation region 109 is connected to the sixth metal 1 206, and the third p+ implantation region 110 is connected to the seventh metal 1 207;
the first metal 1 201 and the second metal 1 202 are connected with the eighth metal 1 208, and a first electrode 211 is led out of the eighth metal 1 208 and is used as a metal anode of the device;
the third metal 1 203, the fourth metal 1 204 and the fifth metal 1 205 are all connected with a ninth metal 1 209;
the sixth metal 1 206 and the seventh metal 1 207 are connected to the tenth metal 1 210, and a second electrode 212 is led out from the tenth metal 1 210 and serves as a metal cathode of the device.
As shown in fig. 3, a MOS capacitor NCAP is formed by the N well 102, the second n+ implantation region 106, the first polysilicon gate 111 and the first thin gate oxide 112 covered by the first polysilicon gate 111, and the third n+ implantation region 107, a gate-controlled diode GD is formed by the second p+ implantation region 108, the second polysilicon gate 113 and the second thin gate oxide 114 covered by the second polysilicon gate 113, and the fourth n+ implantation region 109, and when an ESD pulse is applied to the device of the embodiment of the present invention, a parasitic well resistance R of the N well 102 n Parasitic well resistance R of the P-well 103 p There is a resistance-capacitance coupling between the MOS capacitor NCAP and the gate-controlled diode GD.
When ESD pulse passes through the parasitic well resistor R n When reaching the second n+ injection region 106, a forward voltage pulse is obtained above the first polysilicon gate 111 and the first thin gate oxide 112 covered by the same, and the second polysilicon gate 113 and the second thin gate oxide 114 covered by the same, which pulse is favorable for accumulating majority carriers of the N well 102 in the region below the first thin gate oxide 112 to form electronsA conductive channel, at this time, an intrinsic capacitance C exists between the first polysilicon gate 111 and the first thin gate oxide 112 and the N well 102 covered by the first polysilicon gate int Meanwhile, a parasitic capacitance C exists between the first polysilicon gate 111 and the first thin gate oxide 112 and the second n+ implantation region 106 covered by the first polysilicon gate gd1 A parasitic capacitance C exists between the first polysilicon gate 111 and the first thin gate oxide 112 and the third n+ implant region 107 covered by the first polysilicon gate gs1 The intrinsic capacitance C int The parasitic capacitance C gd1 And the parasitic capacitance C gs1 Parallel connection, equivalent available capacitor C NCAP The method comprises the steps of carrying out a first treatment on the surface of the On the other hand, under the action of the ESD pulse, a depletion region composed of negative ion charges is formed in the lower region of the second thin gate oxide 114, and minority carriers of the P-well 103 are attracted to the lower region of the second thin gate oxide 114 to form an electron conduction channel when the ESD pulse is continuously increased, and a parasitic PN junction capacitor C exists between the second polysilicon gate 113 and the second thin gate oxide 114 and the P-well 103 covered by the second polysilicon gate pn Meanwhile, a parasitic capacitance C exists between the second polysilicon gate 113 and the second thin gate oxide 114 and the second p+ implantation region 108 covered by the second polysilicon gate gd2 A parasitic capacitance C exists between the second polysilicon gate 113 and the second thin gate oxide 114 and the fourth n+ implant region 109 that it covers gs2 The parasitic PN junction capacitance C pn The parasitic capacitance C gd2 And the parasitic capacitance C gs2 Parallel connection, equivalent available capacitor C GD . The equivalent capacitance C NCAP And the equivalent capacitance C GD Parallel connection and equivalent total capacitance C can be obtained. From the total capacitance C, the parasitic well resistance R n And the parasitic well resistance R p The resistance-capacitance coupling circuit is formed, so that the opening speed of the device can be improved.
When the ESD pulse is sufficient to cause zener breakdown of the reverse PN junction formed by the third n+ injection region 107 and the second p+ injection region 108, the parasitic rc coupling auxiliary trigger path formed by the parasitic well resistor, the MOS capacitor and the gated diode is rapidly turned on, so that the device contact can be improvedAnd generating current and reducing the trigger voltage of the device. And, the increased trigger current helps to increase the parasitic well resistance R n The voltage drop accelerates the opening of the parasitic PNP transistor T1 formed by the first n+ injection region 104, the first p+ injection region 105, the N well 102, and the third p+ injection region 110, which is beneficial to assisting in triggering the two SCR structure current drain paths formed by the parasitic PNP and the two NPN.
As shown in fig. 4, when ESD pulse continues to act on the device of the present invention and when the parasitic well resistance R n When the potential of the parasitic PNP transistor T1 rises to 0.7V, the collector current thereof flows through the parasitic well resistor R p This increased emitter current in turn promotes an increase in the base current of the parasitic NPN T2 formed by the first n+ implant region 104, the P-well 103, the fourth n+ implant region 109 and the third p+ implant region 110 and the parasitic NPN T3 formed by the third n+ implant region 107, the second p+ implant region 108, the P-well 103 and the fourth n+ implant region 109, in accordance with the current amplification effect of the transistor, and contributes to promoting the parasitic well resistance R p As a result, the two SCR structure current drain paths formed by the PNP transistor T1, the NPN transistor T2, the NPN transistor T3, and the parasitic well resistance can be quickly turned on, specifically including an SCR structure current path C1 formed by the PNP transistor T1, the NPN transistor T2, and the parasitic well resistance, and another SCR structure current path C2 formed by the PNP transistor T1, the NPN transistor T3, and the parasitic well resistance. In addition, since the base electrode of the NPN tube T3 is connected to the collector electrode of the PNP tube T1, the NPN tube T3 splits the current in the positive feedback loop of the SCR structure current path C1 into a part, so that the positive feedback degree of the SCR structure current path C1 can be reduced, and the maintenance voltage of the device is improved.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.
Claims (3)
1. An ESD protection device with a resistive-capacitive diode auxiliary trigger SCR structure, comprising a parasitic resistive-capacitive coupling auxiliary trigger path formed by a parasitic well resistor, a MOS capacitor and a gate-controlled diode and two SCR structure current bleed paths formed by a parasitic PNP and two NPN, to reduce the trigger voltage and the on time of the device and improve the maintenance voltage of the device, characterized in that: the device mainly comprises a P substrate (101), an N well (102), a P well (103), a first N+ injection region (104), a first P+ injection region (105), a second N+ injection region (106), a third N+ injection region (107), a second P+ injection region (108), a fourth N+ injection region (109), a third P+ injection region (110), a first polysilicon gate (111), a first thin gate oxide layer (112) covered by the first polysilicon gate, a second polysilicon gate (113) and a second thin gate oxide layer (114) covered by the second polysilicon gate;
the surface area of the P substrate (101) is sequentially provided with the N well (102) and the P well (103) from left to right, the left side edge of the P substrate (101) is connected with the left side edge of the N well (102), the right side of the N well (102) is connected with the left side edge of the P well (103), and the right side edge of the P well (103) is connected with the right side edge of the P substrate (101);
the surface area of the N well (102) is sequentially provided with a first N+ injection region (104), a first P+ injection region (105), a second N+ injection region (106), a first polysilicon gate (111) and a first thin gate oxide layer (112) covered by the first polysilicon gate (111), wherein the left side of the first polysilicon gate (111) and the first thin gate oxide layer (112) covered by the first polysilicon gate are connected with the right side of the second N+ injection region (106), and the right side of the first polysilicon gate (111) and the first thin gate oxide layer (112) covered by the first polysilicon gate are connected with the left side of the third N+ injection region (107);
the third N+ injection region (107) spans the surface area of the N well (102) and the P well (103), and the right side of the third N+ injection region (107) is connected with the left side of the second P+ injection region (108);
the surface area of the P well (103) is sequentially provided with a second P+ injection region (108), a second polysilicon gate (113) and a second thin gate oxide layer (114), a fourth N+ injection region (109) and a third P+ injection region (110) which are covered by the second polysilicon gate (113), wherein the left side of the second polysilicon gate (113) and the second thin gate oxide layer (114) covered by the second polysilicon gate are connected with the right side of the second P+ injection region (108), and the right side of the second polysilicon gate (113) and the second thin gate oxide layer (114) covered by the second polysilicon gate are connected with the left side of the fourth N+ injection region (109) from left to right;
the first N+ injection region (104) is connected with the first metal 1 (201), the first P+ injection region (105) is connected with the second metal 1 (202), the second N+ injection region (106) is connected with the third metal 1 (203), the first polysilicon gate (111) is connected with the fourth metal 1 (204), the second polysilicon gate (113) is connected with the fifth metal 1 (205), the fourth N+ injection region (109) is connected with the sixth metal 1 (206), and the third P+ injection region (110) is connected with the seventh metal 1 (207);
the first metal 1 (201) and the second metal 1 (202) are connected with the eighth metal 1 (208), and a first electrode (211) is led out of the eighth metal 1 (208) and is used as a metal anode of the device;
the third metal 1 (203), the fourth metal 1 (204) and the fifth metal 1 (205) are all connected with the ninth metal 1 (209);
the sixth metal 1 (206) and the seventh metal 1 (207) are connected with the tenth metal 1 (210), and a second electrode (212) is led out from the tenth metal 1 (210) and is used as a metal cathode of the device.
2. An ESD protection device having a rc diode assisted triggered SCR structure as claimed in claim 1, wherein: the first n+ injection region (104), the N well (102), the second n+ injection region (106), the first polysilicon gate (111), the first thin gate oxide layer (112) covered by the first polysilicon gate, the third n+ injection region (107), the second p+ injection region (108), the second polysilicon gate (113) and the second thin gate oxide layer (114) covered by the second polysilicon gate, the fourth n+ injection region (109) and the P well (103) form the parasitic well resistor, the MOS capacitor and the gate control diodeUnder the action of ESD stress, when zener breakdown occurs in a reverse bias PN junction formed by the third N+ injection region (107) and the second P+ injection region (108), the parasitic resistance-capacitance coupling auxiliary trigger path is conducted, so that the parasitic well resistance R of the N well (102) can be increased n And the trigger current of the ESD protection device with the rc diode-assisted trigger SCR structure, thereby reducing the trigger voltage and on-time of the device.
3. An ESD protection device having a rc diode assisted triggered SCR structure as claimed in claim 1, wherein: the parasitic PNP tube T1 is formed by the first N+ injection region (104), the first P+ injection region (105), the N well (102) and the third P+ injection region (110), the NPN tube T2 is formed by the first N+ injection region (104), the P well (103), the fourth N+ injection region (109) and the third P+ injection region (110), the NPN tube T3 is formed by the third N+ injection region (107), the second P+ injection region (108), the P well (103) and the fourth N+ injection region (109), the two SCR structure current paths are formed by the PNP tube T1, the NPN tube T2, the NPN tube T3 and the parasitic well resistor, the SCR structure current path C1 is formed by the PNP tube T1, the NPN tube T2 and the parasitic well resistor, and the SCR structure current path C2 is formed by the PNP tube T1, the NPN tube T3 and the parasitic well resistor, and the SCR structure current path C2 is formed by the NPN tube T3 and the parasitic well resistor, and the SCR structure current path C2 is maintained, and the positive feedback device C2 is improved.
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| CN107658295B (en) * | 2017-11-10 | 2023-09-29 | 江南大学 | Bidirectional ESD protection anti-latch-up device with fully symmetrical double-gate control diode triggering SCR structure |
| CN108987388B (en) * | 2018-07-18 | 2020-07-24 | 江南大学 | Transient voltage suppressor with low-voltage low-capacitance triggering characteristic |
| CN113571513B (en) * | 2021-09-23 | 2022-01-04 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
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| CN101246885A (en) * | 2008-03-05 | 2008-08-20 | 浙江大学 | Controllable silicon used for electrostatic discharge protection |
| CN102208455A (en) * | 2011-03-29 | 2011-10-05 | 上海宏力半导体制造有限公司 | Silicon controlled rectifier |
| CN104241277A (en) * | 2014-09-28 | 2014-12-24 | 江南大学 | SCR (semiconductor control rectifier) device with imbedded GDPMOS high in maintaining voltage |
| CN105390491A (en) * | 2015-12-17 | 2016-03-09 | 江南大学 | LDMOS-SCR device with source-end embedded finger NMOS |
| CN206727069U (en) * | 2017-04-28 | 2017-12-08 | 江南大学 | A kind of ESD protection device with resistor capacitor diode auxiliary triggering SCR structure |
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