CN109698195B - Small-hysteresis bidirectional transient voltage suppressor and application thereof - Google Patents
Small-hysteresis bidirectional transient voltage suppressor and application thereof Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 84
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- 229910045601 alloy Inorganic materials 0.000 claims description 3
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- 238000012423 maintenance Methods 0.000 abstract 1
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- 239000000243 solution Substances 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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Abstract
The invention discloses a small-hysteresis bidirectional transient voltage suppressor and application thereof, and belongs to the technical field of integrated circuit semiconductors. The device comprises a P substrate, a first high-voltage deep N well, a second high-voltage deep N well, a first N well, a second N well, a third N well, a fourth N well, a first P well, a second P well, a third P well, a first N + injection region, a first P + injection region, a second P + injection region, a third P + injection region, a second N + injection region, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate, and a second thin gate oxide layer covered by the second polysilicon gate. Under the action of ESD stress, on one hand, an auxiliary trigger SCR path is formed by connecting an off-state PMOS and an on-state PMOS in series, so that the trigger voltage of the device is reduced, the robustness is improved, on the other hand, the current discharge path is prolonged through a high-voltage deep N well and a floating N well, the positive feedback degree of the SCR structure is reduced, the maintenance voltage is improved, and the device is in a symmetrical structure and has the functions of bidirectional overvoltage, overcurrent protection or surge resistance.
Description
Technical Field
The invention relates to a small-hysteresis bidirectional transient voltage suppressor and application thereof, belonging to the technical field of integrated circuit semiconductors.
Background
With the rapid development of electronic information technology, the gate oxide size of an Integrated Circuit (IC) internal device is smaller and smaller, the circuit integration level is higher and higher, and the phenomenon that a semiconductor device is damaged by static electricity is more and more serious. Because the action time of Electro-Static discharge (ESD) is short, the instant release energy is large, and the instant impact on the circuit is easy to cause the functional disorder, the junction breakdown or the metal melting inside the circuit. For IC chips, a minor ESD event may cause severe damage or even permanent failure. Because the ESD phenomenon has the characteristics of potential, randomness, complexity and the like, and along with the whole service cycle of the electronic product, if the internal part of the chip or the electronic product does not have proper ESD protection measures, the service life of the chip or the electronic product and the reliability of the system face a serious threat. Therefore, it is important to establish proper over-voltage and over-current in the IC chip or in the electronic system, to suppress the transient pulse electrical stress, and to improve the system reliability of the IC and the electronic product.
In the transient pulse suppression process, a Silicon Controlled Rectifier (SCR) has the characteristics of high ESD current discharge efficiency per unit area, low parasitic capacitance, strong robustness and the like, is widely applied, and gradually becomes a research hotspot in the fields of ESD protection and transient surge suppression. However, the SCR has problems of too high trigger voltage, too low sustain voltage, easy latch-up, etc., and is limited in engineering application. In the prior art, a gate-grounded NMOS (NMOS transistor) transistor is embedded in an SCR, so that the trigger voltage and the turn-on time of a device can be effectively reduced, but the device with the structure can only resist the striking of an overstress pulse in a certain fixed direction, and a unidirectional discharge current path is provided; when the device is impacted by the over stress in the reverse direction, the device is equivalent to a forward biased diode, and the leakage problem exists.
Disclosure of Invention
The invention provides a small hysteresis bidirectional transient voltage suppressor and application thereof, and aims to solve the problems that the traditional SCR has overhigh trigger voltage and overlow holding voltage, is easy to generate latch-up risk and has unidirectional overstress protection limitation.
The suppressor is composed of a P substrate (101), a first high-voltage deep N well (102), a second high-voltage deep N well (103), a first N well (104), a first P well (105), a second N well (106), a second P well (107), a third N well (108), a third P well (109), a fourth N well (110), a first N + injection region (111), a first P + injection region (112), a second P + injection region (113), a third P + injection region (114), a second N + injection region (115), a first polysilicon gate (116) and a first thin gate oxide layer (117) covered by the first polysilicon gate (116), a second polysilicon gate (118) and a second thin gate oxide layer (119) covered by the second polysilicon gate (118);
a first high-pressure deep N well (102) and a second high-pressure deep N well (103) are sequentially arranged in the surface area of the P substrate (101) from left to right, the left edge of the P substrate (101) is connected with the left side of the first high-pressure deep N well (102), and the right edge of the P substrate (101) is connected with the right side of the second high-pressure deep N well (103); a space is arranged between the first high-voltage deep N well (102) and the second high-voltage deep N well (103);
a first N well (104) and a first P well (105) are sequentially arranged on the surface area of the first high-voltage deep N well (102) from left to right, the left side of the first N well (104) is connected with the left side of the first high-voltage deep N well (102), and the right side of the first N well (104) is connected with the left side of the first P well (105);
a second N well (106) spans the surface areas of the first high-voltage deep N well (102) and the P substrate (101), the right side of the first P well (105) is connected with the left side of the second N well (106), and the right side of the second N well (106) is connected with the left side of the second P well (107);
the third N well (108) spans the surface areas of the P substrate (101) and the second high-voltage deep N well (103), and the right side of the second P well (107) is connected with the left side of the third N well (108);
a third P well (109) and a fourth N well (110) are sequentially arranged in the surface area of the second high-voltage deep N well (103) from left to right, the right side of the third N well (108) is connected with the left side of the third P well (109), the right side of the third P well (109) is connected with the left side of the fourth N well (110), and the right side of the fourth N well (110) is connected with the right side of the second high-voltage deep N well (103);
a first N + injection region (111), a first P + injection region (112), a first polysilicon gate (116) and a first thin gate oxide layer (117) covered by the first polysilicon gate (116) are sequentially arranged in the surface region of the first N well (104) from left to right, the right side of the first P + injection region (112) is connected with the first polysilicon gate (116) and the left side of the first thin gate oxide layer (117) covered by the first polysilicon gate (116), and the right side of the first polysilicon gate (116) and the first thin gate oxide layer (117) covered by the first polysilicon gate (116) are connected with the left side of the second P + injection region (113); a space is arranged between the first N + injection region (111) and the first P + injection region (112);
a second P + injection region (113) crosses the surface regions of the first N well (104), the first P well (105), the second N well (106), the second P well (107), the third N well (108), the third P well (109) and the fourth N well (110);
a second polysilicon gate (118) and a second thin gate oxide layer (119), a third P + injection region (114) and a second N + injection region (115) which are covered by the second polysilicon gate are sequentially arranged in the surface region of the fourth N well (110) from left to right, the right side of the second P + injection region (113) is connected with the second polysilicon gate (118) and the left side of the second thin gate oxide layer (119) which is covered by the second polysilicon gate (118), and the right side of the second polysilicon gate (118) and the right side of the second thin gate oxide layer (119) which is covered by the second polysilicon gate are connected with the left side of the third P + injection region (114); a space is arranged between the third P + injection region (114) and the second N + injection region (115);
the first N + injection region (111) is connected with the first metal 1(201), the first P + injection region (112) is connected with the second metal 1(202), the first polysilicon gate (116) is connected with the third metal 1(203), the second polysilicon gate (118) is connected with the fourth metal 1(204), the third P + injection region (114) is connected with the fifth metal 1(205), and the second N + injection region (115) is connected with the sixth metal 1 (206);
the first metal 1(201), the second metal 1(202) and the third metal 1(203) are connected with the seventh metal 1(207), and a first electrode (301) is led out from the seventh metal 1(207) and is used as a metal anode of a suppressor;
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are all connected with the eighth metal 1(208), and a second electrode (302) is led out from the eighth metal 1(208) and is used as a metal cathode of the suppressor.
Optionally, the first P + injection region (112), the first N well (104), the first polysilicon gate (116), the first thin gate oxide layer (117) covered by the first polysilicon gate, and the second P + injection region (113) form an off-state PMOS, the second P + injection region (113), the second polysilicon gate (118), the second thin gate oxide layer (119) covered by the second polysilicon gate, the third P + injection region (114), and the fourth N well (110) form an on-state PMOS, and the off-state PMOS and the on-state PMOS form a series auxiliary trigger SCR current path, so as to reduce the trigger voltage of the device, and improve the holding voltage of the suppressor and the ESD robustness.
Optionally, an SCR current path is formed by the first P + injection region (112), the first N well (104), the first high-voltage deep N well (102), the second N well (106), the second P + injection region (113), the third N well (108), the second high-voltage deep N well (103), the fourth N well (110), and the second N + injection region (115), and the first P well (105), the second N well (106), the second P well (107), the third N well (108), and the third P well (109) extend a current leakage path inside the device, so that the positive feedback degree of the parasitic SCR structure is weakened, and the holding voltage of the suppressor is improved.
Optionally, the first N well (104), the first P well (105), the second N well (106), the second P well (107), the third N well (108), the third P well (109), the fourth N well (110), the first N + injection region (111), the first P + injection region (112), the second P + injection region (113), the third P + injection region (114), the second N + injection region (115), the first polysilicon gate (116), the first thin gate oxide layer (117) and the second polysilicon gate (118) covering the first and second thin gate oxide layers (119) thereof are all symmetrical about the axis center with the second P + injection region (113) and the second P well (107) as the axis center in the top view layout of the suppressor, and when the first electrode and the second electrode of the suppressor are under the forward electrical stress and the reverse electrical stress, the electrical characteristics of the interior of the suppressor under the forward electrical stress and the electrical stress under the reverse electrical stress are completely the same as the electrical characteristics under the reverse electrical stress, has the functions of bidirectional overvoltage protection, overcurrent protection or surge resistance.
Optionally, the metal 1 material is a single metal or an alloy of two or more metals.
Alternatively, a forward or reverse electrical stress may be applied between the first and second electrodes of the suppressor.
It is a second object of the present invention to provide an integrated circuit comprising the above-mentioned small hysteresis bi-directional transient voltage suppressor.
Optionally, the integrated circuit is applied to overvoltage, overcurrent and surge protection of an electronic product.
A third object of the present invention is to provide the application of the above-mentioned small hysteresis bi-directional transient voltage suppressor and/or integrated circuit in the field of semiconductor electronics and/or electronic engineering.
Optionally, the technical field of semiconductor electronics and/or electronic engineering includes the field of automotive electronics and/or avionics.
The invention has the beneficial effects that:
according to the small-hysteresis bidirectional transient voltage suppressor provided by the embodiment of the invention, on one hand, the two PMOS devices are embedded in the device to form the auxiliary trigger SCR current path formed by connecting the off-state PMOS device and the on-state PMOS device in series, so that the characteristic of strong robustness of the SCR can be fully utilized, the trigger voltage of the device can be reduced by utilizing the MOS tube, the hysteresis window of the device can be reduced, and meanwhile, the fully symmetrical device structure can realize the bidirectional overstress protection function. On the other hand, the device introduces the leakage current into the device through the high-voltage deep N well and the floating P well and the N well, so that the current path can be prolonged, the maintaining voltage of the device is improved, the current density on the surface of the device can be dispersed, the thermal effect is prevented from being excessively concentrated on the surface of the device, and the robustness of the device is further enhanced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a device structure of the present invention.
Fig. 2 is a diagram of the metal connections of the device of the present invention.
Fig. 3 is an equivalent circuit diagram of SCR bleed current under ESD stress for the device of the present invention.
Fig. 4 is an equivalent circuit diagram of the extended SCR bleed current under ESD stress for the device of the present invention.
Fig. 5 is a circuit diagram of the device of the present invention as applied in an integrated circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment is as follows:
the embodiment of the invention provides a small hysteresis bidirectional transient voltage suppressor with embedded double PMOS, which is characterized in that an auxiliary trigger path of SCR is formed by embedding an on-state NMOS and an off-state PMOS to reduce the trigger voltage of a device, a floating N well is added, a current path is introduced into the device through a high-voltage deep N well, the positive feedback of the SCR is weakened, the maintaining voltage of the device is improved, the voltage clamping capability of the device is enhanced, and the bidirectional ESD protection or anti-surge function is realized.
Fig. 1 is a schematic structural cross-sectional view of an suppressor device of the present invention, specifically, an ESD protection device with a bidirectional LVTSCR structure, which is mainly composed of a P substrate 101, a first high-voltage deep N well 102, a second high-voltage deep N well 103, a first N well 104, a first P well 105, a second N well 106, a second P well 107, a third N well 108, a third P well 109, a fourth N well 110, a first N + implantation region 111, a first P + implantation region 112, a second P + implantation region 113, a third P + implantation region 114, a second N + implantation region 115, a first polysilicon gate 116, a first thin gate oxide layer 117 covering the first polysilicon gate 116, a second polysilicon gate 118, and a second thin gate oxide layer 119 covering the second polysilicon gate;
a first high-voltage deep N well 102 and a second high-voltage deep N well 103 are sequentially arranged in the surface region of the P substrate 101 from left to right, the left edge of the P substrate 101 is connected with the left side of the first high-voltage deep N well 102, and the right edge of the P substrate 101 is connected with the right side of the second high-voltage deep N well 103; a space is provided between the first high-voltage deep N-well 102 and the second high-voltage deep N-well 103.
A first N well 104 and a first P well 105 are sequentially arranged on the surface area of the first high-voltage deep N well 102 from left to right, the left side of the first N well 104 is connected with the left side of the first high-voltage deep N well 102, and the right side of the first N well 104 is connected with the left side of the first P well 105;
the second N well 106 crosses over the surface areas of the first high-voltage deep N well 102 and the P substrate 101, the right side of the first P well 105 is connected with the left side of the second N well 106, and the right side of the second N well 106 is connected with the left side of the second P well 107;
a third N well 108 spans the surface areas of the P substrate 101 and the second high-voltage deep N well 103, and the right side of the second P well 107 is connected with the left side of the third N well 108;
a third P well 109 and a fourth N well 110 are sequentially arranged on the surface area of the second high-voltage deep N well 103 from left to right, the right side of the third N well 108 is connected with the left side of the third P well 109, the right side of the third P well 109 is connected with the left side of the fourth N well 110, and the right side of the fourth N well 110 is connected with the right side of the second high-voltage deep N well 103;
a first N + injection region 111, a first P + injection region 112, a first polysilicon gate 116 and a first thin gate oxide layer 117 covered by the first polysilicon gate 116 are sequentially arranged in the surface region of the first N well 104 from left to right, the right side of the first P + injection region 112 is connected with the left side of the first polysilicon gate 116 and the first thin gate oxide layer 117 covered by the first polysilicon gate 116, and the right side of the first polysilicon gate 116 and the first thin gate oxide layer 117 covered by the first polysilicon gate are connected with the left side of the second P + injection region 113;
wherein there is a spacing between the first N + implant region 111 and the first P + implant region 112.
A second P + implantation region 113 spans surface regions of the first N well 104, the first P well 105, the second N well 106, the second P well 107, the third N well 108, the third P well 109, and the fourth N well 110;
a second polysilicon gate 118 and a second thin gate oxide layer 119, a third P + injection region 114 and a second N + injection region 115 which are covered by the second polysilicon gate are sequentially arranged in the surface region of the fourth N well 110 from left to right, the right side of the second P + injection region 113 is connected with the left side of the second polysilicon gate 118 and the second thin gate oxide layer 119 which is covered by the second polysilicon gate 118, and the right side of the second polysilicon gate 118 and the second thin gate oxide layer 119 which is covered by the second polysilicon gate are connected with the left side of the third P + injection region 114;
wherein there is a spacing between the third P + implant region 114 and the second N + implant region 115.
As shown in fig. 2, the first N + implantation region 111 is connected to the first metal 1201, the first P + implantation region 112 is connected to the second metal 1202, the first polysilicon gate 116 is connected to the third metal 1203, the second polysilicon gate 118 is connected to the fourth metal 1204, the third P + implantation region 114 is connected to the fifth metal 1205, and the second N + implantation region 115 is connected to the sixth metal 1206;
the first metal 1201, the second metal 1202 and the third metal 1203 are all connected with the seventh metal 1207, and the first electrode 301 is led out from the seventh metal 1207 and is used as a metal anode of the suppressor;
the fourth metal 1204, the fifth metal 1205 and the sixth metal 1206 are all connected to an eighth metal 1208, from which eighth metal 1208 the second electrode 302 is led, acting as a metal cathode of the suppressor.
The metal 1 is made of a single metal or an alloy of two or more metals:
as shown in fig. 3, the off-state PMOS formed by the first P + injection region 112, the first N well 104, the first polysilicon gate 116 and the first thin gate oxide 117 and the second P + injection region 113 covered by the first P + injection region 112, and the on-state PMOS formed by the second P + injection region 113, the second polysilicon gate 118 and the second thin gate oxide 119, the third P + injection region 114 and the fourth N well 110 covered by the second P + injection region, are connected in series, when the first electrode of the suppressor of the present invention is connected to a high potential and the second electrode is grounded, a longitudinal electric field is formed between the second polysilicon gate 118 and the second thin gate oxide 119 covered by the second polysilicon gate and the second N well 110, so as to promote the accumulation of holes in the second N well 110 under the second thin gate oxide 119, when the applied electrical stress is further increased, the off-state PMOS is turned on, when the avalanche current drops to 0.7V in the well resistance of the first N well 104 or the fourth N well 110, and the parasitic NPN triode T1 and the PNP triode T2 are conducted to form a current path for connecting the on-state PMOS and the off-state PMOS in series to assist in triggering the SCR, and the SCR is conducted, so that the triggering voltage of the suppressor is reduced, and the over-current stress robustness of the suppressor is enhanced.
As shown in fig. 4, when the first electrode of the device of the present invention is connected to a high potential and the second electrode is grounded, the second N well 106 obtains a high potential through the first N + injection region 111, the first N well 104 and the high voltage deep N well 102, forms a reverse bias junction with the second P + injection region 113, when the off-state PMOS and the on-state PMOS are turned on to form a parasitic SCR and drain current, a voltage drop of 0.7V has occurred between the first P + injection region 112 and the first N well 104, and between the second P + injection region 113 and the fourth N well 110, and the parasitic NPN transistor T3 formed by the first N well 104, the first high voltage deep N well 102, the second N well 106, the second P + injection region 113, the third N well 108, the second high voltage deep N well 103, the fourth N well 110 and the second N + injection region 115 is turned on, and the internal current path of the device is extended by the first high voltage deep N well 102, the first P105, the second N well 106, the second P well 107, the third N well 108 and the second N well 109, the positive feedback degree of a parasitic SCR structure is weakened, and the holding voltage of the suppressor can be improved.
Example two
The present embodiment provides an integrated circuit including the dual PMOS embedded small hysteresis bi-directional transient voltage suppressor according to the first embodiment, which can be applied to over-voltage, over-current and surge protection of an automotive or avionics system.
As shown in fig. 5, in the integrated circuit including the suppressor of the present invention, the module 1 is a core circuit of the present invention, and the module 2 is a multi-finger parallel circuit of the small hysteresis bi-directional transient suppressor with embedded dual PMOS, which can improve the integrated circuit ESD robustness of the suppressor of the present invention, reduce the on-resistance, and enhance the voltage clamping capability of the circuit. The module 3 is a multistage cascade circuit of a small hysteresis bidirectional transient suppressor embedded with double PMOS, and can enlarge the multi-voltage domain protection function of the integrated circuit of the suppressor. The module 4 is a signal conversion or control circuit between the embedded double-PMOS small-hysteresis bidirectional transient suppressor and a peripheral circuit, so that the application flexibility and the application range of the integrated circuit of the suppressor are enhanced.
1. In the embodiment of the invention, a first P + injection region, a first N well, a first polysilicon gate, a first thin gate oxide layer covered by the first polysilicon gate, and a second P + injection region form an off-state PMOS, a second P + injection region, a second polysilicon gate, a second thin gate oxide layer covered by the second polysilicon gate, a third P + injection region, and a fourth N well form an on-state PMOS, and the off-state PMOS and the on-state PMOS form a series auxiliary trigger SCR current path, so that the trigger voltage of the suppressor is reduced, and the holding voltage and the ESD robustness of the suppressor are improved.
2. In the embodiment of the invention, a first P + injection region, a first N well, a first high-voltage deep N well, a second P + injection region, a third N well, a second high-voltage deep N well, a fourth N well and a second N + injection region form an SCR current path, and the first P well, the second N well, the second P well, the third N well and the third P well can prolong the current release path in the suppressor, weaken the positive feedback degree of a parasitic SCR structure and improve the holding voltage of the suppressor.
3. In the embodiment of the invention, a first N well, a first P well, a second N well, a second P well, a third N well, a third P well, a fourth N well, a first N + injection region, a first P + injection region, a second P + injection region, a third P + injection region, a second N + injection region, a first polysilicon gate and a first thin gate oxide layer covered by the first polysilicon gate, a second polysilicon gate and a second thin gate oxide layer covered by the second polysilicon gate are arranged in a plan view layout of the device, the second P + injection region and the second P well are used as the axial centers and have the characteristic of an axial center full-symmetrical structure, when the first electrode and the second electrode of the suppressor are arranged, no matter forward and reverse electrical stress is applied, the internal electrical characteristics of the suppressor under the action of the forward electrical stress are completely the same as the internal electrical characteristics under the action of the reverse electrical stress, and the suppressor has the functions of bidirectional overvoltage protection, overcurrent protection or surge resistance.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. The small hysteresis bidirectional transient voltage suppressor is characterized by comprising a P substrate (101), a first high-voltage deep N well (102), a second high-voltage deep N well (103), a first N well (104), a first P well (105), a second N well (106), a second P well (107), a third N well (108), a third P well (109), a fourth N well (110), a first N + injection region (111), a first P + injection region (112), a second P + injection region (113), a third P + injection region (114), a second N + injection region (115), a first polysilicon gate (116), a first thin gate oxide layer (117) covered by the first polysilicon gate (116), a second polysilicon gate (118) and a second thin gate oxide layer (119) covered by the second polysilicon gate (118);
a first high-pressure deep N well (102) and a second high-pressure deep N well (103) are sequentially arranged in the surface area of the P substrate (101) from left to right, the left edge of the P substrate (101) is connected with the left side of the first high-pressure deep N well (102), and the right edge of the P substrate (101) is connected with the right side of the second high-pressure deep N well (103); a space is arranged between the first high-voltage deep N well (102) and the second high-voltage deep N well (103);
a first N well (104) and a first P well (105) are sequentially arranged on the surface area of the first high-voltage deep N well (102) from left to right, the left side of the first N well (104) is connected with the left side of the first high-voltage deep N well (102), and the right side of the first N well (104) is connected with the left side of the first P well (105);
a second N well (106) spans the surface areas of the first high-voltage deep N well (102) and the P substrate (101), the right side of the first P well (105) is connected with the left side of the second N well (106), and the right side of the second N well (106) is connected with the left side of the second P well (107);
the third N well (108) spans the surface areas of the P substrate (101) and the second high-voltage deep N well (103), and the right side of the second P well (107) is connected with the left side of the third N well (108);
a third P well (109) and a fourth N well (110) are sequentially arranged in the surface area of the second high-voltage deep N well (103) from left to right, the right side of the third N well (108) is connected with the left side of the third P well (109), the right side of the third P well (109) is connected with the left side of the fourth N well (110), and the right side of the fourth N well (110) is connected with the right side of the second high-voltage deep N well (103);
a first N + injection region (111), a first P + injection region (112), a first polysilicon gate (116) and a first thin gate oxide layer (117) covered by the first polysilicon gate (116) are sequentially arranged in the surface region of the first N well (104) from left to right, the right side of the first P + injection region (112) is connected with the first polysilicon gate (116) and the left side of the first thin gate oxide layer (117) covered by the first polysilicon gate (116), and the right side of the first polysilicon gate (116) and the first thin gate oxide layer (117) covered by the first polysilicon gate (116) are connected with the left side of the second P + injection region (113); a space is arranged between the first N + injection region (111) and the first P + injection region (112);
a second P + injection region (113) crosses the surface regions of the first N well (104), the first P well (105), the second N well (106), the second P well (107), the third N well (108), the third P well (109) and the fourth N well (110);
a second polysilicon gate (118) and a second thin gate oxide layer (119), a third P + injection region (114) and a second N + injection region (115) which are covered by the second polysilicon gate are sequentially arranged in the surface region of the fourth N well (110) from left to right, the right side of the second P + injection region (113) is connected with the second polysilicon gate (118) and the left side of the second thin gate oxide layer (119) which is covered by the second polysilicon gate (118), and the right side of the second polysilicon gate (118) and the right side of the second thin gate oxide layer (119) which is covered by the second polysilicon gate are connected with the left side of the third P + injection region (114); a space is arranged between the third P + injection region (114) and the second N + injection region (115);
the first N + injection region (111) is connected with the first metal 1(201), the first P + injection region (112) is connected with the second metal 1(202), the first polysilicon gate (116) is connected with the third metal 1(203), the second polysilicon gate (118) is connected with the fourth metal 1(204), the third P + injection region (114) is connected with the fifth metal 1(205), and the second N + injection region (115) is connected with the sixth metal 1 (206);
the first metal 1(201), the second metal 1(202) and the third metal 1(203) are connected with the seventh metal 1(207), and a first electrode (301) is led out from the seventh metal 1(207) and is used as a metal anode of a suppressor;
the fourth metal 1(204), the fifth metal 1(205) and the sixth metal 1(206) are all connected with the eighth metal 1(208), and a second electrode (302) is led out from the eighth metal 1(208) and is used as a metal cathode of the suppressor.
2. The small hysteresis bi-directional transient voltage suppressor of claim 1, wherein an off-state PMOS is formed by the first P + implantation region (112), the first N-well (104), the first polysilicon gate (116) and the first thin gate oxide (117) and the second P + implantation region (113) covered by the first polysilicon gate, an on-state PMOS is formed by the second P + implantation region (113), the second polysilicon gate (118) and the second thin gate oxide (119) covered by the second polysilicon gate, the third P + implantation region (114) and the fourth N-well (110), and a series auxiliary trigger SCR current path is formed by the off-state PMOS and the on-state PMOS to reduce the trigger voltage of the device and improve the holding voltage and ESD robustness of the suppressor.
3. The small hysteresis bi-directional transient voltage suppressor according to claim 1, wherein an SCR current path is formed by the first P + injection region (112), the first N-well (104), the first high-voltage deep N-well (102), the second N-well (106), the second P + injection region (113), the third N-well (108), the second high-voltage deep N-well (103), the fourth N-well (110), and the second N + injection region (115), and the first P-well (105), the second N-well (106), the second P-well (107), the third N-well (108), and the third P-well (109) extend a current leakage path inside the device, weaken a positive feedback degree of a parasitic SCR structure, and improve a holding voltage of the suppressor.
4. The small hysteresis bi-directional transient voltage suppressor according to claim 1, wherein the first N well (104), the first P well (105), the second N well (106), the second P well (107), the third N well (108), the third P well (109), the fourth N well (110), the first N + injection region (111), the first P + injection region (112), the second P + injection region (113), the third P + injection region (114), the second N + injection region (115), the first polysilicon gate (116) and the first and second polysilicon gates (117, 118) covering the first and second polysilicon gates and the second thin gate oxide layer (119) covering the first and second polysilicon gates are centered on the second P + injection region (113) and the second P well (107) in a top view of the suppressor, and have a fully symmetric axial center structure characteristic when between the first and second electrodes of the suppressor, no matter the forward and reverse electrical stress is applied, the internal electrical characteristics of the suppressor under the action of the forward electrical stress are completely the same as the internal electrical characteristics under the action of the reverse electrical stress, and the suppressor has the functions of bidirectional overvoltage protection, overcurrent protection or surge resistance.
5. The small hysteresis bi-directional transient voltage suppressor of claim 1, wherein the metal 1 material is a single metal or an alloy of two or more metals.
6. The small hysteretic bi-directional transient voltage suppressor of any of claims 1 to 5, wherein electrical stress in either a forward or reverse direction can be applied between the first and second electrodes of said suppressor.
7. An integrated circuit comprising the small hysteretic bi-directional transient voltage suppressor of any of claims 1-6.
8. The integrated circuit of claim 7, wherein the integrated circuit is applied to over-voltage, over-current and surge protection of an electronic product.
9. Use of the small hysteresis bi-directional transient voltage suppressor of any of claims 1 to 6 and/or the integrated circuit of any of claims 7 to 8 in the field of semiconductor electronics and/or electronic engineering.
10. Use according to claim 9, wherein the field of semiconductor electronics and/or electronic engineering comprises the field of automotive electronics and/or avionics.
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| CN110880500B (en) * | 2019-11-19 | 2021-12-03 | 江南大学 | Bidirectional high-voltage ESD protection device of full-symmetry LDMOS trigger SCR structure |
| CN114843262B (en) * | 2022-05-09 | 2022-11-08 | 江南大学 | Electrostatic surge protection circuit for low-power-consumption power management chip |
| CN116093153B (en) * | 2023-04-10 | 2023-07-21 | 江苏应能微电子股份有限公司 | Low capacitance bi-directional SCR transient suppression device with high sustain voltage |
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| US9293460B2 (en) * | 2012-08-24 | 2016-03-22 | Texas Instruments Incorporated | ESD protection device with improved bipolar gain using cutout in the body well |
| CN102969312B (en) * | 2012-12-18 | 2015-02-04 | 江南大学 | High-voltage ESD (electro-static discharge) protective device triggered by bidirectional substrate |
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