CN212485327U - Power device electrostatic discharge protection circuit - Google Patents

Abstract

The utility model relates to a power device electrostatic discharge protection circuit has increased an N + bridge region at N type well, second P type well, utilizes the breakdown in N + bridge region to reduce the trigger point voltage of second P type well specially. And a third P + region is arranged in the N-type well, so that the response speed of the device is improved. In the second P-type well, a gate is arranged between the N + bridge region and the second N + region to form an NMOS (the N + bridge region and the second N + region are respectively used as a source and a drain), and the voltage of the gate forms an electron channel on the surface between the N + bridge region and the second N + region, so that the conduction speed of the second NPN bipolar transistor QN2 can be improved.

Description

Power device electrostatic discharge protection circuit

Technical Field

The utility model relates to a power device field, concretely relates to power device electrostatic discharge protection circuit.

Background

The electrostatic discharge protection circuit of the device is mainly divided into a semiconductor built-in circuit and an external circuit connected with the device through a pin, and the purpose of the protection circuit is to protect the device from being damaged by static electricity or performance attenuation caused by the static electricity. When the semiconductor device circuit contacts human body and mechanical equipment, the upper mega charge energy can be input into the device from the pins of the device to cause damage. Similarly, the static charge existing in the device can be output to the external circuit through the pin, and further damage other semiconductor devices of the external circuit, so that an electrostatic discharge protection circuit is constructed between most of the semiconductor devices and the circuit to prevent the damage.

The conventional method for protecting the circuit by electrostatic discharge in the power device is, for example, a double-grounded N-type metal oxide semiconductor device adopted by a thyristor SCR, the triggering time of the electrostatic discharge is very fast, and in order to adapt to the instantaneous discharge, the area of the grounded gate needs to be enlarged to increase the parasitic capacitance of the device to relieve the impact of the discharge current.

As shown in fig. 1, the conventional esd protection circuit is formed by combining an N-well 120 and a P-well 110 on a P-type substrate 101 of a silicon-based thyristor. In the N-well 120, an N + type 121 and a P + type 122 are metal contacts to form an anode electrode in the No. 1 region; in the P-well 110, N + type 111 and P + type 112 contact the metal to form a cathode in the 2 nd region. The N + 121/N well 120, P well 110, and N + 111 form an NPN diode Q2. P + type 122, N-type well 120, P-type well 110 form PNP type diode transistor Q1; the PNP type diode Q1, the NPN type diode Q2 and the PNP type diode Q1 are combined into a thyristor.

As shown in fig. 2, the mechanism of static electricity generation is as follows: when the thyristor 100 is boosted from the short circuit to the trigger point 12, static charge may accumulate at ground; when the voltage or current exceeds the trigger point 12, the operating point of the device will return from the trigger point 12 to the hold region point forward breaker 11 along the characteristic curve, and continue to operate in this region. When the operating voltage of the thyristor 100 reaches the holding point 11 along the curve, an electrostatic discharge path is formed; saturated static charge is dumped to the die pad IC pad, maintaining the die pad at the point 11 potential. Therefore, the electrostatic inrush current flows to the ground, which prevents the electrostatic inrush current from flowing into the thyristor 100, and the inrush current will rush back to the thyristor 100 when the electrostatic inrush current potential of the electrostatic protection circuit is lower than the holding point 11.

The thyristor 100 has good electrostatic protection performance, and when the power of a workpiece rises, a discharge circuit and a stable current parasitic capacitance built in the P-type substrate 101 can achieve a protection effect in a smaller area than those of a common GGNMOS design; the thyristor is more suitable for being applied to high-frequency devices and reducing the requirement on parasitic capacitance. However, the trigger voltage point voltage of the thyristor 100 is 20V, and the holding point voltage is 1-2V, which may damage the MOSFET gate oxide layer or damage the internal channel.

SUMMERY OF THE UTILITY MODEL

Problem to prior art existence, the utility model aims to provide a power device electrostatic discharge protection circuit, its trigger voltage who has reduced the device prevents that high trigger voltage from causing destruction to the device is inside.

In order to achieve the above object, the utility model adopts the following technical scheme:

a power device electrostatic discharge protection circuit comprises an N-type deep well arranged on a semiconductor substrate, wherein the N-type deep well is provided with a first P-type well, an N-type well and a second P-type well, and the N-type well is arranged between the first P-type well and the second P-type well and is in contact with the first P-type well and the second P-type well;

a first N + region and a first P + region are arranged in the first P-type well; a second N + region and a second P + region are arranged in the second P-type well; a P + bridge area is arranged between the first P-type well and the N-type well; an N + bridge region is arranged at a junction region between the N-type well and the second P-type well; a third P + region is arranged in the N-type well;

the first N + region and the first P + region are connected with an anode end; the second N + region, the second P + region and the third P + region are connected with the cathode end; a grid electrode is arranged on the surface of the second P-type well between the N + bridge region and the second N + region;

the P + bridge region, the N-type well and the third P + region form a PNP diode QP 2; the first N + region, the first P-type well and the N-type well form an NPN diode transistor QN 1; the N + bridge region, the second P-type well and the second N + region form an NPN diode transistor QN 2.

The semiconductor substrate is a P-type substrate.

The P + bridge region is arranged on or outside a junction region of the first P-type well and the N-type well.

After the scheme is adopted, an N + bridge area is additionally arranged at the junction area of the N-type well and the second P-type well, a low trigger mechanism is induced by utilizing the breakdown characteristic in the second P-type well, and the electrostatic discharge protection circuit with high performance is provided by driving 1 PNP bipolar transistor and 2 NPN bipolar transistors, and has the characteristics of low trigger voltage, high current driving capability and the like. Meanwhile, a third P + region is arranged in the N-type well, so that the response speed of the device is improved.

Drawings

FIG. 1 is a schematic diagram of a conventional ESD protection circuit applied to a silicon-based thyristor;

fig. 2 is a voltage/current characteristic diagram of the thyristor of fig. 1;

fig. 3 is a schematic structural diagram of an esd protection circuit according to the present invention;

FIG. 4 is a graph comparing the voltage/current characteristics of the ESD protection circuit of the present invention with those of the prior art;

fig. 5 is a comparison diagram of the esd protection circuit of the present invention and the high temperature test of the prior art.

Detailed Description

The utility model discloses a power device electrostatic discharge protection circuit 200, which is characterized in that an N-type deep well 202 is constructed on a semiconductor substrate; a first P-well 210, an N-well 220, and a second P-well 230 are sequentially formed in the N-well 202.

The first N + region 211 and the first P + region 212 are disposed in the first P-well 210, the N + bridge region 231 is disposed between the junction of the N-well 220 and the second P-well 230, and the P + bridge region 221 is disposed between the first P-well 210 and the N + bridge region 231; the second N + region 233 and the second P + region 234 are disposed in the second P-well 230. The second N + region 233 and the N + bridge region 231 are combined into a complete N-type region in the second P-well 230. A third P + region 235 is formed in the N-well 220 between the P + bridge region 221 and the N + bridge region.

The first N + region 211 and the first P + region 212 are connected to an anode terminal; the second N + region 233, the second P + region 234, and the third P + region 235 are connected to the cathode terminal. The P + bridge region 221 can be disposed just above the junction between the N-well 220 and the first P-well 210, or outside the junction, or inside the first P-well 210, or inside the N-well 220 when outside the junction.

The P + bridge region 221, the N-well 220, and the third P + region 235 form a PNP diode QP 2. The first N + region 211, the first P-well 210, and the N-well 220 form an NPN diode transistor QN 1. The N + bridge region 231, the second P-well 230, and the second N + region 233 form an NPN diode transistor QN 2. Between the N + bridge region 231 and the second N + region 233, a gate is disposed on the surface of the second P-type well 230; the gate 232 and the N + bridge 231, the second N + region 233 are used as source (source) and drain (drain) to form an NMOS (N-type metal oxide semiconductor).

Fig. 3 shows an embodiment of the present invention, in which the semiconductor substrate is a p-type substrate 201.

An N-well 220 is formed in the N-well 202 adjacent to and in contact with the first P-well 210. The N-well 220 is the base region of the PNP bipolar transistor QP1, and by adjusting the recombination (recombination of the hole) of holes injected from the emitter through the length change of the N-well 220 at the PNP bipolar transistor QP1, the voltage Vh can be maintained by changing the current gain, and the trigger voltage value Vt can be lowered. That is, if the length of the N-well 220 is increased, the basic width of the PNP bipolar transistor QP1 is increased, and the rate of hole recombination in the base region is also increased.

A second P-well 230 formed in deep N-well 202 is in adjacent contact with N-well 220. In addition, the second P-type well 230 includes a second N + region 233 and a second P + region 234, and the second N + region 233 and the second P + region 234 are connected in parallel to form a single cathode.

An N + bridge 231 is disposed over the junction region of the N-well 220 and the second P-well 230. In the conventional SCR100, avalanche Breakdown (avalanche Breakdown) occurs due to the junction formed by the low doping concentration of the N-type well 120 and the P-type well 110, requiring a higher Breakdown voltage; however, in the esd protection circuit 200 of the present invention, the N-well 220 and the second P-well 230 have avalanche breakdown between the N + bridge 231 and the second P-well 230 through the N + bridge 231 with high doping concentration at the edge, so as to reduce the breakdown voltage and form a low trigger voltage Vt.

In addition, between the N + bridge region 231 and the second N + region 233, the gate 232 is disposed on the surface of the second P-well 230, forming the NMOS feature, wherein the second N + region 233 serves as the drain and the middle N + bridge region 231 serves as the source. When the power-on voltage of the N + bridge region 231 and the second N + region 233 reaches the trigger point trigger voltage Vt, a current-carrying channel is formed under the gate. Accordingly, the turn-on speed of the NPN bipolar transistor QN2 can be increased, and the channel width of the NMOS transistor can minimize the basic width of the NPN bipolar transistor QN 2.

P + bridge region 221 is between first P + region 212 and N + bridge region 231. The P + bridge region 221 may be disposed on the junction region of the first P-well 210 and the N-well 220, or may be disposed outside the junction region. Generally, when avalanche breakdown occurs, current generation is due to carrier movement occurring. At this time, carriers have a characteristic of moving to a high doping concentration, and the hole recombination rate increases in the N-type well 220, decreasing the amount of current, and thus reducing the electrostatic discharge current. Therefore, to suppress the increase of electrostatic discharge in the electrostatic discharge current, the P + bridge region 221 may be disposed between the first P + region 212 and the N + bridge region 231.

The embodiment of the utility model provides an operation condition who describes electrostatic discharge protection circuit 200 among the power device is as follows:

unlike a conventional SCR, the first N + region 211 connected to the first P-type well 210 is a forward bias voltage when an esd current flows into the anode. Therefore, a reverse bias is generated between the N + bridge 231 and the second P-well 230. The carriers in the junction area of the N + bridge area 231 and the second P-type well 230 generate a heating phenomenon due to collision, and the high-energy carriers can generate ionization collision with crystal lattices in the depletion area to form Electron-Hole pairs (Electron-Hole pairs, EHPs); electrons formed by the ionized collisions in the depletion region are transferred to the N-well 220 through the N + bridge 231 by the electric field, and holes are transferred into the N + bridge 231, thereby forming a reverse current from the N + bridge 231 to the second P-well 230. This is called Avalanche Breakdown Avalanche break.

The breakdown voltage is higher in the conventional SCR100 due to avalanche breakdown between the N-type well 120 and the p-type well 110 with low doping concentration. In the esd protection circuit 200 of the present invention, the N + bridge 231 is formed with a high doping concentration, so that avalanche breakdown occurs between the N + bridge 231 and the second P-type well 230, thereby reducing breakdown voltage, which can lower the trigger voltage Vt. The first P + region 212 emitter, the N-well 220 base, and the third P + region 235 collector when avalanche breakdown; the emitter-base junction of the PNP bipolar transistor QP2 is in a forward biased state. This design has a shorter path than the second P + region as collector, and can respond more quickly to the emitter of NPN transistor QN1, creating a forward bias.

When an ESD inrush current occurs at the anode, the PNP bipolar transistor QP2 is turned on, so that the NPN transistor QN1 is biased forward rapidly, and further avalanche breakdown occurs in the N + bridge region 231 of the collector region of the NPN transistor QN2 to generate a hole current, and the base of the second P-type well 230 and the emitter of the second N + region are biased forward. The channel of electrons under the gate 232 in the NMOS (231, 232, 233) accelerates the NPN

When the base first P-well 210 and the emitter N + bridge region 231 of the NPN bipolar transistor QN1 are turned on; the current flows to the second P-well 230, and the second parasitic resistance Rpw2 causes a voltage drop at the collector of the N + bridge 231 in the second P-well 230, turning on the second NPN bipolar transistor QN 2; QN2 has second P-well 230 as the base and second N + region 233 as the emitter.

Meanwhile, the current of the transistor QN1 and the transistor QN2, the voltage drop generated by the 3 rd generation resistor Rnw at the N-type well 220 and the resistor Rnw are connected at the base terminal of the PNP transistor QP2, and the voltage drop generated by the Rnw keeps the PNP transistor (QP2) at positive bias. The second parasitic resistor (Rpw2) is connected to the base of the transistor QN2, and the current is divided between the first parasitic resistor Rpw1 and the second parasitic resistor Rpw2, so that the transistor QN1 and the transistor QN2 are effectively maintained at positive bias. When the thyristor SCR is triggered, the PNP transistor QP2, the transistor QN1 and the transistor QN2 are biased positively, so that it is not necessary to provide a higher bias voltage to the PNP transistor QP 2; the anode voltage is inversely decreased to the minimum value, i.e., the holding voltage Vh. At this time, the SCR is maintained at the holding point Vh after triggering, which is a Latch-mode, and most of the ESD current flows to the cathode.

V of PNP transistor QP2 when avalanche breakdown occurs_CBIs positive bias, the PNP transistor QP2 is turned on. At this time, the current path of the collector region in the PNP transistor QP2 is very short, and can quickly respond to the emitter of the NPN transistor QN1 to establish a forward bias voltage and turn on the NPN transistor QN 1; in addition, avalanche breakdown creates hole current in the N + bridge region 231 of the collector region of NPN transistor QN2, with the base of second P-well 230 and the emitter of second N + region 233 being forward biased.

In addition, when electrostatic inrush current occurs at the anode, the current driving capability and the fast turn-on speed can be high by driving through one PNP transistor QP2 and two NPN transistors QN1, QN 2. Specifically, electrostatic inrush current occurs at the anode, the voltage of the first N + region 211 is forward biased, avalanche breakdown occurs at the N + bridge region 231 at the junction between the N-type well 220 and the P-type well 230 adjacent to the second region, and the doped ESD inrush current can be rapidly released.

Fig. 4 and 5 are a comparison graph of voltage/current characteristics and a comparison graph of high temperature test according to the embodiment of the present invention and the prior art, which are obtained by using the TCAD software of Synopsys, inc.

As shown in fig. 4, the trigger point of the conventional SCR100 is 18V, and the trigger point of the esd protection circuit 200 of the present invention is 8-10V lower than that of the SCR 100.

FIG. 5 shows the heat generation in the device chip in the HBM (human Body model) 8kv ESD test. The maximum temperature of the conventional SCR100 is 345K, while the maximum temperature of the ESD protection circuit 200 is 321K, 24K lower than the conventional SCR 100. The test result demonstrates the utility model discloses a lower interior temperature has, this proves the utility model discloses an electrostatic discharge protection circuit has fine protective properties.

To sum up, the utility model discloses a key is, the utility model discloses increased an N + bridge area 231 at N type well 220, second P type well 230, utilize the breakdown of N + bridge area 231 to specially reduce the trigger point of second P type well 230. In the second P-well 230, a gate 232 is disposed between the N + bridge region 231 and the second N + region 233 to form an NMOS (the N + bridge region and the second N + region are respectively used as a source and a drain), and the voltage of the gate 232 forms an electron channel on the surface between the N + bridge region 231 and the second N + region 232, which can improve the turn-on speed of the second NPN bipolar transistor QN 2. Meanwhile, the utility model adds a third P + region 235 in the N-type well (220); the third P + region 32 serves as the collector, the N-well 220 serves as the base, and the P + bridge region 221 serves as the emitter, forming a PNP transistor QP 2. Thus, by shortening the current path in the chip, a forward bias is established at the base of the NPN transistor QN1, so that the NPN transistor QN1 is turned on quickly and the ESD inrush current is discharged.

The utility model discloses a can release static (ESD) inrush current effectively through realizing the high-gain characteristic. The utility model discloses can be applied to semiconductor integrated circuit, in IO interface circuit and power device, the application is extensive. The utility model discloses at the built-in electrostatic discharge ESD protection circuit of power chip, have high stability and reliability, and can bring considerable cost benefit.

The above description is only an embodiment of the present invention, and is not intended to limit the technical scope of the present invention, so that any slight modifications, equivalent changes and modifications made by the technical spirit of the present invention to the above embodiments are all within the scope of the technical solution of the present invention.

Claims (3)

1. A kind of power device electrostatic discharge protective circuit, characterized by that: the N-type deep well is arranged on a semiconductor substrate and is provided with a first P-type well, an N-type well and a second P-type well, and the N-type well is arranged between the first P-type well and the second P-type well and is in contact with the first P-type well and the second P-type well;

a first N + region and a first P + region are arranged in the first P-type well; a second N + region and a second P + region are arranged in the second P-type well; a P + bridge area is arranged between the first P-type well and the N-type well; an N + bridge region is arranged at a junction region between the N-type well and the second P-type well; a third P + region is arranged in the N-type well;

the first N + region and the first P + region are connected with an anode end; the second N + region, the second P + region and the third P + region are connected with the cathode end; a grid electrode is arranged on the surface of the second P-type well between the N + bridge region and the second N + region;

the P + bridge region, the N-type well and the third P + region form a PNP diode QP 2; the first N + region, the first P-type well and the N-type well form an NPN diode transistor QN 1; the N + bridge region, the second P-type well and the second N + region form an NPN diode transistor QN 2.

2. The power device electrostatic discharge protection circuit of claim 1, wherein: the semiconductor substrate is a P-type substrate.

3. The power device electrostatic discharge protection circuit according to claim 1 or 2, wherein: the P + bridge region is arranged on or outside a junction region of the first P-type well and the N-type well.

Images