KR20200066853A - Electrostatic Discharge Protection Device having Dual Emitter Structure - Google Patents

Abstract

Disclosed is an electrostatic discharge protection device with a dual emitter structure which can be applied with high voltage by improving high holding voltage and endurance characteristics. The present invention may further form a P well in a conventional lateral insulated gate bipolar transistor structure and form a P+ region and an N+ region on the P well to form a double structure connected to a cathode. Therefore, since a current discharge path by an internal parasitic bipolar transistor is added, it is possible to implement a structure of discharging the current in parallel with the conventional parasitic bipolar transistor, thereby improving the endurance characteristics. In addition, since the current gain beta of the parasitic PNP bipolar transistor can be reduced by an additionally inserted N+ floating region to increase the current flowing in the base, provided is an effect that the holding voltage is increased.

Description

Electrostatic discharge protection device having dual emitter structure

The present invention relates to an electrostatic discharge protection device, and more particularly, to an electrostatic discharge protection device having a dual emitter structure capable of high voltage application by increasing a holding voltage and improving the endurance characteristics.

The electrostatic discharge protection device is a device that protects a semiconductor circuit when an unintended high voltage, such as static electricity, is applied among the semiconductor devices. The electrostatic discharge protection element is connected to an input terminal of a semiconductor circuit that performs a specific function, and maintains an off state when a normal level voltage or signal is applied. In addition, when a surge voltage is applied, the electrostatic discharge protection element is turned on to discharge current according to the applied voltage to ground or the like. This operation protects the internal IC from voltages beyond the normal operating range.

The voltage level at which the electrostatic discharge protection element is turned on to start operation is referred to as a trigger point. Also, a region that maintains a constant voltage state in a turned-on state is referred to as a holding region. Therefore, when a high level voltage is applied to the semiconductor device due to static electricity, the electrostatic discharge protection device operates in the holding region, and a large current flows to the ground through the electrostatic discharge protection device. Therefore, the internal circuit of the chip in which the semiconductor circuit is implemented is protected from static electricity or the like.

1 is a cross-sectional view of an SCR according to the prior art.

Referring to FIG. 1, the SCR 100 according to the related art includes a semiconductor substrate 110, an N well 120 and a P well 130. The N-well doped with an N-type includes a first P+ region 121 and a first N+ region 122, and the first P+ region 121 and the first N+ region 122 are anodes. It is connected with. P-type doped P-well 130 includes a second P+ region 131 and a second N+ region 132, and the second P+ region 131 and the second N+ region 132 are cathodes. It is connected with. N-well 120 and P-well 130 are in contact with each other, and a trigger operation is performed by avalanche breakdown at the junction. That is, the ESD current coming through the anode 140 is discharged. The SCR 100 is composed of a PNPN thyristor, and the thyristor includes a first P+ region 121, an N well 120, a P well 130, and a second N+ region 132. As the voltage increases by the ESD current flowing into the anode, the emitter-base junction of the parasitic PNP bipolar transistor constituting the thyristor becomes a forward bias, and the parasitic PNP bipolar The transistor is turned on. The current flowing through the parasitic PNP bipolar transistor flows to the P well 130, and the parasitic NPN bipolar transistor is turned on by this current. The current of the parasitic NPN bipolar transistor flowing from the N well 120 to the cathode 150 catches the forward bias of the parasitic PNP bipolar transistor, and eventually the SCR 100 is triggered by two parasitic bipolar transistors that are turned on. )do. Through this, it is no longer necessary to bias the parasitic PNP bipolar transistor, and the anode voltage is reduced to a minimum value. Afterwards, the SCR 100 effectively performs ESD feedback through the anode by operating a positive feedback operation. It becomes possible to discharge. However, the SCR 100 is not suitable as a device for high voltage and does not minimize the effect of a load on the normal operation of the internal circuit due to a low holding voltage, and overshooting or noise of the voltage. There is a disadvantage in that unintended operation due to influences the operation of the internal circuit.

2 is a cross-sectional view showing an electrostatic discharge protection device using a conventional horizontal insulated gate bipolar transistor (LIGBT).

Referring to FIG. 2, unlike the electrostatic discharge protection device 100 of FIG. 1, it is intended to apply high voltage and is intended for electrostatic discharge rather than general switching, so that the gate and the emitter except the collector are connected to ground (Gate -grounded LIGBT). The operation method is as follows. When the internal circuit is in the normal operating state, the P-well 240 and the deep N-well 220 do not operate by reverse bias. Therefore, the ESD protection circuit in the normal operation state of the internal circuit does not affect the operation. However, when ESD surge is applied, avalanche breakdown occurs in the reverse bias state of the P well 240 and the deep N well 220, and current is formed from the collector to the emitter. When the formed current induces a potential rise of the P well 240 and crosses the potential barrier between the P well 240 and the N+ region 241 of the emitter, the P well 240 and the N+ region 241 are forward biased. The parasitic NPN bipolar transistor formed by the emitter's N+ region 241, P-well 240, and deep N-well 220 operates. Since the parasitic NPN bipolar transistor provides bias current of the parasitic PNP bipolar transistor formed by the collector P+ region 231, the deep N well 220, and the P well 240, the parasitic NPN bipolar transistor is positively feedbacked like the SCR 100 and ESD discharge. Form a path. However, similar to the SCR 100 of FIG. 1, since it has a low holding voltage, it can be used as an electrostatic discharge protection device that can be applied to a higher voltage than FIG.

3 is a cross-sectional view showing another embodiment of an electrostatic discharge protection device based on a conventional lateral insulated gate bipolar transistor.

Referring to FIG. 3, FIG. 3 shows a structure in which the holding voltage of the electrostatic discharge protection device based on the horizontal insulated gate bipolar transistor of FIG. 2 mentioned above is improved. Referring to FIG. 3, the configuration is almost the same as in FIG. 2, and the difference lies in the N+ region 332 additionally inserted inside the N well region 330. At this time, the doping concentration of the added N+ region 332 is doped with an N-type concentration higher than that of the P-well region. The electrostatic discharge protection device having the structure of FIG. 3 has the same operation principle as in FIG. 2 and has an effect of increasing the base concentration of the parasitic PNP bipolar transistor due to the additionally inserted N+ region 332. The current gain decreases due to the increase of the base concentration, and the holding voltage, which is the minimum voltage at which the parasitic bipolar transistor operates due to the increase of the base current, has a higher value than the horizontal insulated gate bipolar transistor of FIG. 2. Therefore, FIG. 3 is a form of an electrostatic discharge protection element that can be applied to a high voltage circuit by effectively preventing the latch-up occurring in FIG. However, due to the insertion of the additional N+ region 332, the length is increased compared to the structure of FIG. 2, so that the on resistance may be reduced for some electric fields, and the endurance characteristics must be improved for high voltage resistance for high voltage applications. There is this.

Korean Patent Publication 10-2006-0067100

The present invention is to solve the above-described problems of the prior art. That is, to provide an electrostatic discharge protection device having a dual emitter structure capable of performing stable operation even at high voltages based on a horizontal insulated gate bipolar transistor.

The present invention for solving the above problems is a semiconductor substrate, a deep N well formed on the semiconductor substrate, an N well formed on the deep N well, a first formed on the deep N well, and formed close to the N well It includes a P well, a second P well formed close to the first P well, and a gate formed to contact the first P well and the second P well.

A first P+ region formed on the N well, a first N+ region formed on the N well, a second P+ region formed on the first P well, a second N+ region formed on the first P well, and the first A third N+ region formed on the 2 P wells and a third P+ region formed on the second P wells may be further included.

The first P+ region may be connected to the anode terminal, and the second P+ region, the second N+ region, the gate, the third N+ region, and the third P+ region may be connected to the cathode terminal.

An NMOS transistor having source and drain as the gate, the second N+ region, and the third N+ region may be formed, respectively.

A first PNP bipolar transistor formed by the first P+ region, the N well and the second P+ region, a second PNP bipolar transistor formed by the first P+ region, the N well, and the third P+ region, the N The well may include a first NPN bipolar transistor formed by the first P well and the second N+ region, and a second NPN bipolar transistor formed by the N well, the second P well, and the third N+ region. .

The first PNP bipolar transistor and the second PNP bipolar transistor may be connected in parallel.

When ESD surge flows into the anode terminal, avalanche breakdown may occur at the junction of the deep N-well and the first P-well.

The first N+ region may be formed by floating with the outside.

The first P well, the second P+ region, and the second N+ region may be formed symmetrically with respect to the gate and the second P well, the third N+ region, and the third P+ region.

According to the present invention, a P-well may be additionally formed in a conventional lateral insulated gate bipolar transistor structure, and a P+ region and an N+ region may be formed on the P-well to form a double structure connected to the cathode. Therefore, since the current discharge path by the internal parasitic bipolar transistor is added, it is possible to take a structure of discharging the current in parallel with the conventional parasitic bipolar transistor, thereby improving the endurance characteristics.

In addition, since the current gain beta of the parasitic PNP bipolar transistor can be reduced by an additionally inserted N+ floating region to increase the current flowing in the base, the holding voltage is increased.

Therefore, it is possible to effectively protect the semiconductor device against ESD surge generated in a high voltage environment due to improved withstand characteristics and increased holding voltage, and ensure stable operation.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view of an SCR according to the prior art.
2 is a cross-sectional view showing a conventional horizontal-type insulated gate bipolar transistor-based electrostatic discharge protection device.
3 is a cross-sectional view showing another embodiment of a conventional horizontal-type insulated gate bipolar transistor-based electrostatic discharge protection device.
4 is a cross-sectional view showing an electrostatic discharge protection device according to a preferred embodiment of the present invention.
5 is a circuit diagram showing an electrostatic discharge protection device according to a preferred embodiment of the present invention.

The present invention can be applied to a variety of transformations and may have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all conversions, equivalents, and substitutes included in the spirit and scope of the present invention. In the description of the present invention, if it is determined that a detailed description of known technologies related to the present invention may obscure the subject matter of the present invention, the detailed description will be omitted.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings, and in describing with reference to the accompanying drawings, identical or corresponding components are assigned the same reference numbers, and redundant description thereof will be omitted. Shall be

4 is a cross-sectional view showing an electrostatic discharge protection device according to a preferred embodiment of the present invention.

5 is a circuit diagram showing an electrostatic discharge protection device according to a preferred embodiment of the present invention.

4 and 5, the electrostatic discharge protection device 400 according to the present invention includes a semiconductor substrate 410, the semiconductor substrate 410 may be a P-type semiconductor substrate.

In addition, a deep N-well 420 may be formed on the semiconductor substrate 410.

An N-well 430, a first P-well 440, and a second P-well 450 may be included on the deep N-well 420.

The N well 430 may be formed on the deep N well 420, and the first P+ region 431 and the first N+ region 432 may be formed on the N well 430. Here, the first P+ region 431 may be connected to an anode terminal functioning as a collector terminal.

In addition, the first N+ region 432 is formed on the N well 430, and may be formed to float outside the first P+ region 431 at a predetermined distance.

The first P-well 440 is formed on the deep N-well 420, and may be formed at a predetermined distance from the N-well 430. That is, an insulating layer is formed between the N well 430 and the first P well 440. The insulating layer may be a structure embedded with an insulating material according to a shallow device separation process. At this time, the spaced distance buried as an insulating material between the N-well 430 and the first P-well 440 may vary according to design requirements.

A second P+ region 441 and a second N+ region 442 may be formed on the first P well 440, and the second P+ region 441 and the second N+ region 442 function as an emitter terminal. Can be connected to the cathode (cathode) terminal.

The second P-well 450 is formed on the deep N-well 420, and may be formed at a predetermined distance from the first P-well 440. A third N+ region 451 and a third P+ region 452 may be formed on the second P well 450, and the second P+ region 441 and the second N+ region 442 may include a second P+ region ( 441) and the second N+ region 442 may be connected to the cathode terminal.

Here, when the voltage below the trigger voltage is applied to the anode terminal, the first P well 440 and the second P well 450 block the flow of current. In addition, when the voltage between the anode terminal and the cathode terminal is greater than or equal to the trigger voltage, a current path toward the cathode terminal is formed to flow the current to the cathode terminal.

In addition, when the ESD surge is introduced into the anode terminal because the first P well 440 and the second P well 450 are formed close to each other, the deep N well 420 and the first P well 440 Avalanche breakdown may occur at the junction or at the deep N well 420 and the second P well 450 junction, respectively. In more detail, avalanche breakdown may occur in the corner portion of the first P-well 440, which is relatively close to the anode terminal.

A gate 460 may be formed on the first P well 440 and the second P well 450 to contact the first P well 440 and the second P well 450. Here, the gate 460 has an NMOS transistor (NM) structure in which the second N+ region 442 and the third N+ region 451 are source and drain, respectively. In addition, the gate 460 may be connected to the cathode terminal together with the second P+ region 441, the second N+ region 442, the third N+ region 451, and the third P+ region 452.

That is, the first P-well 440, the second P+ region 441, and the second N+ region 442 of the electrostatic discharge protection device 400 according to the present invention are centered around the gate 460 ( 450), the third N+ region 451 and the third P+ region 452 are formed to be symmetric to each other and connected to both the cathode terminal, which is an emitter terminal, to take a dual emitter structure.

The first PNP bipolar transistor Qp1 may be formed by the first P+ region 431, the N well 430, and the second P+ region 441, and the first P+ region 431 and the N well ( 430) and a third P+ region 452, a second PNP bipolar transistor Qp2 may be formed. Here, the first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2 may be formed in a parallel structure.

In addition, the first NPN bipolar transistor Qn1 may be formed by the N well 430, the first P well 440, and the second N+ region 442, and the N well 430, the second P well ( 450) and the third N+ region 451 to form the second NPN bipolar transistor Qn2.

That is, the electrostatic discharge protection device 400 according to the present invention may form two PNP bipolar transistors Qp1 and Qp2 and two NPN bipolar transistors Qn1 and Qn2.

As described above, the electrostatic discharge protection device 400 of the present invention includes the third N+ region 451 and the third in the first P well 440 structure in which the second P+ region 441 and the second N+ region 442 are formed. The second P well 450 in which the P+ region 452 is formed is further formed at a predetermined distance apart, and the second P+ region 441, the second N+ region 442, the third N+ region 451, and the third P+ are formed. By connecting the region 452 to the cathode terminal, which is the emitter terminal, the P-well can have a structure in which the emitter terminal is double connected. That is, the second PNP bipolar transistor Qp2 is added by the second P well 450 in which the added third N+ region 451 and the third P+ region 452 are formed, thereby further forming a discharge path. The second formed PNP bipolar transistor Qp2 and the first PNP bipolar transistor Qp1 have a parallel structure, so that the introduced ESD surge can be discharged in parallel. Since the electric currents are discharged in parallel by the parallel structured PNP bipolar transistors Qp1 and Qp2, the electrostatic discharge protection device 400 of the present invention can improve endurance characteristics.

In addition, the current gain beta of the first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2 may be reduced by the floating first N+ region 432 to increase the current flowing in the base. Therefore, since the holding voltage can be increased, the electrostatic discharge protection device 400 according to the present invention has an advantage applicable to high voltage.

The operation of the electrostatic discharge protection device according to the present invention will be described with reference to FIGS. 4 and 5 as follows.

The electrostatic discharge protection device 400 according to the present invention may be divided into two types, when a voltage lower than the trigger voltage is applied to the protection device and when a voltage higher than the trigger voltage is applied. For example, when an ESD current of less than the trigger voltage is introduced into the electrostatic discharge protection device 400, reverse bias is applied to the deep N well 420 and the first P well 440 or the second P well 450. The electrostatic discharge protection device 400 does not operate. However, when an ESD surge of a trigger voltage or higher is introduced into the electrostatic discharge protection device 400 through the anode, the deep N well 420 and the first P well 440 or the second P well 450 have avalanche. Avalanche Breakdown occurs. In more detail, avalanche breakdown may occur in the corner portion of the first P-well 440, which is relatively close to the anode terminal. That is, collision ionization of atoms by a carrier of high energy occurs at a junction interface between the deep N well 420 and the first P well 440 or the second P well 450, which is the deep N well 420 A depletion region having a relatively large width is formed between and the first P well 440 or the second P well 450.

As described above, when avalanche breakdown occurs, a number of electron-hole pairs may be generated. At this time, the former is directed to the anode terminal through the N-well 430, and the hole is directed to the cathode terminal through the first P-well 440. As electrons and holes flow to the N well 430, the first P well 440, and the second P well 450, the electrical potential of each well region is changed to induce forward bias for the generation of parasitic bipolars. The forward bias induced is:

When electrons generated by avalanche breakdown flow to the anode terminal, the electrical potential of the N-well 430 is changed to form a first PNP bipolar transistor (Qp1) and a PN junction comprising a first P+ region 431 and an N-well 430. The 2 PNP bipolar transistor Qp2 achieves forward bias. In addition, when holes generated by avalanche breakdown flow to the cathode terminal, the electrical potentials of the first P well 440 and the second P well 450 are changed to the second N+ region 442 and the first P well 440. The first NPN bipolar transistor Qn1 achieves forward bias with the NP junction, and the second NPN bipolar transistor Qn2 with the NP junction consisting of the third N+ region 451 and the second P-well 450 causes forward bias. To achieve.

The operation of the above-described bipolar transistors will be described in detail as follows.

When avalanche breakdown occurs in the deep N-well 420 and the first P-well 440, the first P+ region 431 is emittered and the N-well 430 is generated by the generated electron-hole pairs. The first PNP bipolar transistor Qp1 and the first P+ region 431 having the base as the base and the second P+ region 441 as the collector are emitters and the N well 430 as the base. 3 The second PNP bipolar transistor Qp2 with the P+ region 452 as a collector is turned on. Here, the first PNP bipolar transistor Qp1 takes a parallel structure by the second PNP bipolar transistor Qp2, which is additionally formed, so that the introduced ESD surge can be discharged in parallel. Since the currents are discharged in parallel by the two PNP bipolar transistors of the parallel structure, it is possible to improve the endurance characteristics.

In addition, the current gain beta of the first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2 is decreased by the first N+ region 432 inserted by floating to increase the current flowing in the base. As a result, the holding voltage increases as the base current increases. Therefore, the electrostatic discharge protection device 400 of the present invention can be applied to a high voltage due to the improvement of the withstand characteristics and the increased holding voltage.

Subsequently, when the first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2 are turned on, the current flowing through the first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2 is the first Pwell ( 440), and increase the potential of the first P-well 440.

The second N+ region 442 contacting the first P-well 440 and the second P-well 450 and the first P-well 440 having the increased potential, and the third N+ region contacting the second P-well 450 ( 451) when the potential difference between the threshold voltage is greater than or equal to the threshold voltage, the first NPN with the N well 430 as the collector, the first P well 440 as the base, and the second N+ region 442 as the emitter. The second NPN bipolar transistor Qn2 with the bipolar transistor Qn1 and the N well 430 as the collector and the second P well 450 as the base and the third N+ region 451 as the emitter is turned on.

The current flowing by the turn-on of the first NPN bipolar transistor Qn1 and the second NPN bipolar transistor Qn2 is the resistance of the resistor Rnw connected to the bases of the first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2. The first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2 are maintained by a voltage drop to maintain a forward bias.

In addition, the current flowing through the first PNP bipolar transistor Qp1 and the second PNP bipolar transistor Qp2 is the voltage of the resistor Rpw connected to the bases of the first NPN bipolar transistor Qn1 and the second NPN bipolar transistor Qn2. The drop helps the first NPN bipolar transistor (Qn1) and the second NPN bipolar transistor (Qn2) to maintain forward bias.

Therefore, the SCR is triggered by the turned-on two first PNP bipolar transistors Qp1 and the second PNP bipolar transistor Qp2, and the two first NPN bipolar transistors Qn1 and the second NPN bipolar transistor Qn2. Through this, it is no longer necessary to bias, and the anode voltage is reduced to a minimum value. This is called a holding voltage, and the operation of maintaining the holding voltage after the trigger operation of the SCR is in latch-mode. It says. As the SCR operates due to the latch operation, the ESD current flowing into the anode is discharged through the cathode terminal.

As described above, the electrostatic discharge protection device 400 having a dual emitter structure according to the present invention provides the second P well 450 to the first P well 440 in the conventional electrostatic discharge protection device 400 structure. It may be further formed to be close, and the third P+ region 452 and the third N+ region 451 may be formed on the second P well 450 to form a double structure connected to the cathode. Therefore, since the current discharge path by the second PNP bipolar transistor Qp2 is added, a structure for discharging current in parallel with the conventional first PNP bipolar transistor Qp1 can be improved, thereby improving the endurance characteristics.

In addition, since the current gain beta of the PNP bipolar transistor can be reduced by the first N+ region 432 formed by the floating and additionally inserted, the current flowing in the base can be raised, thereby increasing the holding voltage.

Therefore, it is possible to effectively protect the semiconductor device against ESD surge generated in a high voltage environment due to improved withstand characteristics and increased holding voltage, and ensure stable operation.

On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented as specific examples for ease of understanding, and are not intended to limit the scope of the present invention. It is apparent to those skilled in the art to which the present invention pertains that other modified examples based on the technical idea of the present invention can be implemented in addition to the embodiments disclosed herein.

410: semiconductor substrate 420: deep N-well
430: N-well 431: 1st P+ area
432: 1st N+ area 440: 1st P well
441: second P+ area 442: second N+ area
450: second P-well 451: third N+ region
452: third P+ area 460: gate
Resistance: Rpw, Rnw
Qp1: first PNP bipolar transistor
Qp2: second PNP bipolar transistor
Qn1: 1st NPN bipolar transistor
Qn2: 2nd NPN bipolar transistor

Claims (9)

Semiconductor substrates;
A deep N well formed on the semiconductor substrate;
An N well formed on the deep N well;
A first P well formed on the deep N well and close to the N well;
A second P well formed on the deep N well and proximate to the first P well; And
An electrostatic discharge protection device having a dual emitter structure including a gate formed to contact the first P well and the second P well. According to claim 1,
A first P+ region formed on the N well;
A first N+ region formed on the N well;
A second P+ region formed on the first P well;
A second N+ region formed on the first P well;
A third N+ region formed on the second P well; And
An electrostatic discharge protection device having a dual emitter structure further comprising a third P+ region formed on the second P well. According to claim 2,
The first P+ region is connected to the anode terminal,
The second P+ region, the second N+ region, the gate, the third N+ region, and the third P+ region are connected to a cathode terminal, and the electrostatic discharge protection device having a dual emitter structure. According to claim 2,
An electrostatic discharge protection device having a dual emitter structure in which NMOS transistors having source and drain as the gate and the second N+ region and the third N+ region, respectively, are formed. According to claim 2,
A first PNP bipolar transistor formed by the first P+ region, the N well and the second P+ region;
A second PNP bipolar transistor formed by the first P+ region, the N well and the third P+ region;
A first NPN bipolar transistor formed by the N well, the first P well, and the second N+ region; And
An electrostatic discharge protection device having a dual emitter structure including a second NPN bipolar transistor formed by the N well, the second P well, and the third N+ region. The method of claim 5,
The first PNP bipolar transistor and the second PNP bipolar transistor are electrostatic discharge protection devices having a dual emitter structure connected in parallel. According to claim 3,
When the ESD surge is introduced into the anode terminal, an electrostatic discharge protection device having a dual emitter structure in which avalanche breakdown occurs at the junction of the deep N well and the first P well. According to claim 2,
The first N+ region is an electrostatic discharge protection device having a dual emitter structure formed by floating with the outside. According to claim 2,
The first P well, the second P+ region, and the second N+ region are formed to be symmetric with each other with respect to the gate and the second P well, the third N+ region, and the third P+ region. Electrostatic discharge protection device with emitter structure.

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