KR102262041B1 - Electrostatic Discharge Protection Device - Google Patents

Abstract

Disclosed is a bidirectional electrostatic discharge protection element having a high holding current and a high holding voltage and having latch-up immunity. In this case, a P+ region and a gate are added in the conventional LTDDSCR structure and the added P+ region is formed to be electrically connected to the gate. Therefore, after a bipolar transistor is turned on, a voltage is applied to the gate through the P+ region before the holding voltage is formed, so that a resistance on a surface of an N well is reduced, thereby lowering a current gain of the bipolar transistor to achieve a high holding voltage and a high holding current. In addition, by forming a plurality of P+ crossing regions and N+ crossing regions to cross to be connected to terminals, an emitter current of the bipolar transistor is reduced, thereby increasing the holding voltage by the lowered current gain.

Description

Electrostatic Discharge Protection Device

The present invention relates to an electrostatic discharge protection device, and more particularly, to a bidirectional electrostatic discharge protection device having a high holding current and a high holding voltage and having latch-up immunity.

An electrostatic discharge protection device is a device that protects a semiconductor circuit when an unintentional high voltage such as static electricity is applied among semiconductor devices. The electrostatic discharge protection device is connected to an input terminal of a semiconductor circuit that performs a specific function, and maintains an off state when a voltage or signal of a normal level is applied. In addition, when a surge voltage is applied, the electrostatic discharge protection device is turned on to discharge a current according to the applied voltage to a ground or the like. Through this operation, it functions to protect the internal IC from voltage exceeding the normal operating range.

A voltage level at which the electrostatic discharge protection device is turned on and starts an operation is referred to as a trigger point. Also, a region in which a kind of constant voltage state is maintained in a turned-on state is referred to as a holding region. Accordingly, when a high level voltage is applied to the semiconductor device due to static electricity or the like, the electrostatic discharge protection device operates in the holding region, and a large current flows to the ground through the electrostatic discharge protection device. Accordingly, the internal circuit of the chip in which the semiconductor circuit is implemented is protected from an impact caused by static electricity or the like.

1 is a cross-sectional view showing a conventional LVTSCR.

Referring to FIG. 1 , in the conventional LVTSCR 100 , an N well 110 and a P well 120 are formed on a substrate 101 . A first N + region 111 and a first P + region 112 are formed on the N well 110 to function as an anode terminal, and a second N + region 121 and a second P + region are formed on the P well 120 . A region 122 is formed to function as a cathode terminal. In addition, the N well 110 and the P well 120 form a PNP bipolar transistor Q1, and the first N + region 111, the P well 120, and the second N + region 121 are formed of an NPN bipolar transistor ( Q2) is formed. In addition, an LVTSCR with a lower trigger voltage is formed by adding an N+ bridge region 102 and a gate 123 between the N well 110 and the P well 120 .

The conventional LVTSCR 100 performs a trigger operation by a breakdown voltage at the junction of the N + bridge region 102 and the P well 120 . In addition, by using the GGNMOS structure to minimize the base width of the NPN bipolar transistor Q2 to the channel width of the NMOS transistor formed with the gate 123 , the N + bridge region 102 and the second N + region 121 , a low trigger voltage be able to have

However, the conventional LVTSCR 100 effectively discharges the ESD current in the forward direction, but discharges the current through the diode formed by the P well 120 and the N well 110 in the case of the ESD current in the reverse direction. This affects the normal operation of the internal circuit (Core circuit) due to the low turn-on voltage of the diode, and the current discharge ability is also not suitable.

2 is a cross-sectional view showing a conventional LTDDSCR.

Referring to FIG. 2 , in the conventional LTDDSCR 200 , a first P+ bridge region 202 is added between the first P well 220 and the N well 230 , and the N well 230 and the second P well are added. It has a structure in which the second P + bridge region 203 is added between 240 and has the same discharge capability even in the reverse ESD current. Therefore, the conventional LTDDSCR according to FIG. 2 can solve the reverse ESD current discharge problem, which is a disadvantage of the LVTSCR of FIG. 1, but has a problem in that the internal circuit is damaged by the latch-up according to the low holding voltage.

Korean Patent Publication 10-2017-0071676

The present invention is to solve the problems of the prior art described above. That is, to provide an electrostatic discharge protection device having a bidirectional characteristic while having a high holding current and a high holding voltage by adding a gate and a P+ region in the conventional LTDDSCR structure.

The present invention for solving the above problems provides a semiconductor substrate, a first deep N-well and a second deep N-well formed to be spaced apart from each other on the semiconductor substrate, a first P-well formed on the first deep N-well, and the first in contact with the P-well, in contact with the first deep N-well and the first N-well formed on the semiconductor substrate, and in contact with the first N-well, and in contact with the second P-well and the second P-well formed on the semiconductor substrate; On the second deep N-well, the second N-well formed on the semiconductor substrate, the third P-well formed on the second deep N-well, the first P-well, the second P-well, and the third P-well a first P+ region, a second P+ region, and a third P+ region respectively formed in and a plurality of second impurity crossing regions formed by intersecting impurities.

A first P+ bridge region formed in the junction region of the first N well and the second P well and a second P+ bridge region formed in the junction region of the second P well and the second N well may be further included.

a first gate formed on the first N well surface between the first impurity crossing region and the first P + bridge region and on the second N well surface between the second impurity crossing region and the second P + bridge region It may further include a second gate formed in the.

The second P+ region may be electrically connected to the first gate and the second gate.

The first impurity crossing region may include a first P+ crossing region formed on the first N well and a first N+ crossing region formed on the first N well.

A plurality of the first P+ crossing region and the first N+ crossing region may be formed to cross each other in a longitudinal direction of the first N well on a plan view.

The second impurity crossing region may include a second P+ crossing region formed on the second N well and a second N+ crossing region formed on the second N well.

A plurality of the second P+ crossing regions and the second N+ crossing regions may be formed to cross each other in a longitudinal direction of the second N well on a plan view.

The first P+ region and the first impurity crossing region may be connected to a first terminal, and the third P+ region and the second impurity crossing region may be connected to a second terminal.

a first PNP bipolar transistor formed by the first P+ region, the first N-well and the third P-well, the first P+ bridge region, a second formed by the first N-well and the first impurity crossing region a PNP bipolar transistor, a third PNP bipolar transistor formed by the third P+ region, the second N-well and the first P-well, the second P+ bridge region, the second N-well and the second impurity crossing region and a fourth PNP bipolar transistor formed by an NPN bipolar transistor formed by the first N-well, the second P-well, and the second N-well.

When the first PNP bipolar transistor, the NPN bipolar transistor, and the fourth PNP bipolar transistor are turned on, a voltage may be applied to the second gate through the second P+ region.

When the third PNP bipolar transistor, the NPN bipolar transistor, and the fourth PNP bipolar transistor are turned on, a voltage may be applied to the first gate through the second P+ region.

The first P+ region, the first impurity crossing region, the first P+ bridge region, and the first gate may include the third P+ region, the second impurity crossing region, and the second with the second P+ region as a center. The P+ bridge region and the second gate may be formed to be symmetrical with each other.

According to the present invention, a P+ region and a gate are added in the conventional LTDDSCR structure, and the added P+ region is formed to be electrically connected to the gate. Therefore, after the bipolar transistor is turned on, a voltage is applied to the gate through the P+ region before the holding voltage is formed, so that the resistance on the surface of the N well is reduced, thereby lowering the current gain of the bipolar transistor to achieve a high holding voltage and high holding voltage. can have current.

In addition, by forming a plurality of P+ crossing regions and N+ crossing regions to cross and connect to the terminals, the emitter current of the bipolar transistor is reduced and the holding voltage can be increased due to the lowered current gain.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view showing a conventional LVTSCR.
2 is a cross-sectional view showing a conventional LTDDSCR.
3 is a plan view illustrating an electrostatic discharge protection device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view taken along line II′ of FIG. 3 .
FIG. 5 is a circuit diagram of the electrostatic discharge protection device shown in FIG. 3 .
6 is a graph for comparing the voltage-current characteristics of the electrostatic discharge protection device according to the present invention and the conventional LTDDSCR.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention. In describing the present invention, if it is determined that a detailed description of a related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. do it with

3 is a plan view illustrating an electrostatic discharge protection device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view taken along line II′ of FIG. 3 .

FIG. 5 is a circuit diagram of the electrostatic discharge protection device shown in FIG. 3 .

3 to 5 , the electrostatic discharge protection device 300 according to the present invention includes a semiconductor substrate 301 , and the semiconductor substrate 301 may be a P-type semiconductor substrate 301 .

A first deep N-well 310 and a second deep N-well 320 may be formed on the semiconductor substrate 301 . Here, the first deep N-well 310 and the second deep N-well 320 may be spaced apart from each other and formed on the semiconductor substrate 301 .

In addition, on the semiconductor substrate 301 , the first deep N-well 310 and the second deep N-well 320 , a first P-well 330 , a first N-well 340 , a second P-well 350 , A second N well 360 and a third P well 370 may be formed.

In more detail, the first P-well 330 is formed on the first deep N-well 310 , and the first N-well 340 is formed to be in contact with the first P-well 330 , and the first It may be formed on the deep N-well 310 and the semiconductor substrate 301 . The second P-well 350 is formed to be in contact with the first N-well 340 , and to be formed on the semiconductor substrate 301 positioned between the first deep N-well 310 and the second deep N-well 320 . can The second N-well 360 is formed to be in contact with the second P-well 350 , and may be formed on the semiconductor substrate 301 and the second deep N-well 320 , and the third P-well 370 is It is formed to be in contact with the second N-well 360 , and may be formed on the second deep N-well 320 .

A first P+ region 331 may be formed on the first P well 330 , and a first impurity crossing region 380 may be formed on the first N well 340 . The first P+ region 331 and the first impurity crossing region 380 may be electrically connected to the first terminal T1 . Here, as shown in FIG. 3 , the first impurity crossing region 380 is formed on the first N well 340 , and in a plan view, in the longitudinal direction of the first N well 340 , the first P+ crossing region ( 381) and the first N+ crossing regions 382 may be formed to cross each other and to be disposed in plurality. Accordingly, the plurality of first P+ crossing regions 381 and first N+ crossing regions 382 that are intersected may have a structure connected to the first terminal T1 together with the first P+ region 331 . This reduces the current gain by reducing the emitter current of the bipolar transistor by allowing the first terminal T1 to cross the first P+ crossing region 381 and the first N+ crossing region 382 in multiple numbers. This is to increase the holding voltage according to the decrease in gain.

In addition, a first P+ bridge region 302 may be formed on the junction region of the first N well 340 and the second P well 350 to be spaced apart from the first impurity crossing region 380 , and the first impurity crossing region 302 may be formed. A first gate 341 may be formed on the surface of the first N well 340 between the region 380 and the first P+ bridge region 302 . That is, as shown in FIG. 3 , on one side of the first gate 341 , the first P+ crossing region 381 and the first N+ crossing region 382 cross each other to form the first gate 341 . It may be formed to be in contact with a plurality of them in the longitudinal direction, and the first P + bridge region 302 may be formed to contact the other side.

By forming the first P+ bridge region 302 in the junction region of the first N-well 340 and the second P-well 350 , when an ESD current flows into the first terminal T1 , the first P+ bridge region 302 has a high doping concentration. The 1 P+ bridge region 302 may have a low trigger voltage characteristic based on a low level avalanche breakdown voltage. In addition, the STI is omitted between the first impurity crossing region 380 and the first P+ bridge region 302 , and a first gate 341 is formed instead of the STI to form a PMOS transistor under the first gate 341 . By forming a channel, a current can flow on the surface of the first N well 340 to enable fast turn-on of the bipolar transistor.

Here, in the electrostatic discharge protection device 300 according to the present invention, the NPN bipolar transistor Qn may be formed by the first N well 340 , the second P well 350 , and the second N well 360 . . In addition, the first PNP bipolar transistor Qp1 may be formed by the first P + region 331 , the first N well 340 and the third P well 370 , and the first P + bridge region 302 , A second PNP bipolar transistor Qp2 may be formed by the first N well 340 and the first impurity crossing region 380 .

A second P+ bridge region 303 may be formed on the junction region of the second P well 350 and the second N well 360 . By forming the second P+ bridge region 303 in the junction region of the second P-well 350 and the second N-well 360 , when an ESD current flows into the second terminal T2 in the opposite direction, the second P+ The bridge region 303 allows for a low trigger voltage based on a low level avalanche breakdown voltage.

A second impurity crossing region 390 may be formed on the second N well 360 to be spaced apart from the second P+ bridge region 303 . Here, as shown in FIG. 3 , the second impurity crossing region 390 is formed on the second N well 360 , and a second P+ crossing region 391 is formed in the longitudinal direction of the second N well 360 . and the second N+ crossing regions 392 may be formed to cross each other and to be disposed in plurality.

A second gate 361 may be formed on the surface of the second N well 360 between the second P+ bridge region 303 and the second impurity crossing region 390 . That is, based on the second gate 361 , the second P + bridge region 303 may be in contact with one side of the second gate 361 , and the second P + cross region 391 and the second N + cross region 392 are formed on the other side. A plurality of the second gates 361 may be formed to cross each other in the longitudinal direction.

STI is omitted between the second P+ bridge region 303 and the second impurity crossing region 390, and a second gate 361 is formed instead of the STI so that a channel is formed under the second gate 361 by forming a PMOS transistor. By forming it, a current can flow on the surface of the second N well 360 to enable fast turn-on of the bipolar transistor.

A third P+ region 371 may be formed on the third P well 370 , and the third P+ region 371 may be electrically connected to the second terminal T2 together with the second impurity crossing region 390 . have. That is, the plurality of second P+ crossing regions 391 and second N+ crossing regions 392 that are intersected may have a structure connected to the second terminal T2 together with the third P+ region 371 . This reduces the current gain by reducing the emitter current of the bipolar transistor by allowing the second terminal T2 to connect the second P+ crossing region 391 and the second N+ crossing region 392 by crossing a plurality of them. This is to increase the holding voltage according to the decrease in gain.

A second P+ region 351 is formed on the second P well 350 , and may be formed between the first P+ bridge region 302 and the second P+ bridge region 303 . Here, the second P+ region 351 may be electrically connected to the first gate 341 and the second gate 361 . That is, by forming the second P+ region 351 on the second P well 350 and electrically connecting to the first gate 341 and the second gate 361 , the first terminal T1 or the second When the ESD current flows into the second terminal T2, after the bipolar transistors are turned on, holes are moved to the first gate 341 and the second gate 361 through the second P+ 351 region to apply a voltage. The resistance on the surfaces of the first N-well 340 and the second N-well 360 may be reduced. Accordingly, the base resistance of the bipolar transistor is lowered and the current gain is lowered by causing the current to increase to have a high holding voltage and thus a high holding current.

Here, a third PNP bipolar transistor Qp3 may be formed by the third P + region 371 , the second N well 360 and the first P well 330 , and a second P + bridge region 303 , A fourth PNP bipolar transistor Qp4 may be formed by the second N well 360 and the second impurity crossing region 390 .

Therefore, in the electrostatic discharge protection device 300 according to the present invention, when the ESD current flows into the first terminal T1 in the forward direction, the first PNP bipolar transistor Qp1, the fourth PNP bipolar transistor Qp4 and the NPN bipolar transistor ( Qn) is turned on to operate in the latch-mode, and when an ESD current flows into the second terminal T2 in the reverse direction, the second PNP bipolar transistor Qp2, the third PNP bipolar transistor Qp3, and the NPN The current gain may be reduced by turning on the bipolar transistor Qn to operate in the latch mode.

As described above, in the electrostatic discharge protection device 300 according to the present invention, the first P + region 331 , the first impurity crossing region 380 , the first P + bridge region 302 , and the first gate 341 are The third P+ region 371 , the second impurity crossing region 390 , the second P+ bridge region 303 , and the second gate 361 may be formed to be symmetrical with each other based on the second P+ region 351 . have. Accordingly, when the ESD current flows into the first terminal T1 and the second terminal T2 , that is, the ESD discharge in the forward direction and the ESD discharge in the reverse direction are discharged so that they are symmetrical to each other.

An operation of the electrostatic discharge protection device according to the present invention will be described with reference to FIGS. 3 and 5 .

When an ESD current flows into the first terminal T1 in the forward direction, the potentials of the first P-well 330 and the first N-well 340 increase in response to the flowing ESD current. Accordingly, a reverse bias is applied between the first N well 340 and the first P+ bridge region 302 .

At the interface of the junction between the first N well 340 and the first P+ bridge region 302 , collision ionization of atoms by high-energy carriers occurs. That is, a depletion region having a relatively large width is formed between the first N well 340 and the first P + bridge region 302 .

High-energy carriers cause ionization collisions with the lattice in the depletion region, forming electron-hole pairs. Electrons formed through ionization collisions formed in the depletion region move to the first N-well 340 by the electric field, and holes move to the second P-well 350 through the first P+ bridge region 302 . Accordingly, an avalanche breakdown occurs in which a reverse current is formed from the first N well 340 to the second P well 350 through the first P + bridge region 302 . Here, by causing the avalanche breakdown to occur between the first P+ bridge region 302 having a high doping concentration and the first N well 340 , a low breakdown voltage is generated to lower the trigger voltage.

Subsequently, the potentials of the second P well 350 and the second P+ bridge region 303 increase due to the holes moved to the second P well 350 , and the P well first resistor Rpw1 increases the potential of the second P well. A forward bias can be formed in the NPN bipolar transistor Qn by operating with a resistance component of 350.

In addition, when the potential difference between the second P+ bridge region 303 and the second N well 360 having a higher potential is equal to or greater than the threshold voltage, the PN junction is forward biased, and the second P+ bridge region 303 and the second N well 360 are forward biased. The NPN bipolar transistor Qn formed of the first N well 340 , the second P well 350 , and the second N well 360 is turned on by the forward bias of the N well 360 . A current flowing by the turn-on of the NPN bipolar transistor Qn may be supplied as a base current of the first PNP bipolar transistor Qp1 and the fourth PNP bipolar transistor Qp4.

Accordingly, the first PNP bipolar transistor Qp1 formed of the first P+ region 331 , the first N well 340 and the third P well 370 , the second P+ bridge region 303 , and the second N well ( 360) and the fourth PNP bipolar transistor Qp4 formed with the second impurity crossing region 390 are turned on, respectively. That is, an additional current path may be formed by adding the fourth PNP bipolar transistor Qp4 to the conventional LTDDSCR 200 . Therefore, the current gain can be reduced compared to the conventional LTDDSCR 200 by the current distribution.

The current flowing by the turn-on of the first PNP bipolar transistor Qp1 and the fourth PNP bipolar transistor Qp4 is reduced by the voltage drop of the P-well first resistor Rpw1 connected to the base of the NPN bipolar transistor Qn. Let (Qn) maintain a forward bias.

In addition, the current flowing through the NPN bipolar transistor Qn is an N-well first resistor Rnw1 and an N-well second resistor Rnw2 connected to the bases of the first PNP bipolar transistor Qp1 and the fourth PNP bipolar transistor Qp4. The first PNP bipolar transistor Qp1 and the fourth PNP bipolar transistor Qp4 maintain a forward bias by the voltage drop of .

Accordingly, the SCR is triggered by the turned-on NPN bipolar transistor Qn, the first PNP bipolar transistor Qp1, and the fourth PNP bipolar transistor Qp4. Through this, it is no longer necessary to hold the bias, and the anode voltage is reduced to a minimum value. This is called a holding voltage, and the current at this time is called a holding current. In addition, the operation of maintaining the holding voltage after the trigger operation of the SCR is referred to as a latch-mode. As the SCR operates due to the latch operation, the ESD current flowing into the first terminal T1 is discharged through the second terminal T2.

Here, in the electrostatic discharge protection device 300 according to the present invention, since the second P+ region 351 and the first gate 341 and the second gate 361 are electrically connected, the bipolar transistor is turned on and held Before the voltage is formed, holes move through the second P+ region 351 and a voltage is applied to the second gate 361 . When a voltage is applied to the second gate 361 , the resistance on the surface of the second N well 360 is reduced. This may reduce the current gain by lowering the base resistance of the fourth PNP bipolar transistor Qp4 and increasing the current. Therefore, it can have a high holding voltage, and thus can have a high holding current. That is, the holding voltage and the holding current can be simultaneously improved.

In addition, since the second terminal T2 is connected to the second impurity crossing region 390 formed by crossing the second P+ crossing region 391 and the second N+ crossing region 392 in large numbers, the NPN bipolar transistor Qn The emitter current (current flowing through the second N-well 360 and the second N+crossing region 392 ) may decrease, thereby reducing a current gain, and thus increasing the holding voltage.

Subsequently, when an ESD current flows into the second terminal T2 in the reverse direction, the potentials of the third P well 370 and the second N well 360 rise in response to the flowing ESD current. Accordingly, a reverse bias is applied between the second N well 360 and the second P + bridge region 303 .

At the interface of the junction between the first N well 340 and the first P+ bridge region 302 , collision ionization of atoms by high-energy carriers occurs. That is, a depletion region having a relatively large width is formed between the second N well 360 and the second P+ bridge region 303 .

The high-energy carriers cause ionization collisions with the lattice in the depletion region, forming electron-hole pairs. Electrons formed through ionization collisions formed in the depletion region move to the second N-well 360 by the electric field, and holes move to the second P-well 350 through the second P+ bridge region 303 . Accordingly, an avalanche breakdown occurs in which a reverse current is formed from the second N well 360 through the second P + bridge region 303 to the second P well 350 . Here, by causing the avalanche breakdown to occur between the second P+ bridge region 303 having a high doping concentration and the second N well 360 , a low breakdown voltage is generated to lower the trigger voltage.

Subsequently, the potentials of the second P well 350 and the first P+ bridge region 302 increase due to the holes moved to the second P well 350 , and the P well second resistor Rpw2 increases the potential of the second P well. A forward bias can be formed in the NPN bipolar transistor Qn by operating with a resistance component of 350.

In addition, when the potential difference between the first P+ bridge region 302 and the first N well 340 having a higher potential is equal to or greater than a threshold voltage, the PN junction is forward biased, and the first P+ bridge region 302 and the first N well 340 are forward biased. The NPN bipolar transistor Qn formed of the first N well 340 , the second P well 350 , and the second N well 360 is turned on by the forward bias of the N well 340 . A current flowing by the turn-on of the NPN bipolar transistor Qn may be supplied as a base current of the second PNP bipolar transistor Qp2 and the third PNP bipolar transistor Qp3.

Accordingly, the second PNP bipolar transistor Qp2 formed with the first P+ bridge region 302 , the first N well 340 , and the first impurity crossing region 380 , the third P+ region 371 , and the second N well The third PNP bipolar transistor Qp3 formed of 360 and the first P well 330 is turned on, respectively. That is, an additional current path may be formed by adding the second PNP bipolar transistor Qp2 to the conventional LTDDSCR 200 . Therefore, the current gain can be reduced compared to the conventional LTDDSCR 200 by the current distribution.

The current flowing by the turn-on of the second PNP bipolar transistor Qp2 and the third PNP bipolar transistor Qp3 is reduced by the voltage drop of the P-well second resistor Rpw1 connected to the base of the NPN bipolar transistor Qn. Let (Qn) hold forward bias.

In addition, the current flowing through the NPN bipolar transistor Qn is an N-well first resistor Rnw1 and an N-well second resistor Rnw2 connected to the bases of the second PNP bipolar transistor Qp2 and the third PNP bipolar transistor Qp3. The second PNP bipolar transistor Qp2 and the third PNP bipolar transistor Qp3 maintain a forward bias by the voltage drop.

Accordingly, the SCR is triggered by the turned-on NPN bipolar transistor Qn, the second PNP bipolar transistor Qp2, and the third PNP bipolar transistor Qp3, and the SCR operates due to the latch operation to the second terminal ( The ESD current flowing into T2 is discharged through the first terminal T1.

Also, as in the forward direction, the bipolar transistor is turned on in the reverse direction, and holes move through the second P+ region 351 before the holding voltage is formed, so that a voltage is applied to the first gate 341 . When a voltage is applied to the first gate 341 , the resistance on the surface of the first N well 340 is reduced. This may reduce the current gain by lowering the base resistance of the second PNP bipolar transistor Qp2 and increasing the current. Therefore, it can have a high holding voltage, and thus can have a high holding current. That is, the holding voltage and the holding current can be simultaneously improved.

In addition, since the first terminal T1 is connected to the first impurity crossing region 380 formed by crossing a plurality of the first P+ crossing region 381 and the first N+ crossing region 382, the NPN bipolar transistor Qn The emitter current (current flowing through the first N-well 340 and the first N+ crossing region 382 ) may decrease, thereby reducing a current gain, and thus increasing the holding voltage.

6 is a graph for comparing the voltage-current characteristics of the electrostatic discharge protection device according to the present invention and the conventional LTDDSCR.

An experiment to confirm the characteristics of the electrostatic discharge protection device 300 according to the present invention and the conventional LTDDSCR 200 was conducted using a TCAD Simulator manufactured by Synopsys, and the experimental results are the same as the experimental results of FIG. 6 .

Referring to FIG. 6 , the holding voltage of the conventional LTDDSCR 200 was measured to be 3.5V, while the electrostatic discharge protection device 300 according to the present invention was measured to be 13.6V, which is the electrostatic discharge protection according to the present invention. It can be seen that the device 300 has an increased holding voltage of about 10.1V than that of the conventional LTDDSCR 200 .

As described above, the electrostatic discharge protection device 300 according to the present invention adds a second P + region 351, a first gate 341, and a second gate 361 in the conventional LTDDSCR 200 structure, The second P+ region 351 is formed to be electrically connected to the first gate 341 and the second gate 361 . Accordingly, after the bipolar transistor is turned on, a voltage is applied to the first gate 341 or the second gate 361 through the second P+ region 351 before the holding voltage is formed, thereby forming the first N well 340 . Alternatively, by reducing the resistance on the surface of the second N well 360 , the current gain of the bipolar transistor may be lowered to have a high holding voltage and a high holding current. In addition, a plurality of P+ crossing regions and N+ crossing regions are formed to cross each other so that they are connected to the first terminal T1 and the second terminal T2, thereby reducing the emitter current of the bipolar transistor and lowering the holding voltage by the current gain. can elevate

On the other hand, the embodiments of the present invention disclosed in the present specification and drawings are merely presented as specific examples to aid understanding, and are not intended to limit the scope of the present invention. It will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

301: semiconductor substrate 302: first P + bridge region
303: second P + bridge region 310: first deep N-well
320: second deep N well 330: first P well
331: first P+ region 340: first N well
341: first gate 350: second P well
351: second P+ region 360: second N well
361: second gate 370: third P well
371: third P+ region 380: first impurity crossing region
381: first P + crossing region 382: first N + crossing region
390: second impurity crossing region 391: second P+ crossing region
392: second N + cross region

Claims (13)

semiconductor substrate;
a first deep N-well and a second deep N-well formed on the semiconductor substrate to be spaced apart from each other;
a first P-well formed on the first deep N-well;
a first N-well in contact with the first P-well and formed on the first deep N-well and the semiconductor substrate;
a second P-well in contact with the first N-well and formed on the semiconductor substrate;
a second N well in contact with the second P well and formed on the second deep N well and the semiconductor substrate;
a third P well formed on the second deep N well;
a first P+ region, a second P+ region, and a third P+ region respectively formed on the first P well, the second P well, and the third P well;
a first impurity crossing region formed on the first N well and formed in a plurality of impurities crossing it; and
The electrostatic discharge protection device is formed on the second N well and includes a second impurity crossing region in which a plurality of impurities cross each other. According to claim 1,
a first P+ bridge region formed in a junction region of the first N well and the second P well; and
The electrostatic discharge protection device further comprising a second P+ bridge region formed in the junction region of the second P well and the second N well. 3. The method of claim 2,
a first gate formed on the first N well surface between the first impurity crossing region and the first P+ bridge region; and
and a second gate formed on a surface of the second N well between the second impurity crossing region and the second P+ bridge region. 4. The method of claim 3,
and the second P+ region is electrically connected to the first gate and the second gate. The method of claim 1, wherein the first impurity crossing region comprises:
a first P+ crossing region formed on the first N-well; and
and a first N+ cross region formed on the first N well. 6. The method of claim 5,
and a plurality of the first P+ crossing regions and the first N+ crossing regions are formed to cross each other in a longitudinal direction of the first N well on a plane. The method of claim 1, wherein the second impurity crossing region comprises:
a second P+ crossing region formed on the second N well; and
and a second N+ crossing region formed on the second N well. 8. The method of claim 7,
and a plurality of the second P+ crossing regions and the second N+ crossing regions are formed to cross each other in a longitudinal direction of the second N well on a plane. According to claim 1,
the first P+ region and the first impurity crossing region are connected to a first terminal;
and the third P+ region and the second impurity crossing region are connected to a second terminal. 4. The method of claim 3,
a first PNP bipolar transistor formed by the first P+ region, the first N-well, and the third P-well;
a second PNP bipolar transistor formed by the first P+ bridge region, the first N well, and the first impurity crossing region;
a third PNP bipolar transistor formed by the third P+ region, the second N well, and the first P well;
a fourth PNP bipolar transistor formed by the second P+ bridge region, the second N well, and the second impurity crossing region; and
and an NPN bipolar transistor formed by the first N well, the second P well, and the second N well. 11. The method of claim 10,
and a voltage is applied to the second gate through the second P+ region when the first PNP bipolar transistor, the NPN bipolar transistor, and the fourth PNP bipolar transistor are turned on. 11. The method of claim 10,
and a voltage is applied to the first gate through the second P+ region when the third PNP bipolar transistor, the NPN bipolar transistor, and the fourth PNP bipolar transistor are turned on. 4. The method of claim 3,
The first P+ region, the first impurity crossing region, the first P+ bridge region, and the first gate may include the third P+ region, the second impurity crossing region, and the second with the second P+ region as a center. The electrostatic discharge protection device is formed to be symmetrical to the P+ bridge region and the second gate.

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