KR102441903B1 - SCR-Based Dual-Directional ESD Protection Device with High Holding Voltage - Google Patents

Abstract

Disclosed is an silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection device with a high holding voltage and dual-directional characteristics. To a conventional LTDDSCR structure, an N+ region on an N-well region and a gate on a P-well region are added, and the added N+ region and gate are electrically connected, to have a parasitic PN diode driven by a voltage applied to the gate during ESD current discharge. As a result, a gain of a positive feedback loop of a PNP bipolar transistor and an NPN bipolar transistor is lowered and high holding voltage characteristics may be attained. In addition, by forming multiple P+ crossing regions and N+ crossing regions to cross each other and to be connected to terminals, an emitter current of the bipolar transistor is reduced, thus resulting in a lower current gain and an increased holding voltage.

Description

SCR-Based Dual-Directional ESD Protection Device with High Holding Voltage

The present invention relates to an ESD protection device, and more particularly, to an ESD protection device having a high holding voltage and bidirectional characteristics.

Electrostatic discharge (ESD) is a factor that greatly affects the quality and reliability of semiconductor products. It is inserted between the I/O or Power Clamp terminals connected to the internal IC to protect the internal IC. As the degree of integration is further improved with the development of the semiconductor process industry, a low-area, high-resistance ESD protection device is required to secure reliability from ESD phenomenon. A commonly known bidirectional ESD protection device, LTDDSCR (Low Triggering Dual-Directional Silicon Controlled Rectifier), has superior areal efficiency and high reliability compared to a unidirectional ESD protection device.

1 is a cross-sectional view showing a conventional LTDDSCR.

Referring to FIG. 1 , in the conventional LTDDSCR 100 , a deep N-well 110 is formed on a substrate 101 , and a first P-well 120 , a second P-well 140 and An N well 130 is formed. A first P+ region 121 and a first N+ region 122 are formed on the first P well 120 to function as a first terminal T1 , and a second P+ region 142 is formed on the second P well 140 . ) and the second N + region 141 are formed to function as the second terminal T2 . In addition, the first P+ bridge region 102 is formed to contact the first P-well 120 and the N-well 130 , and the second P+ bridge to contact the N-well 130 and the second P-well 140 . A region 103 is formed.

In this conventional LTDDSCR 100, when an ESD current flows into the first terminal T1 or the second terminal T2, the operation of two NPN bipolar transistors Q1 and Q2 and one PNP bipolar transistor Q3 is ESD current is discharged by However, in the conventional LTDDSCR 100, there is a problem in that the internal circuit is damaged by the latch-up according to the low holding voltage.

Korean Patent Publication 10-2017-0071676

The present invention is to solve the problems of the prior art described above. That is, to provide an ESD protection device having a high holding voltage and bidirectional characteristics by adding a gate, an N+ region, and an impurity crossing region in the conventional LTDDSCR structure.

The present invention for solving the above problems provides a semiconductor substrate, a deep N-well formed on the semiconductor substrate, a first P-well formed on the deep N-well and having a plurality of first impurity crossing regions formed by crossing impurities, the above An N well formed on the deep N well and in contact with the first P well and having an N+ region, formed on the deep N well and formed in contact with the N well, a plurality of impurities intersecting a second P well in which a second impurity crossing region is formed, a first P+ bridge region formed to contact the first P well and the N well, and a second P+ bridge region formed to contact the N well and the second P well; include

a first gate formed on the first P-well surface between the first impurity crossing region and the first P+ bridge region and on the second P+ well surface between the second impurity crossing region and the second P+ bridge region It may include a second gate formed in the.

The first gate, the N+ region, and the second gate may be electrically connected to each other.

The first impurity crossing region may be connected to a first terminal, and the second impurity crossing region may be connected to a second terminal.

The first impurity crossing region includes a first P+ crossing region formed on the first P well and a first N+ crossing region formed on the first P well, and the first P+ crossing region and the first N+ crossing region A plurality of regions may be formed to cross each other in the longitudinal direction of the first P well on a plane.

The second impurity crossing region may include a second P+ crossing region formed on the second P well; and a second N+ crossing region formed on the second P well, wherein a plurality of the second P+ crossing region and the second N+ crossing region intersect each other in a longitudinal direction of the second P well in a plan view. have.

a PNP bipolar transistor formed by the first P+ bridge region, the N well and the second P+ bridge region, a first NPN bipolar transistor formed by the first impurity crossing region, the first P well and the N well, and the and a second NPN bipolar transistor formed by the N well, the second P well, and the second impurity crossing region.

When the PNP bipolar transistor and the second NPN bipolar transistor are turned on, a voltage may be applied to the second gate through the N+ region.

When the PNP bipolar transistor and the first NPN bipolar transistor are turned on, a voltage may be applied to the first gate through the N+ region.

and a first PN diode formed by the second P+ bridge region and the second impurity crossing region, and a second PN diode formed by the first P+ bridge region and the first impurity crossing region.

The first impurity crossing region, the first P+ bridge region, and the first gate may be formed to be symmetrical to the second impurity crossing region, the second P+ bridge region, and the second gate with respect to the N+ region. can

According to the present invention, in the conventional LTDDSCR structure, by adding an N+ region and a gate on the P well on the N well, and electrically connecting the added N+ region and the gate to each other, by the voltage applied to the gate during ESD current discharge The parasitic PN diode operates to lower the gain of the positive feedback loop of the PNP bipolar transistor and the NPN bipolar transistor. Therefore, it can have a high holding voltage characteristic.

In addition, by forming a plurality of P+ crossing regions and N+ crossing regions to cross and connect to the terminals, the emitter current of the bipolar transistor is reduced and the holding voltage can be increased due to the lowered current gain.

Furthermore, since the ESD discharge in the forward direction and the ESD discharge in the reverse direction have a structure in which the discharge is symmetrical to each other, the effect on the high holding voltage formed by the forward direction can be applied equally in the reverse direction.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view showing a conventional LTDDSCR.
2 is a plan view illustrating an ESD protection device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along II′ of FIG. 3 .
4 is a graph for comparing the voltage-current characteristics of the ESD protection device according to the present invention and the conventional LTDDSCR.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the present invention, if it is determined that a detailed description of a related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. do it with

2 is a plan view illustrating an ESD protection device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along II′ of FIG. 3 .

2 and 3 , the ESD protection device 200 according to an embodiment of the present invention includes a semiconductor substrate 201 , and the semiconductor substrate 201 may be a P-type semiconductor substrate.

A deep N-well 210 may be formed on the semiconductor substrate 201 , and a first P-well 220 , an N-well 230 , and a second P-well 240 may be formed on the deep N-well 210 . have.

For example, the first P-well 220 is formed on the deep N-well 210 , and may be formed to be in contact with one side of the N-well 230 , and the second P-well 240 is the deep N-well 210 . ), and may be formed so as to be in contact with the other side of the N-well 230 .

A first impurity crossing region 250 may be formed on the first P well 220 . The first impurity crossing region 250 may be electrically connected to the first terminal T1 . Here, as shown in FIG. 2 , the first impurity crossing region 250 is formed on the first P well 220 , and in a plan view, in the longitudinal direction of the first P well 220 , the first P+ crossing region ( 251) and the first N+ crossing regions 252 may be formed to cross each other and to be disposed in plurality. Accordingly, a plurality of first P+ crossing regions 251 and first N+ crossing regions 252 that are intersected may have a structure in which they are connected to the first terminal T1 . This is because the first terminal T1 connects a plurality of the first P+ crossing region 251 and the first N+ crossing region 252 to cross each other, so that when the ESD current flows into the second terminal T2, the emitter of the bipolar transistor This is to decrease the current gain by reducing the current, and to increase the holding voltage according to the decrease in the current gain.

Also, a first P+ bridge region 202 may be formed on the junction region of the first P well 220 and the N well 230 to be spaced apart from the first impurity crossing region 250 . Also, a first gate 221 may be formed on the surface of the first P well 220 between the first impurity crossing region 250 and the first P + bridge region 202 . That is, as shown in FIG. 2 , the first P+ crossing region 251 and the first N+ crossing region 252 cross each other on one side of the first gate 221 with the first gate 221 as the center. A plurality of first gates 221 may be in contact in the longitudinal direction, and the first P+ bridge region 202 may be in contact with the other side thereof.

The first P+ bridge region 202 is formed in the junction region of the first P-well 220 and the N-well 230, so that when an ESD current flows into the second terminal T2 in the reverse direction, the second terminal having a high doping concentration is formed. The 1 P+ bridge region 202 may have a low trigger voltage characteristic based on a low level avalanche breakdown voltage. In addition, the STI is omitted between the first impurity crossing region 250 and the first P+ bridge region 202 , and the first gate 221 is formed instead of the STI, and the first gate 221 is formed under the first gate 221 by forming the PMOS transistor. By forming a channel, a current can flow on the surface of the first P-well 220 to enable fast turn-on of the bipolar transistor.

Here, in the ESD protection device 200 according to the present invention, the first NPN bipolar transistor Qn1 may be formed by the first impurity crossing region 250 , the first P well 220 , and the N well 230 . . In more detail, the first NPN bipolar transistor Qn1 is formed by the first N+ crossing region 252 , the first P well 220 , and the N well 230 of the first impurity crossing region 250 . can

A second P+ bridge region 203 may be formed on the junction region of the N well 230 and the second P well 240 . By forming the second P+ bridge region 203 on the junction region of the N-well 230 and the second P-well 240 , when an ESD current flows into the first terminal T1 in the forward direction, the second P+ bridge Region 203 allows for a low trigger voltage based on a low level avalanche breakdown voltage.

A second impurity crossing region 260 may be formed on the second P well 240 to be spaced apart from the second P+ bridge region 203 . The second impurity crossing region 260 may be electrically connected to the second terminal T2 . Here, as shown in FIG. 2 , the second impurity crossing region 260 is formed on the second P well 240 , and a second P+ crossing region 261 in the longitudinal direction of the second P well 240 . and the second N+ crossing regions 262 may be formed to intersect each other and to be disposed in plurality. Accordingly, a plurality of second P+ crossing regions 261 and second N+ crossing regions 262 that are intersected may have a structure in which they are connected to the second terminal T2 . This is because the second terminal T2 connects a plurality of the second P+ crossing region 261 and the second N+ crossing region 262 to cross each other, so that when an ESD current flows into the first terminal T1, the emitter of the bipolar transistor This is to decrease the current gain by reducing the current, and to increase the holding voltage according to the decrease in the current gain.

A second gate 241 may be formed on the surface of the second P well 240 between the second P+ bridge region 203 and the second impurity crossing region 260 . That is, with the second gate 241 as the center, the second P + bridge region 203 may be formed to contact one side of the second gate 241 , and the second P + cross region 261 and the second P + cross region 261 are formed on the other side of the second gate 241 . N+ crossing regions 262 may be formed to cross each other so as to be in contact with each other in the longitudinal direction of the second gate 241 .

STI is omitted between the second P+ bridge region 203 and the second impurity crossing region 260, and a second gate 241 is formed instead of the STI, so that a channel is formed under the second gate 241 by forming a PMOS transistor. By forming it, current can flow on the surface of the second P-well 240 to enable fast turn-on of the bipolar transistor.

Here, in the ESD protection device 200 according to the present invention, the second NPN bipolar transistor Qn2 may be formed by the second impurity crossing region 260 , the second P well 240 , and the N well 230 . . In more detail, the second NPN bipolar transistor Qn2 is formed by the second N+ crossing region 262 , the first P well 220 , and the N well 230 of the second impurity crossing region 260 . can In addition, a PNP bipolar transistor Qp may be formed by the first P+ bridge region 202 , the N well 230 , and the second P+ bridge region 203 .

An N + region 231 is formed on the N well 230 , and may be formed between the first P + bridge region 202 and the second P + bridge region 203 . Here, the N+ region 231 may be electrically connected to the first gate 221 and the second gate 241 . That is, the N+ region 231 is formed on the N well 230 and electrically connected to the first gate 221 and the second gate 241 , so that the first terminal T1 or the second terminal T2 is formed. ), as the potential of the N well 230 rises, a positive voltage is applied to the first gate 221 or the second gate 241 to form the PN diodes D1 and D2. . The positive feedback lube gains of the PNP bipolar transistors Qp and the NPN bipolar transistors Qn1 and Qn2 may be lowered by the current flow through the PN diodes D1 and D2 to have a high holding voltage.

For example, when the ESD current flows into the first terminal T1 in the forward direction, the first PN diode D1 may be formed by the second P+ bridge region 203 and the second impurity crossing region 260 . . In more detail, the first PN diode D1 may be formed by the second P+ bridge region 203 and the second N+ crossing region 262 of the second impurity crossing region 260 . Therefore, when the ESD current is discharged by the positive feedback action of the PNP bipolar transistor Qp and the second NPN bipolar transistor Qn2, the positive feedback loop gain is lowered due to the current flow through the first PN diode D1, resulting in a high It may have a holding voltage.

Also, when the ESD current flows into the second terminal T2 in the reverse direction, the second PN diode D2 may be formed by the first P+ bridge region 202 and the first impurity crossing region 250 . In more detail, the second PN diode D2 may be formed by the first P+ bridge region 202 and the first N+ crossing region 252 of the first impurity crossing region 250 . Accordingly, when the ESD current is discharged due to the positive feedback action of the PNP bipolar transistor Qp and the first NPN bipolar transistor Qn1, even in the reverse direction, the current flows through the second PN diode D2 and the ESD current is positively fed back. The loop gain may be lowered to have a high holding voltage.

That is, in the ESD protection device 200 according to the present invention, the first impurity crossing region 250 , the first P+ bridge region 202 , and the first gate 221 have the N+ region 231 as the center, and the second impurity The cross region 260 , the second P+ bridge region 203 , and the second gate 241 may be formed to be symmetrical to each other. Accordingly, the same high holding voltage may be obtained not only when discharging the ESD current flowing into the first terminal T1 in the forward direction, but also when discharging the ESD current flowing into the second terminal T2 in the reverse direction.

The operation of the ESD protection device according to the present invention will be described with reference to FIGS. 2 and 3 .

When an ESD current flows into the first terminal T1 in the forward direction, the potentials of the first P-well 220 and the N-well 230 increase in response to the flowing ESD current. Accordingly, a reverse bias is applied between the N well 230 and the second P+ bridge region 203 .

At the interface of the junction between the N well 230 and the second P + bridge region 203 , collision ionization of atoms by high-energy carriers occurs. That is, a depletion region having a relatively large width is formed between the N well 230 and the second P+ bridge region 203 .

High-energy carriers cause ionization collisions with the lattice in the depletion region, forming electron-hole pairs. Electrons formed through ionization collisions formed in the depletion region move to the N well 230 by the electric field, and holes move to the second P well 240 through the second P+ bridge region 203 . Accordingly, an avalanche breakdown occurs in which a reverse current is formed from the N well 230 to the second P well 240 through the second P + bridge region 203 . Here, by causing the avalanche breakdown to occur between the second P+ bridge region 203 having a high doping concentration and the N well 230 , a low breakdown voltage is generated to lower the trigger voltage.

Subsequently, the potential of the second P-well 240 is increased by the holes moved to the second P-well 240 , which causes the second P-well 240 and the second N+ cross region 262 to pass in a forward direction. causes turn-on. Accordingly, the PNP bipolar transistor Qp formed with the first P + bridge region 202 , the N well 230 and the second P + bridge region 203 is turned on, and the N well 230 and the second P well 240 are turned on. and the second NPN bipolar transistor Qn2 formed of the second N+ crossing region 262 is turned on.

At this time, a positive voltage is applied to the second gate 241 electrically connected to the N + region 231 by the N well 230 having an elevated potential, so that the second P + bridge region 203 and the second N + cross region ( 262), the first PN diode D1 is formed. Accordingly, the positive feedback loop gain of the PNP bipolar transistor Qp and the second NPN bipolar transistor Qn2 may be lowered using the formed first PN diode D1, thereby providing a high holding voltage.

Also, since the second terminal T2 is connected to the second impurity crossing region 260 formed by crossing a plurality of the second P+ crossing regions 261 and the second N+ crossing regions 262, the second NPN bipolar transistor Qn2 ) of the emitter current may decrease, reducing the current gain. That is, the emitter injection efficiency of the second NPN bipolar transistor Qn2 may be lowered, and thus a high holding voltage may be obtained.

Meanwhile, SCR is triggered by the turned-on PNP bipolar transistor Qp and the second NPN bipolar transistor Qn2. After the trigger operation of the SCR, it operates in a latch-mode in which the holding voltage is maintained. As the SCR operates due to the latch operation by the latch mode, the ESD current flowing into the first terminal T1 is transferred to the second terminal. It is discharged through (T2).

Subsequently, when the ESD current flows into the second terminal T2 in the reverse direction, the potentials of the second P well 240 and the N well 230 increase in response to the flowing ESD current. Accordingly, a reverse bias is applied between the N well 230 and the first P+ bridge region 202 .

At the interface of the junction between the N well 230 and the first P + bridge region 202 , collision ionization of atoms by high-energy carriers occurs. That is, a depletion region having a relatively large width is formed between the N well 230 and the first P+ bridge region 202 .

The high-energy carriers cause ionization collisions with the lattice in the depletion region, forming electron-hole pairs. Electrons formed through ionization collisions formed in the depletion region move to the N well 230 by the electric field, and holes move to the first P well 220 through the first P+ bridge region 202 . Accordingly, an avalanche breakdown occurs in which a reverse current is formed from the N-well 230 to the first P-well 220 through the first P+ bridge region 202 . Here, by allowing the avalanche breakdown to occur between the first P+ bridge region 202 having a high doping concentration and the N well 230 , a low breakdown voltage may be generated to lower the trigger voltage.

Subsequently, the potential of the first P-well 220 is increased due to the holes moved to the first P-well 220 , which causes the first P-well 220 and the first N+ cross region 252 junction in a forward direction. causes turn-on. Accordingly, the PNP bipolar transistor Qp formed with the first P + bridge region 202 , the N well 230 and the second P + bridge region 203 is turned on, and the N well 230 and the first P well 220 are turned on. and the first NPN bipolar transistor Qn1 formed of the first N+ cross region 252 is turned on.

At this time, a positive voltage is applied to the first gate 221 electrically connected to the N + region 231 by the N well 230 having an elevated potential, so that the first P + bridge region 202 and the first N + cross region 252 are applied. ) of the second PN diode D2 is formed. Therefore, as in the forward direction, by lowering the positive feedback loop gains of the PNP bipolar transistor Qp and the first NPN bipolar transistor Qn1 using the formed second PN diode D2, a high holding voltage can be obtained. have.

Also, since the first terminal T1 is connected to the first impurity crossing region 250 formed by crossing a plurality of the first P+ crossing region 251 and the first N+ crossing region 252, the first NPN bipolar transistor Qn1 ) may decrease the emitter current, reducing the current gain. That is, the emitter injection efficiency of the first NPN bipolar transistor Qn1 may be lowered to have a high holding voltage.

Meanwhile, SCR is triggered by the turned-on PNP bipolar transistor Qp and the first NPN bipolar transistor Qn1. After the trigger operation of the SCR, it operates in a latch mode that maintains the holding voltage. As the SCR operates due to the latch operation by the latch mode, the ESD current flowing into the second terminal T2 flows through the first terminal T1. discharged

4 is a graph for comparing the voltage-current characteristics of the ESD protection device according to the present invention and the conventional LTDDSCR.

An experiment to confirm the characteristics of the ESD protection device 200 according to the present invention and the conventional LTDDSCR 100 was conducted using a TCAD Simulator manufactured by Synopsys, and the experimental results are the same as the experimental results of FIG. 4 .

Referring to FIG. 4 , the holding voltage of the conventional LTDDSCR 100 was measured to be 2V, whereas the ESD protection device 200 according to the present invention was measured to be 4.3V, which is the ESD protection device 200 according to the present invention. ), it can be seen that the holding voltage is increased by about 1.3V than that of the conventional LTDDSCR (100).

As described above, in the ESD protection device 200 according to the present invention, gates 221,241 are added on the N+ region 231 on the N well 230 and the P wells 220 and 240 in the conventional LTDDSCR 100 structure. And, by electrically connecting the added N+ region 231 and the gates 221,241 to each other, the parasitic PN diodes D1 and D2 are operated by the voltage applied to the gate during the ESD current discharge to operate with the PNP bipolar transistor Qp and The gain of the positive feedback loop of the NPN bipolar transistors Qn1 and Qn2 may be reduced. Therefore, it can have a high holding voltage characteristic. In addition, by forming a plurality of P+ crossing regions 251,261 and N+ crossing regions 252 and 262 to cross and connect to the terminals, the emitter current of the bipolar transistors Qn1 and Qn2 is reduced to increase the holding voltage by the lowered current gain. can Furthermore, since the ESD discharge in the forward direction and the ESD discharge in the reverse direction have a structure in which the discharge is symmetrical to each other, the effect on the high holding voltage formed in the forward direction can be applied equally in the reverse direction.

On the other hand, the embodiments of the present invention disclosed in the present specification and drawings are merely presented as specific examples to aid understanding, and are not intended to limit the scope of the present invention. It will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

201: semiconductor substrate 202: first P + bridge region
203: second P + bridge region 210: deep N well
220: first P well 221: first gate
230: N well 231: N + region
240: second P well 241: second gate
250: first impurity crossing region 251: first P+ crossing region
252: first N+ crossing region 260: second impurity crossing region
261: second P + crossing region 262: second N + crossing region

Claims (11)

semiconductor substrate;
a deep N-well formed on the semiconductor substrate;
a first P well formed on the deep N well and having a plurality of first impurity crossing regions formed by crossing impurities;
an N well formed on the deep N well, in contact with the first P well, and having an N + region;
a second P-well formed on the deep N-well and in contact with the N-well, the second P-well having a plurality of second impurity crossing regions formed by crossing impurities;
a first P+ bridge region formed to be in contact with the first P-well and the N-well; and
and a second P+ bridge region formed to be in contact with the N-well and the second P-well. According to claim 1,
a first gate formed on a surface of the first P well between the first impurity crossing region and the first P+ bridge region; and
and a second gate formed on a surface of the second P well between the second impurity crossing region and the second P+ bridge region. 3. The method of claim 2,
and the first gate, the N+ region, and the second gate are electrically connected to each other. According to claim 1,
the first impurity crossing region is connected to a first terminal;
and the second impurity crossing region is connected to a second terminal. The method of claim 1, wherein the first impurity crossing region comprises:
a first P+ cross region formed on the first P well; and
a first N+ crossing region formed on the first P well;
and a plurality of the first P+ crossing regions and the first N+ crossing regions are formed to cross each other in the longitudinal direction of the first P well on a plane. The method of claim 1, wherein the second impurity crossing region comprises:
a second P+ crossing region formed on the second P well; and
a second N+ crossing region formed on the second P well;
and a plurality of the second P+ crossing regions and the second N+ crossing regions are formed to cross each other in the longitudinal direction of the second P well on a plane. 3. The method of claim 2,
a PNP bipolar transistor formed by the first P+ bridge region, the N well, and the second P+ bridge region;
a first NPN bipolar transistor formed by the first impurity crossing region, the first P well, and the N well; and
and a second NPN bipolar transistor formed by the N well, the second P well, and the second impurity crossing region. 8. The method of claim 7,
When the PNP bipolar transistor and the second NPN bipolar transistor are turned on, a voltage is applied to the second gate through the N+ region. 8. The method of claim 7,
When the PNP bipolar transistor and the first NPN bipolar transistor are turned on, a voltage is applied to the first gate through the N+ region. According to claim 1,
a first PN diode formed by the second P+ bridge region and the second impurity crossing region; and
and a second PN diode formed by the first P+ bridge region and the first impurity crossing region. 3. The method of claim 2,
the first impurity crossing region, the first P+ bridge region, and the first gate are formed to be symmetrical to each other with the second impurity crossing region, the second P+ bridge region, and the second gate with respect to the N+ region. ESD protection device that is.

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