CN113053874B - Radiation-resistant high-voltage ESD semiconductor device - Google Patents
Radiation-resistant high-voltage ESD semiconductor device Download PDFInfo
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- CN113053874B CN113053874B CN202110279594.4A CN202110279594A CN113053874B CN 113053874 B CN113053874 B CN 113053874B CN 202110279594 A CN202110279594 A CN 202110279594A CN 113053874 B CN113053874 B CN 113053874B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The invention discloses a radiation-resistant high-voltage ESD semiconductor device, and belongs to the technical field of semiconductors. According to the invention, the P-type drift region is introduced on the upper surfaces of the P-type well region and the N-type well region, the withstand voltage between the P-type drift region and the N-type well region determines the trigger voltage of the ESD device, and the withstand voltage is consistent with the breakdown structure of the PMOS device, so that the internal device is protected during the circuit operation, and the ESD damage is avoided. The P-type first heavily doped region is introduced to the surface of the P-type well region, so that the base region concentration of a parasitic triode NPN device is increased, the base region transport coefficient is reduced, and the high-voltage ESD device is prevented from being started in advance under the condition of single-particle radiation, so that the single-particle latch-up resistance of the device is improved, and meanwhile, the holding voltage of the device is also improved. The P-type buried layer on the buried oxide layer reduces the emitter junction parallel resistance of the parasitic NPN triode, and improves the starting threshold of the parasitic NPN triode, so that the single particle latch-up resistance of the ESD device is further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a radiation-resistant high-voltage ESD semiconductor device.
Background
The electrostatic discharge phenomenon is widely present in nature and is one of the important causes of failure of integrated circuit products. Integrated circuit products are susceptible to electrostatic discharge during their manufacturing and assembly processes, resulting in reduced reliability and even damage to the products. Electrostatic Discharge (ESD) design is an important component of the reliability design of integrated circuits, and with the development of integrated circuit processes, more challenges are faced. The research on electrostatic discharge protection devices and circuits with high reliability and strong electrostatic protection performance has a considerable effect on improving the yield and reliability of integrated circuits. An SCR (Silicon Controlled Rectifier) device has the advantages of hysteresis, small on-resistance, small chip area occupation, maximum protection capability and the like, and is widely applied to solving the ESD problem. In a space radiation environment, the structure is triggered and conducted, a low-impedance large-current circuit is formed between a power supply and the ground, and the phenomenon that the circuit cannot work normally and even is burnt is called Single Event Latch-up (SEL). Particularly for radiation-resistant high voltage integrated circuits, the circuits and devices are more susceptible to ESD damage due to the high operating voltages. Therefore, in order to make the chip work normally in a severe irradiation environment, the integrated circuit must be reinforced against SEL.
Disclosure of Invention
The invention aims to provide a radiation-resistant high-voltage ESD semiconductor device, which is used for improving the single-particle latch-up resistance of a circuit on the basis of ensuring the ESD capability of a radiation-resistant high-voltage circuit.
In order to solve the technical problem, the invention provides a radiation-resistant high-voltage ESD semiconductor device which comprises a buried oxide layer, an N-type well region, a P-type drift region, a P-type first heavily doped region, a P-type second heavily doped region, a P-type buried layer, an N-type heavily doped region, an anode metal electrode and a cathode metal electrode;
the N-type well region and the P-type well region are arranged on the buried oxide layer, the P-type first heavily doped region is positioned at the top of the P-type well region, and the P-type buried layer is arranged at the bottom of the P-type well region; the P-type drift region is positioned at the top of the N-type well region and the P-type well region simultaneously; the P-type drift region (42) is transversely adjacent to the P-type first heavily doped region (43);
the P-type first heavily doped region and the N-type well region respectively comprise an N-type heavily doped region and a P-type second heavily doped region; the P-type drift region comprises another P-type second heavily doped region;
the anode metal electrode is arranged on the surface of the P-type well region, and the cathode metal electrode is arranged on the surface of the N-type well region.
Optionally, an N-type buried layer is disposed in the N-type well region, and the N-type buried layer is located at the bottom of the N-type well region and located at an upper interface of the buried oxide layer.
Optionally, the P-type drift region is in contact with the N-type well region and the P-type well region at the same time.
Optionally, the radiation-resistant high-voltage ESD semiconductor device further includes a P-type substrate located at the bottom of the buried oxide layer.
The invention provides a radiation-resistant high-voltage ESD semiconductor device which comprises a buried oxide layer, an N-type well region, a P-type drift region, a P-type first heavily doped region, a P-type second heavily doped region, a P-type buried layer, an N-type heavily doped region, an anode metal electrode and a cathode metal electrode; the N-type well region and the P-type well region are arranged on the buried oxide layer, the P-type first heavily doped region is positioned at the top of the P-type well region, and the P-type buried layer is arranged at the bottom of the P-type well region; the P-type drift region is positioned at the top of the N-type well region and the P-type well region simultaneously; the P-type first heavily doped region and the N-type well region respectively comprise an N-type heavily doped region and a P-type second heavily doped region; the P-type drift region comprises another P-type second heavily doped region; the anode metal electrode is arranged on the surface of the P-type well region, and the cathode metal electrode is arranged on the surface of the N-type well region. A P-type drift region is introduced on the upper surfaces of the P-type well region and the N-type well region, the withstand voltage between the P-type drift region and the N-type well region determines the trigger voltage of the ESD device, and the withstand voltage is consistent with the breakdown structure of the PMOS device, so that the circuit can protect internal devices during operation and avoid ESD damage. The P-type first heavily doped region is introduced to the surface of the P-type well region, so that the base region concentration of a parasitic triode NPN device is increased, the base region transport coefficient is reduced, and the high-voltage ESD device is prevented from being started in advance under the condition of single-particle radiation, so that the single-particle latch-up resistance of the device is improved, and meanwhile, the holding voltage of the device is also improved. The P-type buried layer on the buried oxide layer reduces the emitter junction parallel resistance of the parasitic NPN triode, and improves the starting threshold of the parasitic NPN triode, so that the single particle latch-up resistance of the ESD device is further improved.
Drawings
FIG. 1 is a diagram of a radiation-resistant high-voltage ESD semiconductor device provided by the present invention;
FIG. 2 is a second embodiment of a radiation-resistant high-voltage ESD semiconductor device provided in accordance with the present invention;
FIG. 3 is a third embodiment of a radiation-resistant high-voltage ESD semiconductor device provided by the present invention;
fig. 4 is a TLP result of the conventional high voltage ESD semiconductor device and the radiation-resistant high voltage ESD semiconductor device provided by the present invention;
fig. 5 shows the single-particle radiation characteristics of the conventional high-voltage ESD semiconductor device and the radiation-resistant high-voltage ESD semiconductor device provided by the present invention in the off-state.
Detailed Description
The radiation-resistant high-voltage ESD semiconductor device according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a radiation-resistant high-voltage ESD semiconductor device, the structure of which is shown in figure 1, and the device comprises a P-type substrate 11, a buried oxide layer 21, an N-type well region 31, a P-type well region 41, a P-type drift region 42, a P-type first heavily doped region 43, a P-type second heavily doped region 44, a P-type buried layer 45, an N-type heavily doped region 32, an anode metal electrode 51 and a cathode metal electrode 52; the N-type well region 31 and the P-type well region 41 are arranged on the buried oxide layer 21, the P-type first heavily doped region 43 is positioned at the top of the P-type well region 41, and the P-type buried layer 45 is arranged at the bottom of the P-type well region 41; the P-type drift region 42 is positioned on the tops of the N-type well region 31 and the P-type well region 41 at the same time and is in contact with the N-type well region 31 and the P-type well region 41 at the same time; the P-type first heavily doped region 43 and the N-type well region 31 respectively comprise an N-type heavily doped region 32 and a P-type second heavily doped region 44; the P-type drift region 42 comprises another P-type second heavily doped region 44; an anode metal electrode 51 is provided on the surface of the P-type well region 41, and a cathode metal electrode 52 is provided on the surface of the N-type well region 31. An N-type buried layer 33 is arranged in the N-type well region 31, and the N-type buried layer 33 is located at the bottom of the N-type well region 31 and located at the upper interface of the buried oxide layer 21.
On one hand, a P-type first heavily doped region 43 is introduced to the surface of the P-type well region 41, so that the NPN base region concentration of the parasitic triode is improved, the base region transport coefficient of the parasitic triode and the amplification factor of the triode are reduced, and the single particle latch-up resistance of the device can be improved; on the other hand, the P-type buried layer 45 is arranged on the lower interface of the P-type well region 41, so that the emitter junction parallel resistance of a parasitic triode in the P-type well region is reduced, the parasitic triode is prevented from being turned on under the condition of low current, the turn-on threshold of the parasitic NPN triode is improved, and the single event latch resistance of the device is improved. The P-type drift region 42 is arranged on the P-type well region 41 and the N-type well region 31 instead of the N-type drift region, so that the base region length and the concentration of the parasitic NPN triode are increased, the ESD device is prevented from being started in advance under the condition of single particle radiation, meanwhile, the P-type drift region 42 is consistent with the drift region of a conventional PMOS device, the whole process integration is facilitated, no extra mask is added, and the manufacturing cost of the device is reduced.
Furthermore, the P-type buried layer 45 on the buried oxide layer 21 can be formed without the need of single event resistance, thereby reducing the manufacturing cost of the device.
The working principle of the invention is as follows: when the ESD device is in a single-particle irradiation environment, the P-type first heavily doped region 43 reduces the base resistance of the parasitic NPN triode, reduces the amplification gain of the triode, reduces the single-particle radiation sensitivity of the device, and weakens the positive feedback effect of single-particle latch of the ESD device. The P-type buried layer 45 on the lower interface of the P-type well region 41 reduces the well resistance of the parasitic NPN triode, the emitter junction voltage drop of the parasitic NPN triode is lower for the given single-particle radiation generated current, and the single-particle latch-up effect of the device is avoided. When the ESD device is normally started, the parasitic NPN triode and the parasitic PNP triode form a mutual positive feedback function through larger current, and the internal device and the circuit are protected.
Referring to fig. 2, the radiation-resistant high-voltage ESD semiconductor device according to the present invention is provided, wherein an N-type buried layer 33 is disposed at a lower interface of the N-type well region 31, and the N-type buried layer 33 is located on the buried oxide layer 21. The N-type buried layer 31 further reduces the resistance of the N-type well region 31, the voltage drop on the parasitic PNP triode emitter junction is reduced under the condition of single-particle irradiation, the ESD device cannot be triggered, and the single-particle latch-up effect is avoided.
As shown in fig. 3, the radiation-resistant high-voltage ESD semiconductor device provided in the present invention is shown, wherein the P-type buried layer 45 is not formed in the P-type well region 41. The device comprises a P-type substrate 11, a buried oxide layer 21, an N-type well region 31, a P-type well region 41, a P-type drift region 42, a P-type first heavily doped region 43, an N-type heavily doped region 32, a P-type second heavily doped region 44, an anode metal electrode 51 and a cathode metal electrode 52. The P-type buried layer 45 is not used according to different single-particle radiation capability requirements, so that photoetching can be reduced, and the process manufacturing cost can be reduced.
As shown in fig. 4, the TLP result of the conventional high voltage ESD semiconductor device and the radiation-resistant high voltage ESD semiconductor device provided by the invention is shown. The minimum holding voltage of the conventional ESD device is only 23V, the holding voltage of the conventional ESD device using the P-type drift region 42 is about 39.6V, and the holding voltage of the device of the present invention is up to 41.7V. Meanwhile, the current density of the ESD device provided by the invention is about 38.4 mA/mum, and the current capability of the ESD device is not much different from that of the traditional ESD device.
Fig. 5 shows the single-particle radiation characteristics of the conventional high-voltage ESD semiconductor device and the radiation-resistant high-voltage ESD semiconductor device provided by the present invention in the off-state. It can be seen from the figure that under the condition that the single-particle radiation energy is 100MeV/mg/cm2, when the working voltage of the traditional ESD device is 30V, the large current is caused by the particle incidence but cannot be recovered, compared with a P-type drift region structure, the current generated by an N-type drift region structure is larger, and the single-particle latch-up effect is more obvious. The device of the invention causes larger current pulse when single particle incidence, but quickly recovers to the initial off-state, and the device does not generate single particle latch-up effect. This is because the P-type first heavily doped region 43 reduces the amplification gain of the parasitic NPN transistor, and the P-type buried layer 45 increases the turn-on threshold of the parasitic NPN transistor, thereby preventing turn-on of the ESD device caused by a single event.
According to the radiation-resistant high-voltage ESD semiconductor device, the P-type first heavily doped region is introduced into the surface of the P-type well region, the base region concentration of a parasitic triode NPN device is increased, the base region transport coefficient is reduced, and the high-voltage ESD device is prevented from being started in advance under the condition of single particle radiation, so that the single particle latch-up resistance of the device is improved, and meanwhile, the maintaining voltage of the device is also improved. The P-type buried layer reduces the emitter junction parallel resistance of the parasitic NPN triode, and improves the starting threshold of the parasitic NPN triode, so that the single particle latch-up resistance of the ESD device is further improved. The breakdown voltage and the trigger voltage of the ESD device are mainly determined by the junction breakdown voltage of the P-type drift region and the N-type well region, and for integrated circuits with different working voltages, the P-type drift region can adopt different process injection conditions to prevent ESD damage of devices in the circuits.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (4)
1. The radiation-resistant high-voltage ESD semiconductor device is characterized by comprising a buried oxide layer (21), an N-type well region (31), a P-type well region (41), a P-type drift region (42), a P-type first heavily doped region (43), a P-type second heavily doped region (44), a P-type buried layer (45), an N-type heavily doped region (32), an anode metal electrode (51) and a cathode metal electrode (52);
the N-type well region (31) and the P-type well region (41) are arranged on the buried oxide layer (21), the P-type first heavily doped region (43) is positioned at the top of the P-type well region (41), and the P-type buried layer (45) is arranged at the bottom of the P-type well region (41); the P-type drift region (42) is simultaneously positioned on the tops of the N-type well region (31) and the P-type well region (41); the P-type drift region (42) is transversely adjacent to the P-type first heavily doped region (43);
the P-type first heavily doped region (43) and the N-type well region (31) respectively comprise an N-type heavily doped region (32) and a P-type second heavily doped region (44); the P-type drift region (42) comprises another P-type second heavily doped region (44);
an anode metal electrode (51) is arranged on the surface of the P-type well region (41), and a cathode metal electrode (52) is arranged on the surface of the N-type well region (31).
2. The radiation-resistant high-voltage ESD semiconductor device according to claim 1, wherein an N-type buried layer (33) is disposed in the N-type well region (31), the N-type buried layer (33) being located at a bottom of the N-type well region (31) and at an upper interface of the buried oxide layer (21).
3. Radiation-resistant high-voltage ESD semiconductor device according to claim 1, characterized in that the P-drift region (42) is in contact with both the N-well region (31) and the P-well region (41).
4. Radiation-resistant high-voltage ESD semiconductor device according to any of claims 1-3, characterized in that it further comprises a P-type substrate (11) at the bottom of the buried oxide layer (21).
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| CN202110279594.4A CN113053874B (en) | 2021-03-16 | 2021-03-16 | Radiation-resistant high-voltage ESD semiconductor device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6410963B1 (en) * | 2001-10-16 | 2002-06-25 | Macronix International Co., Ltd. | Electrostatic discharge protection circuits with latch-up prevention function |
| CN103633087A (en) * | 2013-12-19 | 2014-03-12 | 电子科技大学 | Strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with ESD (Electro-Static Discharge) protective function |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102374203B1 (en) * | 2015-08-31 | 2022-03-15 | 삼성전자주식회사 | Electrostatic discharge protection device and electronic device having the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6410963B1 (en) * | 2001-10-16 | 2002-06-25 | Macronix International Co., Ltd. | Electrostatic discharge protection circuits with latch-up prevention function |
| CN103633087A (en) * | 2013-12-19 | 2014-03-12 | 电子科技大学 | Strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with ESD (Electro-Static Discharge) protective function |
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