CN113053874B - A radiation-resistant high-voltage ESD semiconductor device - Google Patents

Abstract

The invention discloses a radiation-resistant high-voltage ESD semiconductor device, and belongs to the technical field of semiconductors. According to the invention, the P-type drift region is introduced on the upper surfaces of the P-type well region and the N-type well region, the withstand voltage between the P-type drift region and the N-type well region determines the trigger voltage of the ESD device, and the withstand voltage is consistent with the breakdown structure of the PMOS device, so that the internal device is protected during the circuit operation, and the ESD damage is avoided. The P-type first heavily doped region is introduced to the surface of the P-type well region, so that the base region concentration of a parasitic triode NPN device is increased, the base region transport coefficient is reduced, and the high-voltage ESD device is prevented from being started in advance under the condition of single-particle radiation, so that the single-particle latch-up resistance of the device is improved, and meanwhile, the holding voltage of the device is also improved. The P-type buried layer on the buried oxide layer reduces the emitter junction parallel resistance of the parasitic NPN triode, and improves the starting threshold of the parasitic NPN triode, so that the single particle latch-up resistance of the ESD device is further improved.

Description

A radiation-resistant high-voltage ESD semiconductor device

technical field

The present invention relates to the technical field of semiconductors, in particular to a radiation-resistant high-voltage ESD semiconductor device.

Background technique

The phenomenon of electrostatic discharge widely exists in nature, and it is one of the important reasons for the failure of integrated circuit products. Integrated circuit products are easily affected by electrostatic discharge during their manufacturing and assembly processes, resulting in reduced product reliability or even damage. Electro-Static Discharge (ESD) design is an important part of integrated circuit reliability design, and with the development of integrated circuit technology, more challenges will be faced. The research on electrostatic discharge protection devices and circuits with high reliability and strong electrostatic protection performance plays an important role in improving the yield and reliability of integrated circuits. SCR (Silicon Controlled Rectifier, Silicon Controlled Rectifier) devices have the advantages of hysteresis characteristics, small on-resistance, small chip area occupation, and maximum protection capability, and are widely used to solve ESD problems. In the space radiation environment, the structure is triggered and turned on, forming a low-impedance and high-current circuit between the power supply and the ground, causing the circuit to fail to work normally, or even to burn out, which is called Single Event Latch-up (SEL, Single Event Latch-up). . Especially for radiation-hardened high-voltage integrated circuits, circuits and devices are more prone to ESD damage due to the high operating voltage. Therefore, in order to make the chip work normally in the harsh irradiation environment, the integrated circuit must be reinforced against SEL.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a radiation-resistant high-voltage ESD semiconductor device, so as to improve the anti-single-event latch-up capability of the circuit on the basis of ensuring the ESD capability of the radiation-resistant high-voltage circuit.

In order to solve the above technical problems, the present invention provides a radiation-resistant high-voltage ESD semiconductor device, including a buried oxide layer, an N-type well region, a P-type well region, a P-type drift region, a P-type first heavily doped region, and a P-type well region. a second heavily doped region, a P-type buried layer, an N-type heavily doped region, an anode metal electrode, and a cathode metal electrode;

The N-type well region and the P-type well region are arranged on the buried oxide layer, the P-type first heavily doped region is located at the top of the P-type well region, and the P-type buried layer is arranged at the bottom of the P-type well region; the P-type drift region is located at the same time The tops of the N-type well region and the P-type well region; the P-type drift region (42) is laterally adjacent to the P-type first heavily doped region (43);

The P-type first heavily doped region and the N-type well region respectively include an N-type heavily doped region and a P-type second heavily doped region; the P-type drift region includes another P-type the second heavily doped region;

The anode metal electrode is arranged on the surface of the P-type well region, and the cathode metal electrode is arranged on the surface of the N-type well region.

Optionally, an N-type buried layer is disposed in the N-type well region, and the N-type buried layer is located at the bottom of the N-type well region and at an upper interface of the buried oxide layer.

Optionally, the P-type drift region is in contact with both the N-type well region and the P-type well region.

Optionally, the radiation-hardened high-voltage ESD semiconductor device further includes a P-type substrate located at the bottom of the buried oxide layer.

The radiation-resistant high-voltage ESD semiconductor device provided by the present invention includes a buried oxide layer, an N-type well region, a P-type well region, a P-type drift region, a P-type first heavily doped region, and a P-type second heavily doped region. , P-type buried layer, N-type heavily doped region, anode metal electrode, cathode metal electrode; N-type well region and P-type well region are arranged on the buried oxide layer, P-type first heavily doped region is located in P-type well region On the top, the P-type buried layer is arranged at the bottom of the P-type well region; the P-type drift region is located on the top of both the N-type well region and the P-type well region; the P-type first heavily doped region and the N-type well region respectively include an N-type heavily doped region and a P-type second heavily doped region; the P-type drift region includes another P-type second heavily doped region; the anode metal electrode is arranged on the surface of the P-type well region , the cathode metal electrode is arranged on the surface of the N-type well region. A P-type drift region is introduced on the upper surface of the P-type well region and the N-type well region. The withstand voltage between the P-type drift region and the N-type well region determines the trigger voltage of the ESD device, and the withstand voltage is related to the breakdown of the PMOS device. The structure is consistent, so the internal devices will be protected during circuit operation to avoid ESD damage. The P-type first heavily doped region is introduced on the surface of the P-type well region, which increases the base region concentration of the parasitic triode NPN device, reduces the base region transport coefficient, and avoids single-particle radiation. The device's resistance to single-event latch-up also improves the device's sustain voltage. The P-type buried layer above the buried oxide layer reduces the parallel resistance of the emitter junction of the parasitic NPN triode, improves the turn-on threshold of the parasitic NPN triode, and further improves the anti-single event latch-up capability of the ESD device.

Description of drawings

1 is a radiation-resistant high-voltage ESD semiconductor device provided by the present invention;

2 is a second embodiment of the radiation-resistant high-voltage ESD semiconductor device provided by the present invention;

3 is a third embodiment of the radiation-resistant high-voltage ESD semiconductor device provided by the present invention;

4 is a TLP result of a conventional high-voltage ESD semiconductor device and a radiation-hardened high-voltage ESD semiconductor device provided by the present invention;

FIG. 5 is the single-event radiation characteristics of the conventional high-voltage ESD semiconductor device and the radiation-hardened high-voltage ESD semiconductor device provided by the present invention under the off-state condition.

Detailed ways

A radiation-resistant high-voltage ESD semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Example 1

The present invention provides a radiation-resistant high-voltage ESD semiconductor device, the structure of which is shown in FIG. 1 , including a P-type substrate 11 , a buried oxide layer 21 , an N-type well region 31 , a P-type well region 41 , and a P-type drift region 42 . , P-type first heavily doped region 43, P-type second heavily doped region 44, P-type buried layer 45, N-type heavily doped region 32, anode metal electrode 51, cathode metal electrode 52; N-type well region 31 The P-type well region 41 is arranged above the buried oxide layer 21, the P-type first heavily doped region 43 is located on the top of the P-type well region 41, and the P-type buried layer 45 is arranged at the bottom of the P-type well region 41; the P-type drift region 42 is located on top of the N-type well region 31 and the P-type well region 41 at the same time, and is in contact with the N-type well region 31 and the P-type well region 41 at the same time; the P-type first heavily doped region 43 and the N-type well region The regions 31 respectively include an N-type heavily doped region 32 and a P-type second heavily doped region 44; the P-type drift region 42 includes another P-type second heavily doped region 44; the anode metal electrode 51 The cathode metal electrode 52 is arranged on the surface of the P-type well region 41 , and the cathode metal electrode 52 is arranged on the surface of the N-type well region 31 . An N-type buried layer 33 is disposed in the N-type well region 31 , and the N-type buried layer 33 is located at the bottom of the N-type well region 31 and at the upper interface of the buried oxide layer 21 .

On the one hand, the P-type first heavily doped region 43 is introduced on the surface of the P-type well region 41 to increase the base region concentration of the parasitic triode NPN, thereby reducing the base region transport coefficient of the parasitic triode and the magnification of the triode, which can improve the On the other hand, a P-type buried layer 45 is arranged at the lower interface of the P-type well region 41 to reduce the parallel resistance of the emitter junction of the parasitic triode in the P-type well region, so as to avoid the parasitic triode in the smaller Turn-on occurs under the condition of high current, which improves the turn-on threshold of the parasitic NPN transistor, thereby improving the anti-single-event latch-up capability of the device. The P-type drift region 42 is set on the P-type well region 41 and the N-type well region 31 instead of the N-type drift region, which increases the base region length and concentration of the parasitic NPN transistor, and prevents the ESD device from turning on in advance in the case of single-particle radiation. At the same time, the P-type drift region 42 is consistent with the drift region of the conventional PMOS device, which facilitates the integration of the entire process and does not add additional masks, thereby reducing the manufacturing cost of the device.

Further, the P-type buried layer 45 on the buried oxide layer 21 may not be formed according to the requirement of anti-single particle capability, thereby reducing the manufacturing cost of the device.

The working principle of the present invention is as follows: when the ESD device is in a single-particle irradiation environment, the P-type first heavily doped region 43 reduces the parasitic NPN transistor base resistance, reduces the transistor's amplification gain, and makes the device's single-particle radiation The sensitivity decreases, and the positive feedback effect of single-event latch-up on ESD devices is weakened. The P-type buried layer 45 at the lower interface of the P-type well region 41 reduces the well resistance of the parasitic NPN triode. For a given current generated by single-event radiation, the emitter junction voltage drop of the parasitic NPN triode is lower, and the occurrence of single-event latch-up in the device is also avoided. lock effect. When the ESD device is normally turned on, the larger current makes the parasitic NPN transistor and the parasitic PNP transistor form a mutual positive feedback effect, and the internal devices and circuits are protected.

As shown in FIG. 2 , it is the radiation-resistant high-voltage ESD semiconductor device provided by the present invention, wherein an N-type buried layer 33 is provided at the lower interface of the N-type well region 31 , and the N-type buried layer 33 is located on the buried oxide layer 21 . The N-type buried layer 31 further reduces the resistance of the N-type well region 31. In the case of single-event irradiation, the voltage drop on the emitter junction of the parasitic PNP transistor is reduced, the ESD device will not be triggered, and the single-event latch-up effect will be avoided.

As shown in FIG. 3 , it is the radiation-resistant high-voltage ESD semiconductor device provided by the present invention, wherein the P-type buried layer 45 is not formed in the P-type well region 41 . The device includes P-type substrate 11, buried oxide layer 21, N-type well region 31, P-type well region 41, P-type drift region 42, P-type first heavily doped region 43, N-type heavily doped region 32, P-type Type second heavily doped region 44 , anode metal electrode 51 and cathode metal electrode 52 . According to the requirements of different single-particle radiation capabilities, choosing not to make the P-type buried layer 45 can also reduce photolithography and reduce process manufacturing costs.

As shown in FIG. 4 , it is the TLP result of the conventional high-voltage ESD semiconductor device and the radiation-hardened high-voltage ESD semiconductor device provided by the present invention. The figure shows that the sustaining voltage of the conventional ESD device is the lowest, only 23V. The conventional ESD device using the P-type drift region 42 has a higher sustaining voltage of about 39.6V, and the device of the present invention has the highest sustaining voltage of 41.7V. Meanwhile, the current density of the ESD device provided by the present invention is about 38.4 mA/μm, and the current capability is not much different from that of the traditional ESD device.

FIG. 5 is the single-event radiation characteristics of the conventional high-voltage ESD semiconductor device and the radiation-hardened high-voltage ESD semiconductor device provided by the present invention under the off-state condition. It can be seen from the figure that when the single particle radiation energy is 100MeV/mg/cm2, when the operating voltage of the traditional ESD device is 30V, the particle incident causes a large current but cannot be recovered. Compared with the P-type drift region structure, the N-type drift region structure. The resulting current is larger and the single-event latch-up effect is more pronounced. The device of the present invention causes a large current pulse when a single particle is incident, but quickly returns to the initial off-state state, and the device does not have a single-particle latch-up effect. This is because the P-type first heavily doped region 43 reduces the amplification gain of the parasitic NPN transistor, and the P-type buried layer 45 increases the turn-on threshold of the parasitic transistor to avoid turning on the ESD device caused by a single particle.

The radiation-resistant high-voltage ESD semiconductor device of the present invention introduces a P-type first heavily doped region on the surface of the P-type well region, increases the base region concentration of the parasitic triode NPN device, reduces the base region transport coefficient, and avoids single particle radiation. The high-voltage ESD device is turned on earlier, thereby improving the device's resistance to single-event latch-up, while also increasing the device's sustain voltage. The P-type buried layer reduces the parallel resistance of the emitter junction of the parasitic NPN triode, improves the opening threshold of the parasitic NPN triode, and further improves the anti-single event latch-up capability of the ESD device. The breakdown voltage and trigger voltage of ESD devices are mainly determined by the junction breakdown voltage of the P-type drift region and the N-type well region. For integrated circuits with different operating voltages, the P-type drift region can use different process injection conditions to prevent the internal circuit. ESD damage has occurred to the device.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (4)

1. The radiation-resistant high-voltage ESD semiconductor device is characterized by comprising a buried oxide layer (21), an N-type well region (31), a P-type well region (41), a P-type drift region (42), a P-type first heavily doped region (43), a P-type second heavily doped region (44), a P-type buried layer (45), an N-type heavily doped region (32), an anode metal electrode (51) and a cathode metal electrode (52);

the N-type well region (31) and the P-type well region (41) are arranged on the buried oxide layer (21), the P-type first heavily doped region (43) is positioned at the top of the P-type well region (41), and the P-type buried layer (45) is arranged at the bottom of the P-type well region (41); the P-type drift region (42) is simultaneously positioned on the tops of the N-type well region (31) and the P-type well region (41); the P-type drift region (42) is transversely adjacent to the P-type first heavily doped region (43);

the P-type first heavily doped region (43) and the N-type well region (31) respectively comprise an N-type heavily doped region (32) and a P-type second heavily doped region (44); the P-type drift region (42) comprises another P-type second heavily doped region (44);

an anode metal electrode (51) is arranged on the surface of the P-type well region (41), and a cathode metal electrode (52) is arranged on the surface of the N-type well region (31).

2. The radiation-resistant high-voltage ESD semiconductor device according to claim 1, wherein an N-type buried layer (33) is disposed in the N-type well region (31), the N-type buried layer (33) being located at a bottom of the N-type well region (31) and at an upper interface of the buried oxide layer (21).

3. Radiation-resistant high-voltage ESD semiconductor device according to claim 1, characterized in that the P-drift region (42) is in contact with both the N-well region (31) and the P-well region (41).

4. Radiation-resistant high-voltage ESD semiconductor device according to any of claims 1-3, characterized in that it further comprises a P-type substrate (11) at the bottom of the buried oxide layer (21).

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