CN103633087A - Strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with ESD (Electro-Static Discharge) protective function - Google Patents
Strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with ESD (Electro-Static Discharge) protective function Download PDFInfo
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Abstract
The invention relates to the electronic technology and specifically relates to a strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with an ESD (Electro-Static Discharge) protective function. The LIGBT device isolates an N-type epitaxial layer 3 by an isolation area 13 into two parts; a first P-type well region 4 and an N-type well region 6 are arranged in the N-type epitaxial layer 3 at one side of the isolation area 13; a second P-type well region 5 is arranged in the N-type epitaxial layer 3 at the other end of the isolation area 13; and a second N-type heavy doping region 22 and a third N-type heavy doping region 23 which are independent with each other are arranged in the second P-type well region 5. The strong anti-latch-up controllable LIGBT device disclosed by the invention has the beneficial effects that on an no-power condition, current is leaked by a parasitic SCR (Semiconductor Control Rectifier), so that ESD ability is very strong; under a power-on state, the parasitic SCR of the LIGBT cannot be started and snapback is not generated, so that maintaining voltage higher than breakdown voltage is achieved, and therefore, the anti-lath-up ability is very strong. The strong anti-latch-up controllable LIGBT device disclosed by the invention is especially suitable for the LIGBT device used for ESD protection.
Description
Technical field
The present invention relates to electronic technology; the static that relates to specifically semiconductor integrated circuit chip discharges (ElectroStatic Discharge; referred to as ESD) protecting circuit designed technology; lateral insulated gate bipolar transistor (a Lateral Insulated Gate Transistors is called for short LIGBT) the esd protection device espespecially with high latch up immunity.
Background technology
In chip production, encapsulation, test, deposit, in handling process, static discharge is as a kind of inevitable natural phenomena and ubiquity.Along with the development with various advanced technologies that reduces of integrated circuit technology characteristic size, the situation that chip is damaged by ESD phenomenon is more and more general, and relevant research shows, 30% of ic failure product is all owing to suffering static discharge phenomenon caused.Therefore, use high performance ESD protective device to be protected and seem very important chip internal circuit.
LIGBT has very high current drain ability under identical area; there is very much high voltage endurance capability simultaneously; common LIGBT esd protection structure has two kinds; a kind of is that snapback phenomenon occurs when leakage current; a kind of is snapback phenomenon not to occur when leakage current (snapback phenomenon is rapid bow tie; be due to device inside breakdown after; the unlatching of parasitic BJT; thereby cause electric current to increase; voltage but reduces; on I-V curve, the rotating phenomenon of performance meeting curve, is therefore called rapid bow tie).
Occur snapback phenomenon LIGBT esd protection device structure as shown in Figure 1, comprising: the P type well region 4 on P type substrate 1, substrate on insulating barrier 2, N epitaxial loayer 3, N epitaxial loayer, the N-type well region 6 on N epitaxial loayer, field oxide 8, polysilicon gate 9, thin oxide layer 10, for the isolated area 13 of isolated high-voltage device and low-voltage device, N-type heavily doped region 21, two P type heavily doped regions 31 and 32.Insulating barrier 2 is positioned at the top that P type substrate 1 ，NXing epitaxial region, top 3 is positioned at insulating barrier 2, and P type well region 4 and N-type well region 6 are positioned at the top of N-type epitaxial region.N-type heavily doped region 21 and a P type heavily doped region 31 are positioned at the ，NXing heavily doped region, top 21 of P type well region 4 between the first P type heavily doped region 31 and polysilicon gate 9.The 2nd P type heavily doped region 32 is positioned at the top of N-type well region 6, and the 2nd P type heavily doped region 32 is as anode; N-type heavily doped region 21 and a P type heavily doped region 31 are as negative electrode.Its structure comprises a parasitic PNP triode Q1(and is comprised of the 2nd P type heavily doped region 32, N-type extension and a P type well region), a parasitic NPN triode Q2(is comprised of the first N-type heavily doped region 21, a P type well region 4 and N-type extension) and the dead resistance R in P well region district
b.When anode pin occurs that a positive ESD voltage (is that anode is positive voltage, negative electrode is zero potential) time, N-epi/P trap knot is partially anti-, and avalanche breakdown occurs, and breakdown potential fails to be convened for lack of a quorum and on RB, produces pressure drop, when pressure drop is greater than 0.7V, BJT Q2 conducting, and the collector current of Q2 provides electric current by the base stage for Q1, after Q1 conducting, its collector current will provide base current for Q2, final Q1, Q2 form positive feedback, and parasitic SCR structure conducting is with the ESD electric current of releasing.Because SCR parasitic after LIGBT conducting works, so relieving capacity is very strong, but it is very little to maintain voltage; therefore when the protection between VDD and VSS; easily produce breech lock (latch-up) phenomenon, cause power supply continuous discharge, finally burn out esd protection circuit.
Do not have the structure chart of LIGBT esd protection device of snapback phenomenon identical with Fig. 1, just the doping content of P trap is high, has reduced the dead resistance R of P well region
b, make to be added in R when On current
bon voltage be less than 0.7V, parasitic NPN can not open, and therefore snapback phenomenon can not occur.Its TLP curve as shown in Figure 2, due to snapback phenomenon not occurring, therefore has the very high voltage that maintains, and has very strong anti-breech lock ability.
Summary of the invention
To be solved by this invention, be exactly for the problems referred to above, a kind of controlled LIGBT device of strong anti-breech lock with esd protection function is proposed.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of controlled LIGBT device of strong anti-breech lock with esd protection function, comprise P type substrate 1, be positioned at the insulating barrier 2 and the N-type epitaxial loayer 3 that is positioned at insulating barrier 2 upper surfaces of P type substrate 1 upper surface, in described N-type epitaxial loayer 3, be provided with isolated area 13 N-type epitaxial loayer 3 is isolated into two parts, in the N-type epitaxial loayer 3 of described isolated area 13 1 sides, be provided with P type well region 4 and a N-type well region 6, in a described P type well region 4, be provided with the first separate N-type heavily doped region 21 and a P type heavily doped region 31, in described N-type well region 6, be provided with the 2nd P type heavily doped region 32, the upper surface of described N-type epitaxial loayer 3 arranges field oxide 8 and the first thin oxide layer 10, described the first thin oxide layer 10 is connected with field oxide 8 with the upper surface of a P type well region 4, described field oxide 8 is connected with the upper surface of N-type well region 6, the upper surface of described the first thin oxide layer 10 is provided with the first polysilicon gate 9, in described N-type epitaxial loayer 3, be provided with isolated area 13, it is characterized in that, in the N-type epitaxial loayer 3 of described isolated area 13 opposite sides, be provided with the second separate N-type heavily doped region 22 and the 3rd N-type heavily doped region 23, the upper surface of the N-type epitaxial loayer 3 between the second N-type heavily doped region 22 and the 3rd N-type heavily doped region 23 is provided with the second thin oxide layer 12, described the second thin oxide layer 12 upper surfaces are provided with the second polysilicon gate 11, described the second N-type heavily doped region 22 is connected by wire with a P type heavily doped region 31, described the first polysilicon gate 9 is connected with the 3rd N-type heavily doped region 23 with the first N-type heavily doped region 21.
Concrete, described N-type epitaxial loayer 3 is also provided with the 3rd P type heavily doped region 7, and described the first N-type heavily doped region 21 and a P type heavily doped region 31 are arranged in the 3rd P type heavily doped region 7, and the doping depth of described the 3rd P type heavily doped region 7 is greater than a P type well region 4.
Concrete, described N-type epitaxial loayer 3 is also provided with the 2nd P type well region 5, and described the second N-type heavily doped region 22 and the 3rd N-type heavily doped region 23 are arranged in the 2nd P type well region 5.
Beneficial effect of the present invention is, under electrifying condition not, by parasitic SCR leakage current, has very strong ESD ability; Under electrifying condition, the parasitic SCR of LIGBT can not open, and snapback can not occur, and has the voltage that maintains higher than puncture voltage, therefore has very strong anti-breech lock ability.
Accompanying drawing explanation
Fig. 1 is prior art LIGBT device profile schematic diagram;
Fig. 2 is the TLP curve chart that there is no the LIGBT esd protection structure of snapback phenomenon;
Fig. 3 is embodiment 1 structural representation;
Fig. 4 is the equivalent circuit diagram of embodiment 1;
Fig. 5 is the TLP resolution chart of LIGBT in embodiment 1;
Fig. 6 is the structural representation of embodiment 2;
Fig. 7 is the structural representation of embodiment 3;
Fig. 8 is the structural representation of embodiment 4.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
The invention provides a kind of controlled LIGBT esd protection device with strong anti-breech lock ability.This device, under electrifying condition not, by parasitic SCR leakage current, has very strong ESD ability; Under electrifying condition, the parasitic SCR of LIGBT can not open, and snapback can not occur, and has the voltage that maintains higher than puncture voltage, therefore has very strong anti-breech lock ability.
Embodiment 1:
As shown in Figure 3, for this routine structural representation, comprise P type substrate 1, be positioned at the insulating barrier 2 and the N-type epitaxial loayer 3 that is positioned at insulating barrier 2 upper surfaces of P type substrate 1 upper surface, in described N-type epitaxial loayer 3, be provided with isolated area 13 N-type epitaxial loayer 3 is isolated into two parts, in the N-type epitaxial loayer 3 of described isolated area 13 1 sides, be provided with P type well region 4 and a N-type well region 6, in a described P type well region 4, be provided with the first separate N-type heavily doped region 21 and a P type heavily doped region 31, in described N-type well region 6, be provided with the 2nd P type heavily doped region 32, the upper surface of described N-type epitaxial loayer 3 arranges field oxide 8 and the first thin oxide layer 10, described the first thin oxide layer 10 is connected with field oxide 8 with the upper surface of a P type well region 4, described field oxide 8 is connected with the upper surface of N-type well region 6, the upper surface of described the first thin oxide layer 10 is provided with the first polysilicon gate 9, in described N-type epitaxial loayer 3, be provided with isolated area 13, in the N-type epitaxial loayer 3 of described isolated area 13 opposite sides, be provided with the second separate N-type heavily doped region 22 and the 3rd N-type heavily doped region 23, the upper surface of the N-type epitaxial loayer 3 between the second N-type heavily doped region 22 and the 3rd N-type heavily doped region 23 is provided with the second thin oxide layer 12, described the second thin oxide layer 12 upper surfaces are provided with the second polysilicon gate 11, described the second N-type heavily doped region 22 is connected by wire with a P type heavily doped region 31, described the first polysilicon gate 9 is connected with the 3rd N-type heavily doped region 23 with the first N-type heavily doped region 21, at N-type epitaxial loayer 3, be also provided with the 2nd P type well region 5, described the second N-type heavily doped region 22 and the 3rd N-type heavily doped region 23 are arranged in the 2nd P type well region 5.
Operation principle:
As shown in Figure 4, for this routine equivalent circuit diagram, comprise a parasitic PNP triode Q1(and formed by the 2nd P type heavily doped region 32, N-type epitaxial loayer 3 and a P type well region 4), a parasitic NPN triode Q2(is comprised of the first N-type heavily doped region 21, a P type well region 4 and N-type epitaxial loayer 3), a parasitic gate grounding NMOS pipe M1 (being formed by N-type epitaxial loayer 3, a P type well region 4, the first N-type heavily doped region 21, the first thin oxide layer 10, the first polysilicon gate 9), dead resistance R
b, additional grounded-grid nmos pass transistor M2(by the 2nd P type well region 5, the second N-type heavily doped region 22, the 3rd N-type heavily doped region 23, the second polysilicon gate 11 and the second thin oxide layer 12, formed).
Under chip does not have electrifying condition, M2 raceway groove is in off state, if there is a positive ESD voltage in the anode pin in Fig. 3 structure now, a N epitaxial loayer 3/ P type well region 4 is binded up one's hair raw partially anti-, there is avalanche breakdown, because M2 is in off state, electric current will can not flow through from a P type heavily doped region 31, but flow into negative electrode from the first N-type heavily doped region 21, parasitic NPN triode Q2 opens, form positive feedback with parasitic PNP triode Q1, cause parasitic SCR to open, therefore there is the ability of very strong leakage current, and now anode and negative electrode do not have additional power source, do not worry occurring latch-up.The in the situation that of chip power, be that the grid (the second polysilicon gate 11) of anode, negative electrode and NMOS is while all having applied voltage, due to the grid of NMOS additional forward low pressure source, make M2 raceway groove in conducting state, if now noise pulse appears in anode pin, N extension/one P type well region 4 is binded up one's hair raw partially anti-, and avalanche breakdown occurs, the hole producing enters a P type heavily doped region 31 by a P well region, by M2, flows to negative electrode.Because the doping content of a P type well region 4 is larger, be added in dead resistance R
bon voltage very little.Fig. 5 has provided the TLP test curve of LIGBT, its inefficacy electric current is 1mA/um, and NMOS is under raceway groove opening, maximum On current can arrive 1mA/um, because NMOS is very little with respect to the area of LIGBT, we can increase the width of NMOS again, make it when leakage current, be operated in variable resistor district, and guarantee that the drain-source voltage of NMOS is less than 0.5V before On current reaches the inefficacy electric current of LIGBT.Therefore can be less than 0.7V so that be added in A point in Fig. 4 (being added in the voltage on the P trap of 21 times, the first N-type heavily doped region) voltage, that is to say, the applied voltage of the emitter junction of parasitic NPN triode Q2 is less than 0.5V, and Q2 can not open, so this structure snapback phenomenon can not occur.There is the voltage that maintains higher than puncture voltage, therefore there is very strong anti-breech lock ability.
In addition, the grid voltage that we also can be by improving NMOS to be to reduce the conducting resistance of NMOS, and the drain-source voltage while reducing NMOS conducting also can increase the doping content of the P well region of LIGBT, reduces the dead resistance R in the P well region district of LIGBT
b, A point voltage in Fig. 4 is strict controlled in below 0.7V, guarantee that under electrifying condition, parasitic NPN triode Q2 can not open, and to avoid latch-up
Fig. 5 is the TLP resolution chart of the LIGBT in the specific embodiment of the invention one.The doping content of a P type well region 4 of this LIGBT is higher, carries out the result demonstration of TLP test, and snapback phenomenon does not occur the I-V curve of this structure, and under the condition that is 600um at device widths, inefficacy electric current I t2 is 0.6A, is 1mA/um.
Embodiment 2:
As shown in Figure 6, this example is on the architecture basics of embodiment 1, under the first N-type heavily doped region 21 and a P type heavily doped region 31, add a P-sink doped region 7, and P-sink doped region is wrapped in the first N-type heavily doped region 21 and a P type heavily doped region 31, the degree of depth of the depth ratio of a P-sink doped region 7 P type well region 4 is large, and the doping content of the P type well region in this structure relatively and a P type well region of structure shown in Fig. 3 lower, improved the withstand voltage of LIGBT, and the doping content of the P-sink doped region 7 of this structure is higher.
This example is identical with the operation principle of embodiment 1, and difference is that the relative concentration of P-sink doped region is larger in P well region, is therefore added in dead resistance R
bvoltage less, more easily guarantee under electrifying condition, parasitic NPN triode Q2 can not open, and therefore has better anti-breech lock ability.
Embodiment 3:
As shown in Figure 7, on the basis of this routine embodiment 1, delete the 2nd P type well region 5, change the second N-type heavily doped region 22 and the 3rd N-type heavily doped region 23 into the 3rd P type heavily doped region 33 and the 4th P type heavily doped region 34.Multi-crystal silicon area 11 is wired to negative sense low pressure source.
This example is identical with the operation principle of embodiment 1.What difference was to adopt is the structure that LIGBT connects with PMOS, need to be at the grid of PMOS additional reverse low pressure, with this, control the unlatching of the parasitic SCR of LIGBT.
Embodiment 4:
As shown in Figure 8, this example is on the basis of embodiment 3, under the first N-type heavily doped region 21 and a P type heavily doped region 31, add a P-sink doped region 7, and P-sink doped region is wrapped in the first N-type heavily doped region 21 and a P type heavily doped region 31, the degree of depth of the depth ratio of a P-sink doped region 7 P type well region 4 is large, and the doping content of the P type well region in this structure relatively and a P type well region of structure shown in Fig. 3 lower, improved the withstand voltage of LIGBT, and the doping content of the P-sink doped region 7 of this structure is higher.Multi-crystal silicon area 11 is wired to negative sense low pressure source.
This example is identical with the operation principle of embodiment 1.What difference was to adopt is the structure that LIGBT connects with PMOS, need to be at the grid of PMOS additional reverse low pressure, with this, control the unlatching of the parasitic SCR of LIGBT.
Claims (3)
1. the controlled LIGBT device of strong anti-breech lock with esd protection function, comprise P type substrate (1), be positioned at the insulating barrier (2) of P type substrate (1) upper surface and be positioned at the N-type epitaxial loayer (3) of insulating barrier (2) upper surface, in described N-type epitaxial loayer (3), be provided with isolated area (13) N-type epitaxial loayer (3) is isolated into two parts, in the N-type epitaxial loayer (3) of described isolated area (13) one sides, be provided with a P type well region (4) and N-type well region (6), in a described P type well region (4), be provided with the first separate N-type heavily doped region (21) and a P type heavily doped region (31), in described N-type well region (6), be provided with the 2nd P type heavily doped region (32), the upper surface of described N-type epitaxial loayer (3) arranges field oxide (8) and the first thin oxide layer (10), described the first thin oxide layer (10) is connected with field oxide (8) with the upper surface of a P type well region (4), described field oxide (8) is connected with the upper surface of N-type well region (6), the upper surface of described the first thin oxide layer (10) is provided with the first polysilicon gate (9), in described N-type epitaxial loayer (3), be provided with isolated area (13), it is characterized in that, in the N-type epitaxial loayer (3) of described isolated area (13) opposite side, be provided with the second separate N-type heavily doped region (22) and the 3rd N-type heavily doped region (23), the upper surface of the N-type epitaxial loayer (3) between the second N-type heavily doped region (22) and the 3rd N-type heavily doped region (23) is provided with the second thin oxide layer (12), described the second thin oxide layer (12) upper surface is provided with the second polysilicon gate (11), described the second N-type heavily doped region (22) is connected by wire with a P type heavily doped region (31), described the first polysilicon gate (9) is connected with the 3rd N-type heavily doped region (23) with the first N-type heavily doped region (21).
2. a kind of controlled LIGBT device of strong anti-breech lock with esd protection function according to claim 1; it is characterized in that; described N-type epitaxial loayer (3) is also provided with the 3rd P type heavily doped region (7); described the first N-type heavily doped region (21) and a P type heavily doped region (31) are arranged in the 3rd P type heavily doped region (7), and the doping depth of described the 3rd P type heavily doped region (7) is greater than a P type well region (4).
3. a kind of controlled LIGBT device of strong anti-breech lock with esd protection function according to claim 1 and 2; it is characterized in that; described N-type epitaxial loayer (3) is also provided with the 2nd P type well region (5), and described the second N-type heavily doped region (22) and the 3rd N-type heavily doped region (23) are arranged in the 2nd P type well region (5).
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| CN103972233A (en) * | 2014-05-30 | 2014-08-06 | 电子科技大学 | SCR (Semiconductor Control Rectifier) shut-off device with latching resistant capability |
| CN104078498A (en) * | 2014-07-14 | 2014-10-01 | 东南大学 | Trench isolation lateral insulated gate bipolar transistor |
| CN104701362A (en) * | 2015-03-23 | 2015-06-10 | 东南大学 | Trench-isolated and lateral insulated-gate bipolar transistor |
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| CN104078498A (en) * | 2014-07-14 | 2014-10-01 | 东南大学 | Trench isolation lateral insulated gate bipolar transistor |
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| CN104701362A (en) * | 2015-03-23 | 2015-06-10 | 东南大学 | Trench-isolated and lateral insulated-gate bipolar transistor |
| CN110034176A (en) * | 2019-04-22 | 2019-07-19 | 东南大学 | Solve the inverse conductivity type landscape insulation bar double-pole-type transistor of Reverse recovery failure |
| CN110034176B (en) * | 2019-04-22 | 2022-02-11 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor for solving reverse recovery failure |
| CN111668209A (en) * | 2020-06-10 | 2020-09-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| CN111668209B (en) * | 2020-06-10 | 2022-03-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| CN112687681A (en) * | 2020-12-29 | 2021-04-20 | 电子科技大学 | LIGBT device with integrated NMOS tube |
| CN113053874A (en) * | 2021-03-16 | 2021-06-29 | 中国电子科技集团公司第五十八研究所 | Radiation-resistant high-voltage ESD semiconductor device |
| CN113053874B (en) * | 2021-03-16 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Radiation-resistant high-voltage ESD semiconductor device |
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