CN103633087B - A kind of strong anti-breech lock controlled LIGBT device with ESD defencive function - Google Patents
A kind of strong anti-breech lock controlled LIGBT device with ESD defencive function Download PDFInfo
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Abstract
The present invention relates to electronic technology, particularly relate to a kind of strong anti-breech lock controlled LIGBT device with ESD defencive function.The LIGBT device of the present invention, by isolation area 13, N-type epitaxy layer 3 is isolated into two parts, the N-type epitaxy layer 3 of side, isolation area 13 is provided with the first P type trap zone 4 and N-type well region 6, the N-type epitaxy layer 3 of isolation area 13 opposite side is provided with the second P type trap zone 5, the second P type trap zone 5 is provided with the second separate N-type heavily doped region 22 and the 3rd N-type heavily doped region 23.Beneficial effects of the present invention is, under not electrifying condition, by parasitic SCR leakage current, has the strongest ESD ability；Under electrifying condition, the parasitic SCR of LIGBT can not open, and snapback will not occur, and has the maintenance voltage higher than breakdown voltage, therefore has the strongest latch-up immunity.Present invention is particularly suitable for the LIGBT device for ESD protection.
Description
Technical field
The present invention relates to electronic technology, particularly relate to the Electro-static Driven Comb (ElectroStatic of semiconductor integrated circuit chip
Discharge, referred to as ESD) protecting circuit designed technology, a kind of lateral isolation with high latch up immunity
Grid bipolar transistor (Lateral Insulated Gate Transistors is called for short LIGBT) ESD protective device.
Background technology
Chip production, encapsulate, test, deposit, in handling process, static discharge is as the inevitable natural phenomena of one
And generally exist.Along with reducing and the development of various advanced technologies of integrated circuit technology characteristic size, chip is damaged by ESD event
Situation about ruining is more and more universal, and relevant research shows, the 30% of ic failure product is all owing to suffering static discharge
Caused by phenomenon.Therefore, high performance ESD protection device is used to be protected by chip internal circuits seeming particularly significant.
LIGBT has the highest current drain ability under identical area, has very much high voltage endurance capability simultaneously, common
LIGBT esd protection structure has two kinds, and one is the generation snapback phenomenon when leakage current, and one is when leakage current
Do not occur snapback phenomenon (snapback phenomenon is rapid bow tie, be due to device inside breakdown after, parasitic BJT
Unlatching, thus cause electric current to increase, voltage but reduces, on I-V curve performance can the phenomenon of curve revolution, because being referred to herein as
Rapid bow tie).
Occur the structure of LIGBT ESD protective device of snapback phenomenon as it is shown in figure 1, include: P type substrate 1, substrate
P type trap zone 4 on upper insulating barrier 2, N epitaxial layer 3, N epitaxial layer, the N-type well region 6 on N epitaxial layer, field oxide 8,
Polysilicon gate 9, thin oxide layer 10, for isolating high tension apparatus and the isolation area 13 of low-voltage device, N-type heavily doped region 21, two
Individual p-type heavily doped region 31 and 32.Insulating barrier 2 is positioned at P type substrate 1 top, and N-type epitaxial region 3 is positioned at the top of insulating barrier 2,
P type trap zone 4 and N-type well region 6 are positioned at the top of N-type epitaxial region.N-type heavily doped region 21 and the first p-type heavily doped region 31
In the top of P type trap zone 4, N-type heavily doped region 21 is between the first p-type heavily doped region 31 and polysilicon gate 9.2nd P
Type heavily doped region 32 is positioned at the top of N-type well region 6, and the second p-type heavily doped region 32 is as anode；N-type heavily doped region 21 He
First p-type heavily doped region 31 is as negative electrode.Its structure comprises parasitic PNP triode Q1(by the second p-type heavily doped region
32, N-type extension and the first P type trap zone composition), parasitic NPN audion Q2(by the first N-type heavily doped region 21, the
One P type trap zone 4 and N-type extension composition) and dead resistance R in p-well region districtB.When a positive ESD voltage occurs in anode pin
Time (i.e. anode is positive voltage, and negative electrode is zero potential), N-epi/P trap knot is reverse-biased, and avalanche breakdown occurs, and breakdown current can be
Producing pressure drop on RB, when pressure drop is more than 0.7V, BJT Q2 turns on, and the base stage for Q1 is provided electricity by the collector current of Q2
Stream, after Q1 conducting, its collector current will provide base current for Q2, and final Q1, Q2 form positive feedback, parasitic SCR knot
Structure turns on ESD electric current of releasing.SCR parasitic after turning on due to LIGBT works, and therefore relieving capacity is very strong, but maintains
Voltage is the least, therefore when the protection between VDD and VSS, easily produces breech lock (latch-up) phenomenon, causes power supply
Continuous discharge, finally burns out esd protection circuit.
The structure chart not having the LIGBT ESD protective device of snapback phenomenon is identical with Fig. 1, and simply the doping content of p-well is high,
Reduce dead resistance R of p-well regionBSo that it is added in R when turning on electric currentBOn voltage less than 0.7V, parasitic NPN will not
Open, thus without snapback phenomenon occurs.Its TLP curve as in figure 2 it is shown, owing to not there is snapback phenomenon,
Therefore there is the highest maintenance voltage, there is the strongest latch-up immunity.
Summary of the invention
To be solved by this invention, it is simply that for the problems referred to above, a kind of strong anti-breech lock with ESD defencive function is proposed controlled
LIGBT device.
The present invention solves above-mentioned technical problem and be the technical scheme is that a kind of strong anti-breech lock with ESD defencive function is controlled
LIGBT device, the insulating barrier 2 including P type substrate 1, being positioned at P type substrate 1 upper surface and the N being positioned at insulating barrier 2 upper surface
Type epitaxial layer 3, is provided with isolation area 13 and N-type epitaxy layer 3 is isolated into two parts in described N-type epitaxy layer 3, described every
The first P type trap zone 4 and N-type well region 6 it is provided with, in described first P type trap zone 4 in the N-type epitaxy layer 3 of side, district 13
It is provided with the first separate N-type heavily doped region 21 and the first p-type heavily doped region 31, described N-type well region 6 is provided with
Second p-type heavily doped region 32, the upper surface of described N-type epitaxy layer 3 arranges field oxide 8 and the first thin oxide layer 10, described
First thin oxide layer 10 is connected with upper surface and the field oxide 8 of the first P type trap zone 4, described field oxide 8 and N-type well region
The upper surface of 6 connects, and the upper surface of described first thin oxide layer 10 is provided with the first polysilicon gate 9, described N-type epitaxy layer 3
In be provided with isolation area 13, it is characterised in that the N-type epitaxy layer 3 of described isolation area 13 opposite side is provided with separate
The second N-type heavily doped region 22 and the 3rd N-type heavily doped region 23, in the second N-type heavily doped region 22 and the 3rd N-type heavy doping
The upper surface of the N-type epitaxy layer 3 between district 23 is provided with the second thin oxide layer 12, and described second thin oxide layer 12 upper surface sets
Being equipped with the second polysilicon gate 11, described second N-type heavily doped region 22 and the first p-type heavily doped region 31 are connected by wire, institute
State the first polysilicon gate 9 to be connected with the first N-type heavily doped region 21 and the 3rd N-type heavily doped region 23.
Concrete, described N-type epitaxy layer 3 is additionally provided with the 3rd p-type heavily doped region 7, described first N-type heavily doped region 21 He
First p-type heavily doped region 31 is positioned in the 3rd p-type heavily doped region 7, and the doping depth of described 3rd p-type heavily doped region 7 is more than
First P type trap zone 4.
Concrete, described N-type epitaxy layer 3 is additionally provided with the second P type trap zone 5, described second N-type heavily doped region 22 and the 3rd
N-type heavily doped region 23 is positioned in the second P type trap zone 5.
Beneficial effects of the present invention is, under not electrifying condition, by parasitic SCR leakage current, has the strongest ESD ability；
Under electrifying condition, the parasitic SCR of LIGBT can not open, and snapback will not occur, and has the maintenance electricity higher than breakdown voltage
Pressure, therefore has the strongest latch-up immunity.
Accompanying drawing explanation
Fig. 1 is prior art LIGBT device profile schematic diagram；
Fig. 2 is the TLP curve chart of the LIGBT esd protection structure not having snapback phenomenon；
Fig. 3 is embodiment 1 structural representation；
Fig. 4 is the equivalent circuit diagram of embodiment 1；
Fig. 5 is the TLP test figure of LIGBT in embodiment 1；
Fig. 6 is the structural representation of embodiment 2；
Fig. 7 is the structural representation of embodiment 3；
Fig. 8 is the structural representation of embodiment 4.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, technical scheme is described in detail:
The invention provides a kind of controlled LIGBT ESD protective device with strong latch-up immunity.This device is in not electrifying condition
Under, by parasitic SCR leakage current, there is the strongest ESD ability；Under electrifying condition, the parasitic SCR of LIGBT can not
Open, snapback will not occur, there is the maintenance voltage higher than breakdown voltage, therefore there is the strongest latch-up immunity.
Embodiment 1:
As it is shown on figure 3, be the structural representation of this example, including P type substrate 1, the insulating barrier 2 that is positioned at P type substrate 1 upper surface
Be positioned at the N-type epitaxy layer 3 of insulating barrier 2 upper surface, described N-type epitaxy layer 3 is provided with isolation area 13 by N-type epitaxy layer
3 are isolated into two parts, are provided with the first P type trap zone 4 and N-type well region in the N-type epitaxy layer 3 of side, described isolation area 13
6, described first P type trap zone 4 is provided with the first separate N-type heavily doped region 21 and the first p-type heavily doped region 31,
Being provided with the second p-type heavily doped region 32 in described N-type well region 6, the upper surface of described N-type epitaxy layer 3 arranges field oxide 8
With the first thin oxide layer 10, described first thin oxide layer 10 is connected with upper surface and the field oxide 8 of the first P type trap zone 4,
Described field oxide 8 is connected with the upper surface of N-type well region 6, and the upper surface of described first thin oxide layer 10 is provided with the first polycrystalline
Si-gate 9, is provided with isolation area 13 in described N-type epitaxy layer 3, arrange in the N-type epitaxy layer 3 of described isolation area 13 opposite side
There is the second separate N-type heavily doped region 22 and the 3rd N-type heavily doped region 23, at the second N-type heavily doped region 22 and the 3rd
The upper surface of the N-type epitaxy layer 3 between N-type heavily doped region 23 is provided with the second thin oxide layer 12, described second thin oxide layer
12 upper surfaces are provided with the second polysilicon gate 11, and described second N-type heavily doped region 22 and the first p-type heavily doped region 31 are by leading
Line connects, and described first polysilicon gate 9 is connected, in N-type with the first N-type heavily doped region 21 and the 3rd N-type heavily doped region 23
Epitaxial layer 3 is additionally provided with the second P type trap zone 5, and described second N-type heavily doped region 22 and the 3rd N-type heavily doped region 23 are positioned at
In second P type trap zone 5.
Operation principle:
As shown in Figure 4, for the equivalent circuit diagram of this example, parasitic PNP triode Q1(is comprised by the second p-type heavily doped region
32, N-type epitaxy layer 3 and the first P type trap zone 4 form), a parasitic NPN audion Q2(is by the first N-type heavily doped region
21, the first P type trap zone 4 and N-type epitaxy layer 3 form), parasitic gate grounding NMOS pipe M1 (by N-type epitaxy layer 3,
First P type trap zone the 4, first N-type heavily doped region the 21, first thin oxide layer the 10, first polysilicon gate 9 forms), parasitic electricity
Resistance RB, Applied gate ground connection nmos pass transistor M2(by second P type trap zone the 5, second N-type heavily doped region the 22, the 3rd N
Type heavily doped region the 23, second polysilicon gate 11 and the second thin oxide layer 12 form).
Under chip does not has electrifying condition, M2 raceway groove is off state, if now the anode pin in Fig. 3 structure occurs one
Positive ESD voltage, N epitaxial layer 3/ first P type trap zone 4 is binded up one's hair raw reverse-biased, avalanche breakdown is occurred, owing to M2 is off state,
Electric current will not flow through from the first p-type heavily doped region 31, but flows into negative electrode, parasitic NPN from the first N-type heavily doped region 21
Audion Q2 opens, and forms positive feedback with parasitic PNP triode Q1, causes the SCR of parasitism to open, therefore has the strongest
The ability of leakage current, and now anode and negative electrode do not have additional power source, do not worry latch-up.Power at chip
In the case of, when i.e. the grid (the second polysilicon gate 11) of anode, negative electrode and NMOS all has applied voltage, due to NMOS's
Forward low pressure source that grid is additional so that M2 raceway groove is in the conduction state, if now there is noise pulse in anode pin, outside N
Prolong/the first P type trap zone 4 binds up one's hair raw reverse-biased, and avalanche breakdown occurs, it is heavily doped that the hole of generation is entered the first p-type by the first p-well region
Miscellaneous district 31, flows to negative electrode by M2.Owing to the doping content of the first P type trap zone 4 is relatively big, it is added in dead resistance RBOn electricity
Press the least.Fig. 5 gives the TLP test curve of LIGBT, and its inefficacy electric current is 1mA/um, and NMOS opens shape at raceway groove
Under state, maximum conducting electric current can arrive 1mA/um, and the least due to the NMOS area relative to LIGBT again, we can increase
The width of big NMOS so that it is operated in variable resistance district when leakage current, and ensures to reach the mistake of LIGBT at conducting electric current
Before effect electric current, the drain-source voltage of NMOS is less than 0.5V.Therefore so that add A point in the diagram (to be i.e. added in the first N-type weight
Voltage in 21 times the first p-well of doped region) voltage is less than 0.7V, say, that the emitter junction of parasitic NPN audion Q2
Applied voltage can not be opened less than 0.5V, Q2, and therefore this structure will not occur snapback phenomenon.Have higher than breakdown potential
The maintenance voltage of pressure, therefore has the strongest latch-up immunity.
It addition, we can also be by improving the grid voltage conducting resistance with reduction NMOS of NMOS, when reducing NMOS conducting
Drain-source voltage, it is also possible to increase the doping content of p-well region of LIGBT, reduce dead resistance R in the p-well region district of LIGBTB,
Making A point voltage in Fig. 4 be strict controlled in below 0.7V, it is ensured that under electrifying condition, parasitic NPN audion Q2 will not open,
To avoid latch-up
Fig. 5 is the TLP test figure of the LIGBT in the specific embodiment of the invention one.First P type trap zone 4 of this LIGBT
Doping content is higher, and the result carrying out TLP test shows, the I-V curve of this structure does not occur snapback phenomenon,
Under conditions of device widths is 600um, inefficacy electric current It2 is 0.6A, is 1mA/um.
Embodiment 2:
As shown in Figure 6, this example is on the architecture basics of embodiment 1, heavily doped at the first N-type heavily doped region 21 and the first p-type
Add a P-sink doped region 7 under miscellaneous district 31, and P-sink doped region is wrapped in the first N-type heavily doped region 21 He
First p-type heavily doped region 31, the degree of depth of depth ratio first P type trap zone 4 of P-sink doped region 7 is big, and in this structure
The doping content of the first P type trap zone is the most relatively low with the first P type trap zone of structure shown in Fig. 3, improves the pressure of LIGBT,
And the doping content of the P-sink doped region 7 of this structure is higher.
This example is identical with the operation principle of embodiment 1, and difference is that the concentration of P-sink doped region is bigger relative to p-well region,
Therefore dead resistance R it is added inBVoltage less, it is easier to ensureing under electrifying condition, parasitic NPN audion Q2 will not open,
Therefore there is more preferable latch-up immunity.
Embodiment 3:
As it is shown in fig. 7, on the basis of this example embodiment 1, delete the second P type trap zone 5, by the second N-type heavily doped region 22 He
3rd N-type heavily doped region 23 changes the 3rd p-type heavily doped region 33 and the 4th p-type heavily doped region 34 into.Multi-crystal silicon area 11 is passed through
Wire is connected to negative sense low pressure source.
This example is identical with the operation principle of embodiment 1.Difference is to use the structure that LIGBT with PMOS connects, and needs
The unlatching of parasitic SCR of LIGBT is controlled in the additional reverse low pressure of the grid of PMOS with this.
Embodiment 4:
As shown in Figure 8, this example is on the basis of embodiment 3, at the first N-type heavily doped region 21 and the first p-type heavily doped region
Add a P-sink doped region 7 under 31, and P-sink doped region is wrapped in the first N-type heavily doped region 21 and a P
Type heavily doped region 31, the degree of depth of depth ratio first P type trap zone 4 of P-sink doped region 7 is big, and the P in this structure
The doping content of type well region is relatively the most relatively low with the first P type trap zone of structure shown in Fig. 3, improves the pressure of LIGBT, and this knot
The doping content of the P-sink doped region 7 of structure is higher.Multi-crystal silicon area 11 is wired to negative sense low pressure source.
This example is identical with the operation principle of embodiment 1.Difference is to use the structure that LIGBT with PMOS connects, and needs
The unlatching of parasitic SCR of LIGBT is controlled in the additional reverse low pressure of the grid of PMOS with this.
Claims (2)
1. there is a strong anti-breech lock controlled LIGBT device for ESD defencive function, including P type substrate (1), be positioned at p-type lining
The insulating barrier (2) of the end (1) upper surface and be positioned at the N-type epitaxy layer (3) of insulating barrier (2) upper surface, described N-type epitaxy layer
(3) it is provided with isolation area (13) in and N-type epitaxy layer (3) is isolated into two parts, described isolation area (13) side
N-type epitaxy layer (3) is provided with the first P type trap zone (4) and N-type well region (6), described first P type trap zone (4) sets
It is equipped with the first separate N-type heavily doped region (21) and the first p-type heavily doped region (31), in described N-type well region (6)
Being provided with the second p-type heavily doped region (32), the upper surface of described N-type epitaxy layer (3) arranges field oxide (8) and first thin
Oxide layer (10), described first thin oxide layer (10) respectively with upper surface and the field oxide (8) of the first P type trap zone (4)
Connecting, described field oxide (8) is connected with the upper surface of N-type well region (6), the upper end of described first thin oxide layer (10)
Face is provided with the first polysilicon gate (9), it is characterised in that set in the N-type epitaxy layer (3) of described isolation area (13) opposite side
It is equipped with the second separate N-type heavily doped region (22) and the 3rd N-type heavily doped region (23), at the second N-type heavily doped region (22)
With the upper surface of the N-type epitaxy layer (3) that the 3rd between N-type heavily doped region (23) is provided with the second thin oxide layer (12), institute
State the second thin oxide layer (12) upper surface and be provided with the second polysilicon gate (11), described second N-type heavily doped region (22) and
One p-type heavily doped region (31) is connected by wire, described first polysilicon gate (9) and the first N-type heavily doped region (21) and
3rd N-type heavily doped region (23) connects；Described N-type epitaxy layer (3) is additionally provided with the second P type trap zone (5), and described second
N-type heavily doped region (22) and the 3rd N-type heavily doped region (23) are positioned in the second P type trap zone (5).
A kind of strong anti-breech lock controlled LIGBT device with ESD defencive function the most according to claim 1, its feature exists
Be additionally provided with the 3rd p-type heavily doped region (7) in, described N-type epitaxy layer (3), described first N-type heavily doped region (21) and
First p-type heavily doped region (31) is positioned in the 3rd p-type heavily doped region (7), mixing of described 3rd p-type heavily doped region (7)
The miscellaneous degree of depth is more than the first P type trap zone (4).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11899057B2 (en) | 2021-07-08 | 2024-02-13 | Changxin Memory Technologies, Inc. | Method for identifying latch-up structure |
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| CN103972233B (en) * | 2014-05-30 | 2016-11-02 | 电子科技大学 | A kind of turned off SCR device with latch-up immunity |
| CN104078498B (en) * | 2014-07-14 | 2016-08-31 | 东南大学 | A kind of trench isolations landscape insulation bar double-pole-type transistor |
| CN105845738B (en) * | 2015-01-15 | 2018-09-14 | 北大方正集团有限公司 | High-tension resistive |
| CN104701362B (en) * | 2015-03-23 | 2018-01-02 | 东南大学 | A kind of trench isolations landscape insulation bar double-pole-type transistor |
| CN110034176B (en) * | 2019-04-22 | 2022-02-11 | 东南大学 | Reverse conducting type transverse insulated gate bipolar transistor for solving reverse recovery failure |
| CN111668209B (en) * | 2020-06-10 | 2022-03-15 | 电子科技大学 | Low-leakage silicon controlled rectifier for low-voltage ESD protection |
| CN112687681B (en) * | 2020-12-29 | 2023-05-02 | 电子科技大学 | LIGBT device with integrated NMOS (N-channel metal oxide semiconductor) tube |
| CN113053874B (en) * | 2021-03-16 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Radiation-resistant high-voltage ESD semiconductor device |
| CN117556761A (en) * | 2022-08-03 | 2024-02-13 | 无锡华润上华科技有限公司 | Anode short-circuit transverse insulated gate bipolar transistor model and modeling method thereof |
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| CN2914330Y (en) * | 2006-05-24 | 2007-06-20 | 杭州电子科技大学 | Anti-ESD integrated SOI LIGBT unit |
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| JP5261927B2 (en) * | 2006-12-11 | 2013-08-14 | パナソニック株式会社 | Semiconductor device |
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| CN2914330Y (en) * | 2006-05-24 | 2007-06-20 | 杭州电子科技大学 | Anti-ESD integrated SOI LIGBT unit |
| CN101969074A (en) * | 2010-10-28 | 2011-02-09 | 电子科技大学 | High voltage lateral double diffused MOSFET element |
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