CN102244105B - Thyristor with high hold voltage and low triggering voltage ESD (electronstatic discharge) characteristic - Google Patents

Abstract

The present invention relates to the technical field of protection circuits for semiconductor integrated chips, and in particular to a thyristor with high sustain voltage and low trigger voltage ESD characteristics. , the well region layer includes an N well region and a P well region, the N well region is adjacent to the P well region, and both the N well region and the P well region are in contact with the substrate layer (311), the The well layer includes an N well region (309) and a P well region (310), and a first N+ doped region (305) is provided at the junction of the P well region (310) and the N well region (309), so The N well region (309) is provided with a first P+ doping region (304), and the P well region (310) is provided with a second N+ doping region (306) and a second P+ doping region (307). The invention improves the structure of the original thyristor, reduces the trigger voltage of the thyristor, and increases the maintenance voltage of the thyristor, so that the thyristor can be ideally used as an ESD clamp protection device.

Description

Thyristors with high sustain voltage and low trigger voltage ESD characteristics

technical field

The invention relates to the technical field of protection circuits for semiconductor integrated chips, in particular to a thyristor with high sustain voltage and low trigger voltage ESD characteristics.

Background technique

In the manufacturing process of integrated circuit IC chips and the final system application, there will be different degrees of electrostatic discharge (Electrostatic Discharge, ESD) events. Electrostatic discharge is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating. The whole process takes about 100ns to 200ns. In addition, when the integrated circuit is discharged, an equivalent high voltage of hundreds or even thousands of volts will be generated, which will break down the gate oxide layer of the input stage in the integrated circuit. As the size of MOS transistors in integrated circuits becomes smaller and smaller, the thickness of the gate oxide layer becomes thinner and thinner, only 2.6nm in the 0.13um process. Under this trend, it is very necessary to use high-performance electrostatic protection devices to discharge electrostatic charges to protect internal functional devices from damage.

The ESD clamp protection circuit is located between the power supply VDD and the ground level VSS, and has the following two main functions: first, it can effectively provide full-chip ESD protection and realize ESD current discharge between any two pins; second Second, the threat of voltage and current fluctuations on the power/ground bus to the internal circuit can be eliminated in time.

The working principle of the ESD clamp protection circuit is as follows: When an ESD pulse or voltage fluctuation occurs on VDD/VSS, the clamp protection circuit is triggered and turned on in time, a low-impedance path appears between VDD and VSS, and the ESD current is discharged to the ground Level; when the circuit is working normally, the levels on VDD and VSS are in the normal range, the clamp protection circuit is off, and the leakage current should be small enough to not affect the performance of the internal circuit.

Semiconductor devices commonly used as ESD clamp protection circuits include: NMOS structure, thyristor structure (SCR tube) and cascaded diode string structure (Cascade Diode String, CDS). Among these three types of clamping protection circuits: First, NMOS tubes are compatible with CMOS technology and are easy to implement, but the ESD resistance per unit area is very low. When used as a clamping protection circuit, the area is usually large. For large-area, multi-pin The circuit is not applicable; secondly, the SCR tube circuit has a strong ability to resist ESD per unit area, and the area is the smallest when used as a clamp circuit. The most important point is that the leakage current of the SCR structure circuit is very small, but its trigger voltage is not adjustable, and Latch-up phenomenon is prone to occur; finally, CDS tubes are widely used because of their simple structure and adjustable trigger voltage, but the CDS tubes in CMOS process will have Darlington effect, which will reduce the trigger voltage and increase the leakage current. large, the on-resistance increases.

In the design of ESD clamp protection devices, the constraints of the ESD design window must be met. As shown in Figure 1, the design window refers to the highest turn-on voltage (Vt1) and the lowest sustain voltage (Vhold) that the device reaches when it is turned on. Among them, Vt2 is the secondary breakdown voltage. The turn-on voltage Vt1 of the ESD device cannot be greater than the breakdown voltage of the polysilicon gate of the I/O device. At the same time, there must be a certain safety interval between the breakdown voltage and the breakdown voltage, generally about 10%. At the same time, in order to prevent the latch-up effect of the internal CMOS device, the minimum voltage after the clamp protection device is turned on, that is, the maintenance voltage, cannot be lower than the voltage of the power supply VDD, and at the same time it cannot be too high, so as to reduce the heat generated by the large current. damage to the device itself. As the process feature size decreases, the width of this design window will become smaller and smaller. Thyristor SCR devices have strong ESD unit protection ability and small leakage current, making them ideal for use as clamp protection devices. However, due to its high turn-on voltage and low maintenance voltage (the turn-on voltage of common silicon controlled rectifier devices is above 20V, and the maintenance voltage is within 3V), it does not meet the ESD design window and is prone to latch-up, so the turn-on voltage is greatly reduced. It is the main difficulty of its design to increase the maintenance voltage in an appropriate amount.

As shown in Figure 2, the existing SCR tube includes: a substrate layer, the substrate layer is a P-type substrate, an N well region is arranged in the substrate layer, and a first N+ doped region is arranged in the N well region and the first P+ doped region, in the substrate layer, and not in the N well region, a second N+ doped region and a second P+ doped region are provided, and the first N+ doped region and the first P+ doped region The impurity region is connected, and the connection point is used as an anode, and the second N+ doped region is connected to the second P+ doped region, and the connection point is used as a cathode, the SCR tube shown in Figure 2 can be equivalent to three PN junctions in series A device with a four-layer PNPN structure can be regarded as a combination of a PNP transistor and an NPN transistor. Fig. 3 is the equivalent circuit diagram of the SCR tube shown in Fig. 2, wherein the terminal A1 is the anode, the terminal B1 is the cathode, and R _nw1 is the resistance of the N well region; Fig. 4 is the working principle diagram of the SCR tube shown in Fig. 2, wherein , U _AC represents the voltage difference from the anode to the cathode, and I _AC represents the current of the anode. When a large voltage is applied to the A1 terminal, the reverse PN junction on the breakdown NPN transistor M _N1 produces an avalanche effect, and the generated current makes the substrate resistance A voltage drop is generated on R _sub1 , thereby improving the current amplification capability of NPN transistor M _N1 and PNP transistor M _P1 , thereby increasing the emitter current I _E of the NPN transistor, and I _E replaces the reverse bias current of the PN junction on M _N1 to maintain The avalanche multiplication process, so that the SCR tube has a negative resistance process in which the applied voltage decreases and the current increases, that is, the Snapback characteristic. When the voltage drops to the minimum maintenance voltage V _h required to maintain avalanche multiplication, it stops decreasing, and a low-resistance process occurs in which the voltage remains basically unchanged and the current rises rapidly until the BJT tube is burned due to thermal breakdown due to excessive current.

When the SCR tube is used as an ESD clamp protection device, the anode can be connected to the chip input and output terminal I/O or the chip power supply VDD, and the cathode can be connected to VSS. The biggest problem with the SCR structure is that the trigger voltage V _t1 is too high, and the V _t1 can be as high as 40V in a 1μm standard CMOS process. Such a high trigger voltage V _t1 is obviously not suitable for sub-micron and deep sub-micron CMOS processes with thinner and thinner gate oxides, because too high a trigger voltage will cause the gate oxidation of the internal circuit when the ESD protection circuit of the SCR tube is not turned on. layer is broken.

In order to solve this problem, in 1991, A. Chatterjee proposed a low-voltage trigger SCR structure (Low-Voltage Triggering SCR, LVTSCR for short), as shown in Figure 5. LVTSCR has become a commonly used SCR tube design structure.

Compared with the SCR tube, the improvement of the LVTSCR tube is: on the one hand, a saddle-type N+ doped region is added at the boundary between the N well and the P substrate to reduce the breakdown voltage of the N well/P substrate junction; , GGNMOS tube M _G2 is added to assist SCR tube triggering.

First, the trigger voltage Vt1 of the SCR tube is related to the breakdown voltage of the N well/P substrate junction. The addition of the saddle-type N+ doped region makes the reverse PN junction that needs to break down change from P substrate/N well to P substrate/N+ doped region, according to the relationship between the breakdown voltage and doping concentration of the reverse PN junction , The breakdown voltage of the reverse PN junction formed by the N+ doped region/P substrate is lower than that of the reverse PN junction formed by the N well/P substrate.

Secondly, a GGNMOS tube auxiliary trigger is added. Figure 6 is the equivalent circuit diagram of the LVTSCR tube shown in Figure 5, where the A2 terminal is the anode, the B2 terminal is the cathode, and R _nw2 is the resistance of the _N well region. The breakdown generates a substrate current I _sub2 , and the current flows through the substrate resistor R _sub2 to generate a voltage drop, making the BE junction of the NPN transistor M _N2 forward-biased, and the NPN transistor M _N2 is turned on. The emitter current of the NPN transistor M _N2 flows through the N-well resistor R _nw2 to generate a voltage drop, so that the BE junction of the PNP transistor _MP2 is forward-biased, and the PNP transistor _MP2 is turned on. Thus the entire LVTSCR tube forms a low-resistance path to discharge the ESD current.

Through the above improvements, the trigger voltage of the LVTSCR tube can be successfully reduced to below 10V, but for devices with deep submicron technology, the trigger voltage of LVTSCR is still higher than the breakdown voltage of the gate oxide layer (gate oxide in 0.13um process The breakdown voltage of the layer is about 5V, and the experimental data shows that its trigger voltage is about 7V).

At the same time, since the LVTSCR tube is a latch-type structure of two BJT tubes (namely M _N2 and _MP2 ), the current amplification capability is very strong, which is the product of the amplification factors of the two BJT tubes. The current discharge capability after turning on is very strong, so the holding voltage (Holding Voltage) that maintains the current generated by avalanche breakdown after triggering is also very small (the experimental data under the 0.13um process shows that the holding voltage is about 3V, which is lower than the power supply voltage 3.3V ). In this way, its sustain voltage does not meet the design requirements of the ESD clamp protection device.

Contents of the invention

(1) Technical problems to be solved

The technical problem to be solved by the invention is: how to reduce the trigger voltage of the thyristor and increase the maintenance voltage of the thyristor while maintaining the characteristics of strong ESD resistance per unit area and small leakage current of the SCR device.

(2) Technical solutions

In order to solve the above technical problems, the present invention provides a thyristor with high sustain voltage and low trigger voltage ESD characteristics. The thyristor includes from bottom to top: a substrate layer, a well layer and a gate oxide layer, and the well layer includes An N well region and a P well region, the N well region is adjacent to the P well region, both the N well region and the P well region are in contact with the substrate layer, and the well region layer includes an N well region and an N well region. In the P well region, a first N+ doped region is provided at the junction of the P well region and the N well region, the N well region is provided with a first P+ doped region, and the P well region is provided with a second N+ doped region. region and a second P+ doped region, an insulating material region is provided between the first P+ doped region and the first N+ doped region, and between the second P+ doped region and the second N+ doped region An insulating material region is also provided; the gate oxide layer is arranged on the upper surface of the well region layer, and is located between the second N+ doped region and the first N+ doped region, and the first N+ doped region The gate oxide layer, the second N+ doped region and the second P+ doped region are connected to each other, and the connection point is used as a cathode.

Preferably, a buried oxide layer is further provided between the substrate layer and the well region layer.

The invention also discloses a thyristor with high maintenance voltage and low trigger voltage ESD characteristics. The thyristor includes from bottom to top: a substrate layer, a well layer and a gate oxide layer, and the well layer includes an N well region and a P well region. a well region, the N well region is adjacent to the P well region, both the N well region and the P well region are in contact with the substrate layer, and the well region layer includes an N well region and two P well regions, The junction of the N well region and the first P well region is provided with a first N+ doped region, the second P well region is provided with a first P+ doped region, and the first P well region is provided with a second N+ doped region. The impurity region and the second P+ doped region, an insulating material region is provided between the first P+ doped region and the first N+ doped region, and the second P+ doped region and the second N+ doped region There is also an insulating material region between them; the gate oxide layer is arranged on the upper surface of the well region layer, and is located between the second N+ doped region and the first N+ doped region, and the first N+ doped region The region is connected to the first P+ doped region, and the connection point is used as an anode, and the gate oxide layer, the second N+ doped region and the second P+ doped region are connected to each other, and the connection point is used as a cathode.

Preferably, a buried oxide layer is further provided between the substrate layer and the well region layer.

(3) Beneficial effects

The invention improves the original thyristor structure, reduces the trigger voltage of the thyristor, and increases the maintenance voltage of the thyristor, so that the thyristor can be ideally used as an ESD clamp protection device, and can also be used as an ESD protection device for the input or output of the chip. clamp protection device.

Description of drawings

Fig. 1 is the schematic diagram of ESD design window;

Fig. 2 is a specific structural schematic diagram of an existing SCR tube;

Fig. 3 is an equivalent schematic diagram of the SCR tube shown in Fig. 2;

Fig. 4 is a working principle diagram of the SCR tube shown in Fig. 2;

Fig. 5 is the concrete structure schematic diagram of existing LVTSCR tube;

Fig. 6 is an equivalent schematic diagram of the LVTSCR tube shown in Fig. 5;

FIG. 7 is a schematic structural view of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to the first embodiment of the present invention;

Fig. 8 is a specific structural diagram of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to the second embodiment of the present invention;

FIG. 9 is a schematic structural view of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to a third embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to a fourth embodiment of the present invention;

FIG. 11 is a schematic diagram of the specific structure of the thyristor shown in FIG. 7 using SOI technology;

Fig. 12 is an equivalent circuit diagram of the thyristor shown in Figs. 7 to 10;

FIG. 13 is a performance comparison diagram of the existing LVTSCR transistor shown in FIG. 5 and the thyristor shown in FIG. 7 .

Detailed ways

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

Example 1

Fig. 7 is a specific structural schematic diagram of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to the first embodiment of the present invention, the thyristor includes: a substrate layer 311, a well region layer and a gate oxide layer in order from bottom to top, so The well region layer includes an N well region and a P well region, the N well region is adjacent to the P well region, and both the N well region and the P well region are in contact with the substrate layer, and the well region layer includes a N well region 309 and a P well region 310, the junction of the P well region 310 and the N well region 309 is provided with a first N+ doped region 305, and the N well region 309 is provided with a first P+ doped region 304, The P well region 310 is provided with a second N+ doped region 306 and a second P+ doped region 307, and the gate oxide layer is arranged on the upper surface of the well layer and is located in the second N+ doped region 306 Between the first N+ doped region 305, the first N+ doped region 305 is connected to the first P+ doped region 304, and the connection point is used as the anode 301, the gate oxide layer, the second N+ doped region 306 and the second P+ doped region 307 are connected to each other, and the connection point serves as the cathode 303 .

Example 2

Fig. 8 is a specific structural diagram of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to the second embodiment of the present invention. On the basis of Embodiment 1, the preferred technical solution of the present invention is that the first P+ An insulating material region 313 is provided between the doped region 304 and the first N+ doped region 305 , and an insulating material region 313 is also provided between the second P+ doped region 307 and the second N+ doped region 306 .

Example 3

Fig. 9 is a schematic structural diagram of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to a third embodiment of the present invention, the thyristor includes: a substrate layer, a well region layer and a gate oxide layer in order from bottom to top, and the The well region layer includes an N well region and a P well region, the N well region is adjacent to the P well region, and both the N well region and the P well region are in contact with the substrate layer, and the well region layer includes a N well region. Well region 309 and two P well regions, the junction of the N well region 309 and the first P well region 310 is provided with a first N+ doped region 305, and the second P well region 308 is provided with a first P+ doped region 304, the first P well region 310 is provided with a second N+ doped region 306 and a second P+ doped region 307, the gate oxide layer is arranged on the upper surface of the well region layer, and is located on the second N+ Between the doped region 306 and the first N+ doped region 305, the first N+ doped region 305 is connected to the first P+ doped region 304, and the connection point is used as the anode 301, the gate oxide layer, the second N+ The doped region 306 and the second P+ doped region 307 are connected to each other, and the connection point serves as the cathode 303 .

Example 4

Fig. 10 is a specific structural diagram of a thyristor with high sustain voltage and low trigger voltage ESD characteristics according to the fourth embodiment of the present invention. On the basis of Embodiment 3, the preferred technical solution of the present invention is that the first P+ An insulating material region 313 is provided between the doped region 304 and the first N+ doped region 305 , and an insulating material region 313 is also provided between the second P+ doped region 307 and the second N+ doped region 306 .

The thyristor can apply SOI (Silicon-On-Insulator, silicon on insulating substrate) technology, and a buried oxide layer is added on the basis of the thyristors in Examples 1 to 4, and the thyristor in Example 4 is taken as an example below to illustrate In this structure, as shown in FIG. 11 , a buried oxide layer 312 is also provided between the substrate layer and the well region layer.

Since the equivalent principle diagrams of the thyristors in Examples 1 to 4 are the same, they can all be equivalent to Figure 12, and the working principle of the thyristor of the present invention will be described below with reference to Figure 12: when the ESD impact reaches the anode (that is, the A3 terminal), first the GGNMOS transistor The reverse PN junction formed by the first N+ doped region and the P-type substrate first breaks down, generating a substrate current I _sub3 , which flows through the substrate resistor R _sub3 to generate a voltage drop, making the parasitic NPN transistor M _N3 The BE junction is forward biased, and the NPN transistor M _N3 is turned on. The emitter current of the NPN transistor M _N3 flows through the N-well resistor R _nw3 to generate a voltage drop, so that the BE junction of the parasitic PNP transistor _MP3 is forward-biased, and the PNP transistor _MP3 is turned on. Thus, the entire SCR structure is turned on, and the ESD current is discharged. At the same time, the voltage drop flowing through the resistors R _sub3 and R _nw3 further increases after being turned on, thereby improving the current amplification capabilities of the NPN transistor M _N3 and the PNP transistor _MP3 , and further increasing the emitter current I _E3 of the NPN transistor M _N3 , I _E3 replaces the reverse bias current of the reverse PN junction to maintain the avalanche multiplication process, so that the SCR has a negative resistance process in which the applied voltage decreases and the current increases, that is, the hysteresis characteristic. When the voltage drops to the minimum maintenance voltage V _h required to maintain avalanche multiplication, it stops decreasing, and the voltage remains basically unchanged, and the current rises rapidly in a low-resistance process until the current is too large and the thyristor is burned due to thermal breakdown.

The realization of the low trigger voltage of the thyristor in Examples 1-4 is due to the N+ doped region/P substrate junction breakdown of the saddle-shaped N+ region (that is, the first N+ doped region 305 ) replacing the traditional SCR transistor when it is turned on. The N well region/P-type substrate junction breaks down, and the junction breakdown voltage of the former is low. At the same time, adding GGNMOS can trigger SCR to open in advance. And because the saddle-shaped N+ region of the thyristor of the present invention is directly connected to the A3 terminal (anode) electrode, and the A2 terminal electrode in the LVTSCR is connected to the N+ region in the N-well region, the current needs to pass through the N-well region first and then reach the saddle-type N+ area, so its turn-on voltage will be smaller than that of LVTSCR.

At the same time, since the P+ region connected to the A3 end of the thyristor of the present invention (i.e. the first P+ doped region 304) is at the far end, compared with SCR and LVTSCR, it is equivalent to an increase in the base width of the parasitic PNP transistor, reducing the PNP The current amplification capability of the tube _MP3 increases the minimum voltage required to maintain the multiplication of the avalanche, that is, the maintenance voltage increases.

The transmission line pulse (transmission line pulse, TLP) test data is shown in Figure 13. It can be seen from the comparison that the trigger voltage of the traditional LVTSCR device is relatively large, about 7V. However, the trigger voltage of the thyristor of the present invention can be lower than 5V (the breakdown voltage of the gate oxide layer is about 5V). At the same time, its maintenance voltage is higher than the power supply voltage of the integrated circuit (the power supply voltage is 3.3V under the feature size of 0.13 micron process). Therefore, the thyristor of the present invention meets the requirements of ESD clamping circuit protection for deep submicron devices. At the same time, in the case of the same width, the secondary breakdown current It2 is basically the same. It is proved that the thyristor of the present invention, like LVTSCR, has higher ESD protection ability.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (4)

1. thyristor with high maintenance voltage low trigger voltage ESD characteristic, it is characterized in that, described thyristor comprises from bottom to up successively: substrate layer (311), well region layer and grid oxide layer, described well region layer comprises N well region and P well region, described N well region is in abutting connection with described P well region, described N well region and P well region all contact with described substrate layer, described well region layer comprises a N well region (309) and a P well region (310), described P well region (310) and N well region (309) intersection are provided with a N+ doped region (305), described N well region (309) is provided with a P+ doped region (304), described P well region (310) is provided with the 2nd N+ doped region (306) and the 2nd P+ doped region (307), be provided with insulating material district (313) between a described P+ doped region (304) and the N+ doped region (305), and also be provided with insulating material district (313) between described the 2nd P+ doped region (307) and the 2nd N+ doped region (306); Described grid oxide layer is located at described well region layer upper surface, and be positioned between described the 2nd N+ doped region (306) and the N+ doped region (305), a described N+ doped region (305) is connected with a P+ doped region (304), and tie point is as anode (301), described grid oxide layer, the 2nd N+ doped region (306) and the 2nd P+ doped region (307) are connected to each other, and tie point is as negative electrode (303).

2. thyristor as claimed in claim 1 is characterized in that, also is provided with oxygen buried layer (312) between described substrate layer and the well region layer.

3. thyristor with high maintenance voltage low trigger voltage ESD characteristic, it is characterized in that, described thyristor comprises from bottom to up successively: substrate layer, well region layer and grid oxide layer, described well region layer comprises N well region and P well region, described N well region is in abutting connection with described P well region, described N well region and P well region all contact with described substrate layer, described well region layer comprises a N well region (309) and two P well regions, the intersection of described N well region (309) and a P well region (310) is provided with a N+ doped region (305), the 2nd P well region (308) is provided with a P+ doped region (304), a described P well region (310) is provided with the 2nd N+ doped region (306) and the 2nd P+ doped region (307), be provided with insulating material district (313) between a described P+ doped region (304) and the N+ doped region (305), and also be provided with insulating material district (313) between described the 2nd P+ doped region (307) and the 2nd N+ doped region (306); Described grid oxide layer is located at described well region layer upper surface, and be positioned between described the 2nd N+ doped region (306) and the N+ doped region (305), a described N+ doped region (305) is connected with a P+ doped region (304), and tie point is as anode (301), described grid oxide layer, the 2nd N+ doped region (306) and the 2nd P+ doped region (307) are connected to each other, and tie point is as negative electrode (303).

4. thyristor as claimed in claim 3 is characterized in that, also is provided with oxygen buried layer (312) between described substrate layer and the well region layer.

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