CN113871383B - Improved LVTSCR device for reducing trigger voltage by reverse diode - Google Patents
Improved LVTSCR device for reducing trigger voltage by reverse diode Download PDFInfo
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- CN113871383B CN113871383B CN202111119364.8A CN202111119364A CN113871383B CN 113871383 B CN113871383 B CN 113871383B CN 202111119364 A CN202111119364 A CN 202111119364A CN 113871383 B CN113871383 B CN 113871383B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides an improved LVTSCR device with a reverse diode for reducing trigger voltage. On the basis of a traditional LVTSCR device, an oxide layer region is arranged on the silicon surface between a P-type heavily doped region connected with an anode and an n-type heavily doped region connected with a silicon substrate and an n-type well region in a bridging mode; forming a polysilicon layer on the surface of the oxide layer region; the polysilicon layer is connected to the polysilicon layer over another oxide layer region on the silicon surface between the bridged n-type heavily doped region and the n-type heavily doped region connected to the cathode by a reverse diode. Compared with the traditional LVTSCR structure, the structure further reduces the trigger voltage by adding two new current paths, reduces the peak voltage of the second peak of the HBM voltage waveform, and improves the robustness of the device.
Description
Technical Field
The invention belongs to the field of electrostatic discharge (Electrostatic Discharge, ESD for short) protection of integrated circuits, and particularly relates to an ESD protection structure device, in particular to an improved LVTSCR (Low Voltage Trigger SCR) device.
Background
Since the advent of the first bipolar transistor invention and the first IC chip, ESD poses an increasing threat to the reliability of the IC chip. During the manufacturing, testing, packaging, transportation, and use of the IC chip, the IC chip may be damaged by ESD, and thus, research into ESD protection schemes of the IC chip is necessary.
In certain semiconductor processes, ESD protection devices are required to operate within certain design windows in addition to achieving a strong current drain capability. However, as the minimum linewidth of the chip decreases, the ESD design window narrows. In this trend, it is important to discharge electrostatic charges with low trigger voltage ESD devices to protect circuits.
In integrated circuits, SCR is one of the most efficient ESD protection devices. The SCR has low maintaining voltage and small on-resistance, so that the SCR can bear high ESD current, and has high ESD robustness. The SCR device has the strongest ESD protection capability per unit area compared to other ESD protection devices. However, the high trigger voltage problem common to SCR devices results in its inability to be directly applied to IC chips. To reduce the trigger voltage of the SCR device, a Low Voltage Triggered SCR (LVTSCR) is generated.
Fig. 1 is a device structure of a conventional LVTSCR. The structure comprises:
a p-type silicon substrate 110;
forming an n-type heavily doped region 131, a p-type heavily doped region 132 and an n-type well region 120 on the p-type silicon substrate 110;
an n-type heavily doped region 121 and a p-type heavily doped region 122 are arranged in the n-type well region 120;
an n-type heavily doped region 141 bridging the two regions is arranged near the junction surface of the p-type silicon substrate 110 and the n-type well region 120;
an oxide layer region 161 is formed on the surface between the n-type heavily doped region 141 and the n-type heavily doped region 131;
shallow trench isolation is provided between the n-type heavily doped region 121 and the p-type heavily doped region 122, between the p-type heavily doped region 122 and the n-type heavily doped region 141, and between the n-type heavily doped region 131 and the p-type heavily doped region 132, as shown by the hatched areas in fig. 1.
The LVTSCR is composed of a parasitic PNP transistor, a parasitic NPN transistor, and a parasitic NMOS structure, and the equivalent circuit diagram thereof is shown in fig. 1. The p-type heavily doped region 122, the n-type well region 120, the p-type substrate 110 and the p-type heavily doped region 132 constitute a PNP transistor Q p1 The method comprises the steps of carrying out a first treatment on the surface of the The n-type heavily doped region 121, the n-type well region 120, the p-type substrate 110 and the n-type heavily doped region 131 form an NPN transistor Q n1 The method comprises the steps of carrying out a first treatment on the surface of the The n-type heavily doped region 141, the oxide layer region 161 and the n-type heavily doped region 131 form an NMOS structure M n1 ；R NW1 Is the parasitic resistance in the n-type well region 120; r is R PW1 Is the parasitic resistance of the p-type well region 130.
The n-type heavily doped region 121 and the p-type heavily doped region 122 are connected with the anode; the polysilicon layer, the n-type heavily doped region 131 and the p-type heavily doped region 132 on the oxide region 161 are connected to a cathode.
When a positive pulse is applied to the anode of the LVTSCR device structure (cathode grounded), the p-n junction formed by the n-type heavily doped region 141 and the p-type silicon substrate 110 is first reverse biased. The p-n junction breakdown voltage is reduced because the polysilicon layer on oxide region 161 is connected to the cathode. When the voltage across the p-n junction is greater than its avalanche breakdown voltage, a large number of electron-hole pairs are generated near the p-n junction. The generated holes reach the cathode via the p-type silicon substrate 110 and the p-type heavily doped region 132. Parasitic resistance R of p-type silicon substrate 110 PW1 The partial voltage of (1) reaches the positive bias voltage of the p-n junction formed by the p-type silicon substrate 110 and the n-type heavily doped region 131, Q n1 And opening. As the current continues to increase, R NW1 The partial voltage of (a) reaches the positive bias voltage of the p-n junction formed by the n-type well region 120 and the p-type heavily doped region 122, Q p1 And opening. And then, the collector current of the PNP tube provides base current for the NPN tube, the collector current of the NPN tube provides base current for the PNP tube, positive feedback is formed between the parasitic PNP tube and the NPN tube, an SCR1 current channel is formed, and the device is triggered as shown by a dotted line in FIG. 1.
In the traditional LVTSCR structure, the trigger voltage is reduced by embedding a GGNMOS structure in the SCR structure. Trigger voltage of LVTSCR structure is composed of M n1 Is determined by the source-drain breakdown voltage of (a). However, with the increasing process requirements, the conventional LVTSCR has failed to meet the low voltage triggering requirements.
Accordingly, an improved LVTSCR device capable of reducing trigger voltages is presented herein. The structure is based on the existing LVTSCR structure, two current channels are added, and therefore trigger voltage is reduced.
Disclosure of Invention
It is an object of the present invention to provide an improved LVTSCR device capable of reducing the trigger voltage. The invention adopts the technical scheme that:
an improved LVTSCR device for reducing trigger voltage using a reverse diode includes a main bleeder device and an auxiliary device.
The main bleeder device comprises a first conductive type silicon substrate, wherein a first conductive type heavily doped region, a second conductive type heavily doped region and a second conductive type well region are formed on the first conductive type silicon substrate; forming a first conductive type heavily doped region and a second conductive type heavily doped region on the second conductive type well region; forming a second conductive type heavily doped region crossing both sides between the second conductive type well region and the first conductive type silicon substrate; forming a first oxide layer region on the silicon surface between the first conductive type heavily doped region of the second conductive type well region and the second conductive type heavily doped regions crossing both sides; forming a second oxide layer region on the silicon surface between the second conductive type heavily doped region formed on the first conductive type silicon substrate and the second conductive type heavily doped region crossing both sides;
the auxiliary device comprises a first conductive type silicon substrate, and a second conductive type well region is formed on the first conductive type silicon substrate; forming a first conductive type heavily doped region and a second conductive type heavily doped region on the second conductive type well region;
the second conductive type heavily doped region and the first conductive type heavily doped region of the second conductive type well region in the main bleeder device are connected with the anode; the first heavily doped region and the second heavily doped region on the first conductivity type silicon substrate are directly connected with the cathode; the first oxide layer region is covered with a polysilicon layer and is connected with a second conductive type heavily doped region formed on a second conductive type well region in the auxiliary device; the second oxide layer region is covered with a polysilicon layer and is connected with a first conductive type heavily doped region formed on a second conductive type well region in the auxiliary device;
the width of the auxiliary device is the same as or different from that of the main discharging device.
The present invention provides an improved LVTSCR device that reduces trigger voltage. The device consists of a main bleeder device and an auxiliary device, wherein the auxiliary device controls the opening of the parasitic NMOS tube. When an ESD event comes, an RC (Resistance-capacitance) current path formed by the auxiliary device enables the NMOS current channel to be conducted, and the trigger voltage of the device is reduced.
Description of the drawings:
FIG. 1 illustrates a conventional LVTSCR device construction and equivalent circuit;
fig. 2 example 1 a modified LVTSCR device structure and equivalent circuit with trigger voltage reduced by a reverse diode;
FIG. 3 simulation results of the modified LVTSCR device and the conventional LVTSCR device shown in example 1 under ESD human body model discharge (HBM) conditions
(a) A simulation circuit of the HBM model;
(b) The voltage of the modified LVTSCR device and LVTSCR during HBM ESD discharge varies with time.
Fig. 4 example 2 improved LVTSCR device structure and equivalent circuit with trigger voltage reduced by reverse diode;
fig. 5 example 1 a modified LVTSCR device structure with trigger voltage lowered by a reverse diode;
specific embodiments:
the invention will be described in detail below with reference to the drawings and the detailed description.
Example 1
An embodiment of the present invention is a modified LVTSCR device with a reverse diode to reduce the trigger voltage, the device structure and equivalent circuit being shown in fig. 2.
The structure comprises a p-type silicon substrate 110;
an n-type heavily doped region 131, a p-type heavily doped region 132, an n-type well region 120 and an n-type well region 130 are formed on the p-type silicon substrate 110;
an n-type heavily doped region 141 bridging the two regions is arranged near the junction surface of the p-type silicon substrate 110 and the n-type well region 120;
an n-type heavily doped region 121 and a p-type heavily doped region 122 are arranged in the n-type well region 120;
a p-type heavily doped region 151 and an n-type heavily doped region 152 are arranged in the n-type well region 130;
an oxide layer region 161 is formed on the surface between the n-type heavily doped region 141 and the n-type heavily doped region 131, and a polysilicon layer is formed on the surface of the oxide layer region 161;
an oxide layer region 162 is formed on the surface between the p-type heavily doped region 122 and the n-type heavily doped region 141, and a polysilicon layer is formed on the surface of the oxide layer region 162;
shallow trench isolation is provided between the n-type heavily doped region 121 and the p-type heavily doped region 122, between the n-type heavily doped region 131 and the p-type heavily doped region 132, between the p-type heavily doped region 132 and the p-type heavily doped region 151, and between the p-type heavily doped region 151 and the n-type heavily doped region 152, as shown by the hatched regions in fig. 2.
The improved LVTSCR device consists of a main bleeder device and an auxiliary device; the main bleeder device is formed by a parasitic PNP transistor Q p2 A parasitic NPN transistor Q n2 And a parasitic NMOS structure M n2 The composition is formed. Wherein the p-type heavily doped region 122, the n-type well region 120, the p-type substrate 110 and the p-type heavily doped region 132 constitute Q p2 The method comprises the steps of carrying out a first treatment on the surface of the n-type heavily doped region 121, n-type well region 120, p-type substrate 110, and n-type heavily doped region 131 form Q n2 The method comprises the steps of carrying out a first treatment on the surface of the The n-type heavily doped region 141, the oxide layer region 161 and the n-type heavily doped region 131 constitute M n2 The method comprises the steps of carrying out a first treatment on the surface of the The auxiliary device is constituted by a reverse diode device D1. Wherein the p-type heavily doped region 151, the n-type well region 130, and the n-type heavily doped region 152 constitute D1.R is R NW2 Parasitic resistance of the n-type well region 120; r is R PW2 Parasitic resistance of the p-type well region 130; the polysilicon layer overlying oxide layer region 162 and the underlying silicon surface form a capacitance C1.
The n-type heavily doped region 121 and the p-type heavily doped region 122 are connected with the anode; the n-type heavily doped region 131 and the p-type heavily doped region 132 are connected with the cathode; the polysilicon layer of oxide layer region 162 is connected to n-type heavily doped region 152; the polysilicon layer of oxide region 161 is connected to p-type heavily doped region 151.
When a positive pulse is applied to the anode of the device (cathode grounded), current flows through resistor R due to the rise of the pulse voltage NW2 Capacitor C1, diode D1, parasitic NMOS transistor gate capacitance and resistor R PW2 Reaching the cathode to form an RC1 current path, as shown by the solid line in fig. 2. Parasitic NMOS structure M with increasing voltage n2 The gate voltage of (2) is high enough that M n2 Channel is opened, and current passes through resistor R NW2 By parasitizing NMOS structure M n2 Reaching the cathode to form an NMOS1 current channel, as indicated by the dotted line in fig. 2. With increasing current, resistance R NW2 A sufficiently high voltage drop is generated across the p-n junction formed by the p-type heavily doped region 131 and the n-type well region 130, Q p2 And opening. Then, with Q p2 Increase of collector current, resistance R PW2 Creating a voltage drop across the p-n junction of the n-type heavily doped region 131 and the p-type well region 150 that is sufficiently positive, Q n2 And opening. And then, the collector current of the PNP tube provides base current for the NPN tube, the collector current of the NPN tube provides base current for the PNP tube, positive feedback is formed between the parasitic PNP tube and the NPN tube, an SCR2 current channel is formed, and the device is triggered as shown by a dotted line in FIG. 2.
Compared with the traditional LVTSCR device, the device is added with RC and NMOS current channel auxiliary triggering. A feature of the conventional LVTSCR device is to embed a GGNMOS structure to reduce the trigger voltage. The method has the advantages of maintaining the maintaining voltage and the device failure current I of the SCR structure t2 The trigger voltage is reduced without change. The device is characterized in that a reverse diode is connected between polysilicon layers on an oxide layer region, the diode is used as a capacitor, is a part of an RC channel, and plays roles of assisting in reducing trigger voltage and improving the bleeder capacity of the device. Due to M n2 The channel of the device can be opened at the rising edge of the ESD pulse, so that under the combined action of the NMOS1 current channel and the RC1 current channel, the triggering process of the device does not need p-n junction breakdown, and therefore the device can be triggered by a voltage lower than the p-n junction breakdown voltage.
To verify the working principle of the improved LVSCR of the present invention, fig. 3 shows a simulation of the discharging process of the improved LVTSCR and the conventional LVSCR under the HBM model (human body discharging model) using TACD simulation software. Fig. 3 (a) is an equivalent circuit of the simulation. When the switch is turned on (1), the power supply charges the capacitor. After the capacitor is charged, the switch is turned on (2), and the capacitor discharges the test device through the 1500 omega resistor. Fig. 3 (b) is a graph of voltage versus time during HBM ESD discharge for a modified LVTSCR device and a conventional LVTSCR device. It can be seen from the figure that during the discharge of HBM, the improvement is achievedThe peak value of the first peak and the peak value of the second peak of the voltage waveform are reduced in the LVTSCR device compared to the conventional LVTSCR device. The first peak of the voltage waveform represents the trigger voltage of the SCR device, and from simulation results, it can be seen that the trigger voltage of the improved LVTSCR device is greatly reduced compared to that of the LVTSCR device. The second peak of the voltage waveform, which is the final stage of the HBM discharge process, has a small ESD current and the LVTSCR device operates at M in order to bleed the small ESD current n1 And a breakdown state, in which the voltage is only slightly less than the trigger voltage. However, for the modified LVTSCR device, M is a low current condition n2 The current can be turned on and thus the voltage can be maintained at a relatively small value, thereby improving the robustness of the device. Therefore, the improved LVTSCR device not only can reduce the trigger voltage, but also can improve the robustness of the device.
Example 2
An embodiment of the present invention is a modified LVTSCR device with a reverse diode to reduce the trigger voltage, the device structure and equivalent circuit being shown in fig. 4.
The structure comprises a p-type silicon substrate 110;
forming an n-type deep well region 140 on the p-type silicon substrate 110;
forming a p-type well region 150 on the n-type deep well region 140;
an n-type heavily doped region 131, a p-type heavily doped region 132, an n-type well region 120, and an n-type well region 130 are formed on the p-type well region 150;
an n-type heavily doped region 121 and a p-type heavily doped region 122 are arranged in the n-type well region 120;
a p-type heavily doped region 151 and an n-type heavily doped region 152 are arranged in the n-type well region 130;
an n-type heavily doped region 141 bridging the two regions is arranged near the junction surface of the p-type well region 150 and the n-type well region 120;
an oxide layer region 162 is formed on the surface between the p-type heavily doped region 122 and the n-type heavily doped region 141, and a polysilicon layer is formed on the surface of the oxide layer region 162;
an oxide layer region 161 is formed on the surface between the n-type heavily doped region 141 and the n-type heavily doped region 131, and a polysilicon layer is formed on the surface of the oxide layer region 161;
shallow trench isolation is provided between the n-type heavily doped region 121 and the p-type heavily doped region 122, between the n-type heavily doped region 131 and the p-type heavily doped region 132, between the p-type heavily doped region 132 and the p-type heavily doped region 151, and between the p-type heavily doped region 151 and the n-type heavily doped region 152, as shown by the hatched regions in fig. 4.
The improved LVTSCR device consists of a main bleeder device and an auxiliary device; the main bleeder device is formed by a parasitic PNP transistor Q p3 A parasitic NPN transistor Q n3 And a parasitic NMOS structure M n3 The composition is formed. Wherein p-type heavily doped region 122, n-type well region 120, p-type well region 150, and p-type heavily doped region 132 constitute Q p3 The method comprises the steps of carrying out a first treatment on the surface of the n-type heavily doped region 121, n-type well region 120, n-type heavily doped region 141, p-type well region 150, and n-type heavily doped region 131 form Q n3 The method comprises the steps of carrying out a first treatment on the surface of the The n-type heavily doped region 141, the oxide layer region 161 and the n-type heavily doped region 131 constitute M n3 The method comprises the steps of carrying out a first treatment on the surface of the The auxiliary device is constituted by a reverse diode device D2. Wherein the p-type heavily doped region 151, the n-type well region 130, and the n-type heavily doped region 152 constitute D2; r is R NW3 Resistance of the n-type well region 120; r is R PW3 Resistance of the p-type well region 150; the polysilicon layer overlying oxide layer region 162 and the underlying silicon surface form a capacitor C2.
The n-type heavily doped region 121 and the p-type heavily doped region 122 are connected with the anode; the n-type heavily doped region 131 and the p-type heavily doped region 132 are connected with the cathode; the polysilicon layer of oxide layer region 162 is connected to n-type heavily doped region 152; the polysilicon layer of oxide region 161 is connected to p-type heavily doped region 151.
When a positive pulse is applied to the anode of the device (cathode grounded), current flows through resistor R due to the rise of the pulse voltage NW3 Capacitor C2, diode D2, parasitic NMOS transistor gate capacitance and resistor R PW3 Reaching the cathode to form an RC2 current path, as shown by the solid line in fig. 4. With increasing voltage, parasitic NMOS structure M n3 The gate voltage of (2) is high enough that M n3 Channel opening, current flow directly from resistor R NW3 And parasitic NMOS structure M n3 Reach the cathode to form an NMOS2 current path, such as the dummy point in FIG. 4Shown by the lines. With increasing current, resistance R NW3 A sufficiently high voltage drop is generated on the p-n junction formed by the p-type heavily doped region 131 and the n-type well region 130 to cause forward bias, and parasitic PNP transistor Q p3 And opening. Then, as the current increases, the resistance R PW3 Creating a voltage drop across the p-n junction of the n-type heavily doped region 131 and the p-type well region 150 that is sufficiently positive, Q n3 And opening. And then, the collector current of the PNP tube provides base current for the NPN tube, the collector current of the NPN tube provides base current for the PNP tube, positive feedback is formed between the parasitic PNP tube and the NPN tube, an SCR3 current channel is formed, and the device is triggered as shown by a dotted line in FIG. 4.
The newly added deep n-well 140 and p-well 150, compared to example 2, function to isolate the modified LVTSCR device above it from the p-type silicon substrate and to increase the resistivity of the well region by impurity compensation to reduce the trigger voltage of the device.
In summary, by adding a reverse diode, two current channels are formed to assist the SCR path to be started with lower trigger voltage, and the trigger mechanism after the SCR breakdown is broken, so that the LVTSCR device has lower trigger voltage. The device can be used in an ESD protection circuit with power clamp and has lower trigger voltage. And the robustness of the protection device is improved due to the peak drop of the second peak of the HBM voltage waveform.
Finally, it is noted that the above examples are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred examples, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.
Claims (3)
1. An improved LVTSCR device structure for reducing trigger voltage using a reverse diode, comprising a main bleeder device and an auxiliary device, characterized in that:
the main bleeder device comprises a first conductive type silicon substrate, wherein a first conductive type heavily doped region, a second conductive type heavily doped region and a second conductive type well region are formed on the first conductive type silicon substrate; forming a first conductive type heavily doped region and a second conductive type heavily doped region in the second conductive type well region; forming a second conductive type heavily doped region between the second conductive type well region and the first conductive type silicon substrate to cross both sides; forming a first oxide layer region on the silicon surface between the first conductive type heavily doped region and the second conductive type heavily doped regions crossing both sides in the second conductive type well region; forming a second oxide layer region on the silicon surface between the second conductive type heavily doped region formed on the first conductive type silicon substrate and the second conductive type heavily doped region crossing both sides; the auxiliary device comprises a second conductive type well region formed on the first conductive type silicon substrate; forming a first conductive type heavily doped region and a second conductive type heavily doped region on the second conductive type well region;
the second conductive type heavily doped region and the first conductive type heavily doped region in the second conductive type well region in the main bleeder device are connected with the anode; the first heavily doped region and the second heavily doped region on the first conductive type silicon substrate in the main bleeder device are directly connected with the cathode; the first oxide layer region is covered with a polysilicon layer and is connected with a second conductive type heavily doped region in a second conductive type well region in the auxiliary device; the second oxide layer region is covered with a polysilicon layer and is connected to the first conductivity type heavily doped region in the second conductivity type well region in the auxiliary device.
2. The device of claim 1 wherein the polysilicon layer on the first oxide layer region is connected to a heavily doped region of the second conductivity type formed on a well region of the second conductivity type in the auxiliary device; the polysilicon layer on the second oxide layer region is connected with the first conductive type heavily doped region formed on the second conductive type well region in the auxiliary device, namely, a reverse diode is connected between the polysilicon layers on the two oxide layer regions.
3. The improved LVTSCR device structure of claim 1 wherein said main bleeder device shares a silicon substrate of a first conductivity type with said auxiliary device and wherein said auxiliary device has a device width that is the same as or different from a device width of said main bleeder device.
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| CN108336082A (en) * | 2017-01-18 | 2018-07-27 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection devices and electrostatic discharge protective circuit |
| CN107731810A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of low trigger voltage MLSCR devices for ESD protection |
| CN108538831A (en) * | 2018-04-10 | 2018-09-14 | 电子科技大学 | A kind of SCR device for input/output port and power clamp |
| CN110335866A (en) * | 2019-06-26 | 2019-10-15 | 电子科技大学 | A kind of two-way low triggering ESD protective device based on nanometer-grade IC technique |
| CN111341770A (en) * | 2020-02-19 | 2020-06-26 | 中国科学院微电子研究所 | ESD protection structure, integrated circuit and equipment with low trigger voltage |
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