CN112071834A - Gate-constrained silicon controlled rectifier and implementation method thereof - Google Patents
Gate-constrained silicon controlled rectifier and implementation method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 43
- 239000010703 silicon Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 40
- 229910021332 silicide Inorganic materials 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 19
- 230000000694 effects Effects 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 description 46
- 238000013461 design Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Abstract
The invention discloses a gate-constrained silicon controlled rectifier and an implementation method thereof, wherein the part of a second P-type grid (50) covering a P well in the existing novel gate-constrained silicon controlled rectifier is removed, the part of the second P-type grid covering the N well is reserved, the second P-type grid (50) is connected with high-concentration P-type doping (20), and an electrode is led out to form an anode of the gate-constrained silicon controlled rectifier.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a novel grid-constrained silicon controlled rectifier and an implementation method thereof.
Background
In the field of integrated circuit anti-static protection design, an anti-static protection design window generally depends on working voltage and gate oxide thickness of an internal protected circuit, and taking a 55LP advanced process platform of a certain company as an example, the working voltage of a core device (1.2V MOSFET) of the anti-static protection design window is 1.2V, and the gate oxide thickness is 25A (angstrom, 0.1nm), so the anti-static protection design window of the core device (1.2V MOSFET) of the 55LP advanced process platform of the company is usually between 1.32V and 5V. However, as shown in fig. 1, the hysteresis effect characteristic curve of the core device (1.2V nmos) of the company 55LP advanced process platform shows that the trigger voltage (Vt1, voltage corresponding to the inflection point at the lower position of the right curve) of the core device is 6.7V, which exceeds the anti-static protection design window of the core device, and if the core device (1.2V nmos) is directly used for the anti-static protection design, the reliability problem of the gate oxide layer of the core device (1.2V MOSFET) is easily caused.
One company in the industry first proposed a gate-tied scr as shown in fig. 2 in an attempt to solve the esd protection design problem of the advanced platform core device.
As shown in fig. 2, the conventional gate-tied scr ESD device includes a plurality of Shallow Trench Isolation (STI) layers 10, high-concentration N-type dopants (N +)28, high-concentration P-type dopants (P +)20, high-concentration N-type dopants (N +)24, high-concentration P-type dopants (P +)26, N-wells (N-Well)60, P-wells (P-Well)70, P-type substrates (P-sub)80, first P-type gates 40, second P-type gates 50, and a plurality of metal silicides (silicides) 30 connecting doped regions and electrodes.
The whole ESD device is arranged on a P-type substrate (P-sub)80, an N-Well (N-Well)60 is generated on the left side of the P-type substrate (P-sub)80, a P-Well (P-Well)70 is generated on the right side of the P-type substrate (P-sub)80, high-concentration N-type doping (N +)28 and high-concentration P-type doping (P +)20 are arranged on the upper portion of the N-Well (N-Well)60, high-concentration P-type doping (P +)20, the N-Well (N-Well)60 and the P-Well (P-Well)70 form an equivalent PNP triode structure, high-concentration N-type doping (N +)24 and high-concentration P-type doping (P +)26 are arranged on the upper portion of the P-Well (P-Well)70, and the N-Well (N-Well)60, the P-Well (P-Well)70 and the high-concentration N-type doping (N +)24 form an equivalent NPN triode structure;
shallow Trench Isolation (STI, Shallow Trench Isolation)10 is disposed on the left side of the high concentration N-type dopant (N +)28, the high concentration N-type dopant (N +)28 and the high concentration P-type dopant (P +)20 are separated by N-Well (N-Well)60 (i.e., a portion of the N-Well 60 is spaced therebetween), a first P-type gate 40 is disposed above the N-Well, the right side of the high concentration P-type dopant (P +)20 is a portion of the N-Well (N-Well)60, the right side of the high concentration P-type dopant (P +)20 is separated from the N-Well (N-Well)60 and the P-Well (P-Well)70 by a width a, the high concentration N-type dopant (N +)24, the high concentration P-type dopant (P +)26 is separated by Shallow Trench Isolation (STI, the Shallow Trench Isolation 10 is disposed on the right side of the high concentration P-type dopant (P +)26, the left side of the high concentration N-type dopant (N +)24 is a portion of the P-Well (P-Well)70, and the width from the left side of the high concentration N-type dopant (N +)24 to the boundary of the N-Well (N-Well)60 and the P-Well (P-Well)70 is B;
4 metal silicides 30 are generated above the high-concentration N-type doping (N +)28, above the high-concentration P-type doping (P +)20, above the high-concentration N-type doping (N +)24 and above the high-concentration P-type doping (P +)26, and a second P-type grid 50 is arranged above a P well with the width of B on the left side of the high-concentration N-type doping (N +)24 and above an N well with the width of A on the right side of the high-concentration P-type doping (P +)20, namely the second P-type grid 50 is arranged above the boundary of the N well and the P well and does not cover the high-concentration P-type doping (P +)20 and the high-concentration N-type doping (N +) 24;
the leading-out electrode of the metal silicide 30 above the high-concentration N-type doping (N +)28 is connected to a power supply Vdd, the leading-out electrode of the metal silicide 30 above the high-concentration P-type doping (P +)20 is used as an Anode Anode of the novel grid-constraint silicon controlled rectifier ESD device, the second P-type grid 50 is connected with the metal silicide 30 above the high-concentration N-type doping (N +)24 and the metal silicide 30 above the high-concentration P-type doping (P +)26 and is led out to form a Cathode Cathode of the conventional grid-constraint silicon controlled rectifier ESD device, and the Cathode is grounded Vss when the grid-constraint silicon controlled rectifier ESD device is used.
The gate-constrained silicon controlled rectifier ESD device shown in FIG. 2 has a working voltage of 1.0V for an advanced process platform, a gate oxide layer thickness of 14A, and an anti-static protection design window of 1.2V-2.8V, which is slightly different from a 55LP advanced process platform of the company, and the actual measurement result shows that the holding voltage of the ESD device is too low, and is only about 1.2V.
Next, based on the gate-tied scr as shown in fig. 2, the improved Schottky Junction-embedded scr as shown in fig. 3 is proposed to raise its sustain voltage (Vh), i.e., the metal layer 22 is formed directly above the P-Well (P-Well)70 on the left side of the high concentration N-type dopant (N +)24 to form a Schottky Junction (Schottky Junction), and the second P-type gate (gate) 50 is formed above the P-Well (P-Well)70 with a width of B-S on the left side of the metal layer 22 and above the N-Well (N-Well)60 with a width of a on the right side of the high concentration P-type dopant (P +) 20.
The hysteresis effect characteristic (left curve) of the gate-tied scr as shown in fig. 2 and the hysteresis effect characteristic (right curve) of the improved gate-tied scr as shown in fig. 3 are shown in fig. 4, where the higher inflection point at the left side of each hysteresis effect characteristic corresponds to the holding voltage Vh, the lower inflection point at the right side corresponds to the trigger voltage Vt1, the hysteresis effect characteristics of fig. 2 and fig. 3 are compared with the upper left corner of fig. 4, the parameters Vh and Vt1 to be compared in the first P-type behavior, the specific values of Vh and Vt1 in the second P-type behavior diagram 2(w/o Schottky, without Schottky junction), the third row is the specific values of Vh and Vt1 in fig. 3(w/l Schottky junction, with Schottky junction), as can be derived from fig. 4, the gate-tied scr as shown in fig. 3 can raise the holding voltage Vh of the hysteresis effect from 1.2V 2 to V2, the trigger voltage Vt1 is controlled to be 2.4V, which is still lower than 2.8V, so the gate-tied scr with embedded schottky junction as shown in fig. 3 is more suitable for the esd protection design of the core device of the 55LP advanced CMOS integrated circuit. However, the introduction of the Schottky junction causes the process to be more complicated, and in addition, the metal-semiconductor contact interface is easy to introduce interface defects.
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a gate-tied scr and a method for implementing the same, so as to improve the sustain voltage, simplify the manufacturing process, and reduce the interface defect caused by the introduction of the schottky junction.
To achieve the above and other objects, the present invention provides a gate-tied scr, comprising:
a semiconductor substrate (80);
an N-well (60) and a P-well (70) formed in the semiconductor substrate (80);
the high-concentration N-type doping (28) and the high-concentration P-type doping (20) are sequentially arranged on the upper portion of an N well (60), the high-concentration N-type doping (24) and the high-concentration P-type doping (26) are sequentially arranged on the upper portion of a P well (70), the right side of the high-concentration P-type doping (20) is a part of the N well (60), the width from the right side of the high-concentration P-type doping (20) to the boundary of the N well (60) and the P well (70) is A, the left side of the high-concentration N-type doping (24) is a part of the P well (70), and the width from the left side of the high-concentration N-type doping (24) to the boundary of the N well (60) and the P well (70) is B;
respectively generating metal silicides (30) above the high-concentration N-type doping (28), the high-concentration P-type doping (20), the high-concentration N-type doping (24) and the high-concentration P-type doping (26), and arranging a second P-type grid (50) above the N well (60) with the width of A;
the metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) is connected to a power supply, the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) is connected with the second P-type grid electrode (50) and forms an anode of the grid-constrained silicon controlled rectifier, and the metal silicide (30) above the high-concentration N-type doping (24) is connected with the metal silicide (30) above the high-concentration P-type doping (26) and forms a cathode of the grid-constrained silicon controlled rectifier.
Preferably, the high concentration P-type doping (20), the N-well (60), and the P-well (70) constitute an equivalent PNP triode structure.
Preferably, the N well (60), the P well (70) and the high-concentration N-type doping (24) form an equivalent NPN triode structure.
Preferably, the second gate (50) is a P-type gate.
Preferably, a shallow channel isolation layer (10) is arranged on the left side of the high-concentration N-type doping (28), the high-concentration N-type doping (28) and the high-concentration P-type doping (20) are isolated by the N well (60), and a first grid electrode (40) is arranged above the part of the N well.
Preferably, the first gate (40) is a P-type gate.
Preferably, a shallow channel isolation layer (10) is arranged on the right side of the high-concentration P-type doping (26), and the high-concentration N-type doping (24) and the high-concentration P-type doping (26) are isolated by the shallow channel isolation layer (10).
Preferably, the value of A, B determines the holding voltage Vh and the trigger voltage Vt1, A, B of the gate-tied scr hysteretic effect to be 0.2um to 1 um.
In order to achieve the purpose, the invention also provides a method for realizing the gate-constrained silicon controlled rectifier, which is characterized in that the part of the second P-type grid (50) covering the P well in the existing novel gate-constrained silicon controlled rectifier is removed, the part of the second P-type grid covering the N well is reserved, and the second P-type grid (50) is connected with the high-concentration P-type doping (20) and the leading-out electrode forms the anode of the gate-constrained silicon controlled rectifier.
Preferably, the method comprises:
step S1, providing a semiconductor substrate (80);
step S2, generating an N-well (60) and a P-well (70) in the semiconductor substrate (80);
step S3, sequentially placing high-concentration N-type doping (28) and high-concentration P-type doping (20) on the upper portion of an N well (60), placing high-concentration N-type doping (24) and high-concentration P-type doping (26) on the upper portion of a P well (70), wherein the right side of the high-concentration P-type doping (20) is a part of the N well (60), the width from the right side of the high-concentration P-type doping (20) to the boundary of the N well (60) and the P well (70) is A, the left side of the high-concentration N-type doping (24) is a part of the P well (70), and the width from the left side of the high-concentration N-type doping (24) to the boundary of the N well (60) and the P well (70) is B;
step S4, respectively generating metal silicides (30) above the high-concentration N-type doping (28), above the high-concentration P-type doping (20), above the high-concentration N-type doping (24) and above the high-concentration P-type doping (26), and arranging the second P-type grid (50) above the N well (60) with the width of A;
and step S5, connecting a metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) to a power supply, connecting the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) with the second P-type grid (50) and leading-out electrode to form an anode of the grid-constrained silicon controlled rectifier, and connecting the metal silicide (30) above the high-concentration N-type doping (24) with the metal silicide (30) above the high-concentration P-type doping (26) and leading-out electrode to form a cathode of the grid-constrained silicon controlled rectifier.
Compared with the prior art, the gate-constrained silicon-controlled rectifier and the implementation method thereof provided by the invention have the advantages that the part of the N-type gate electrode covering the P well in the existing gate-constrained silicon-controlled rectifier is removed, the part covering the N well is reserved, and the N-type gate electrode and the high-concentration P-type doping 20 are connected to the anode of the novel gate-constrained silicon-controlled rectifier together.
Drawings
FIG. 1 is a hysteresis effect characteristic curve of 1.2V GGNMOS of a 55LP advanced technology platform of a company;
FIG. 2 is a diagram of a prior art ESD device with a gate-tied SCR;
FIG. 3 is a block diagram of a prior art improved gate-tied SCR ESD device with an embedded Schottky junction;
FIG. 4 is a graph showing the comparison of hysteresis effect characteristics of a gate-tied SCR with or without Schottky junctions;
FIG. 5 is a diagram of the structure of a gate-tied SCR device according to a preferred embodiment of the present invention;
FIG. 6 is a flowchart illustrating steps of a method for implementing a gate-tied SCR according to the present invention;
FIG. 7 is a schematic diagram of an application scenario of the present invention;
FIG. 8 is a graph showing the actual hysteresis effect of the gate-tied SCR of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 5 is a diagram of the structure of a gate-tied SCR according to a preferred embodiment of the present invention. As shown in fig. 5, a gate-tied scr of the present invention includes: the device comprises a plurality of Shallow Trench Isolation (STI) layers 10, high-concentration N-type doping (N +)28, high-concentration P-type doping (P +)20, high-concentration N-type doping (N +)24, high-concentration P-type doping (P +)26, an N Well (N-Well)60, a P Well (P-Well)70, a P substrate (P-Sub)80, a first P-type grid 40, a second P-type grid 50 and a plurality of metal Silicide (Silicide)30 for connecting a doping region and an electrode.
The whole ESD device is arranged on a P-type substrate (P-Sub)80, an N-Well (N-Well)60 is generated on the left side of the P-type substrate (P-Sub)80, a P-Well (P-Well)70 is generated on the right side of the P-type substrate (P-Sub)80, high-concentration N-type doping (N +)28 and high-concentration P-type doping (P +)20 are arranged on the upper portion of the N-Well (N-Well)60, high-concentration P-type doping (P +)20, the N-Well (N-Well)60 and the P-Well (P-Well)70 form an equivalent PNP triode structure, high-concentration N-type doping (N +)24 and high-concentration P-type doping (P +)26 are arranged on the upper portion of the P-Well (P-Well)70, and the N-Well (N-Well)60, the P-Well (P-Well)70 and the high-concentration N-type doping (N +)24 form an equivalent NPN triode structure;
shallow Trench Isolation (STI, Shallow Trench Isolation)10 is disposed on the left side of the high concentration N-type dopant (N +)28, the high concentration N-type dopant (N +)28 and the high concentration P-type dopant (P +)20 are separated by N-Well (N-Well)60 (i.e., a portion of the interval between them is 60), a first P-type gate 40 is disposed above the N-Well, the right side of the high concentration P-type dopant (P +)20 is a portion of the N-Well (N-Well)60, the right side of the high concentration P-type dopant (P +)20 is separated from the N-Well (N-Well)60 to the P-Well (P-Well)70 by a width a, the high concentration N-type dopant (N +)24, the high concentration P-type dopant (P +)26 is separated by Shallow Trench Isolation (STI, Shallow Trench Isolation)10 is disposed on the right side of the high concentration P-type dopant (P +)26, the left side of the high concentration N-type dopant (N +)24 is a portion of the P-Well (P-Well)70, and the width from the left side of the high concentration N-type dopant (N +)24 to the boundary of the N-Well (N-Well)60 and the P-Well (P-Well)70 is B;
4 metal silicides 30 are generated above the high-concentration N-type doping (N +)28, above the high-concentration P-type doping (P +)20, above the high-concentration N-type doping (N +)24 and above the high-concentration P-type doping (P +)26, and a second P-type grid 50 is arranged above an N well with the width A on the right side of the high-concentration P-type doping (P +) 20;
the leading-out electrode of the metal silicide 30 above the high-concentration N-type doping (N +)28 is connected to a power supply Vdd, the leading-out electrode of the metal silicide 30 above the high-concentration P-type doping (P +)20 is connected with a second P-type grid 50 and forms an Anode Anode of the novel grid-restrained silicon controlled rectifier ESD device, the metal silicide 30 above the high-concentration N-type doping (N +)24 and the metal silicide 30 above the high-concentration P-type doping (P +)26 are connected and form a Cathode Cathode of the conventional grid-restrained silicon controlled rectifier ESD device, and the Cathode is grounded Vss when the grid-restrained silicon controlled rectifier ESD device is used.
It can be seen that, in the ESD device of the conventional gate-tied scr of fig. 2, the part of the N-type gate 50 covering the P-Well is actually removed, the part covering the N-Well is remained, and the N-type gate 50 is connected to the high-concentration P-type dopant (P +)20 and the extraction electrode constitutes the Anode of the gate-tied scr of the present invention, when a positive voltage is applied to the Anode, the N-type gate 50 connected to the Anode causes a large amount of electrons in the N-Well (N-Well)60 to accumulate under the N-type gate 50, which can reduce the efficiency of injecting holes from (P +)20 into the N-Well (N-Well)60 and migrating to the interface of the N-Well (N-Well) 60/P-Well (P-Well)70, reduce the current gain (β) of the parasitic PNP (high-concentration P-type dopant (P +) 20/N-Well (N-Well) 60/P-Well (P-Well)70) transistor inside the scr, thereby improving the holding voltage (Vh) of the gate-tied SCR of the present invention. The novel grid-constrained silicon controlled rectifier provided by the invention does not need to introduce a Schottky junction, and the manufacturing process is simplified while the maintaining voltage of the novel grid-constrained silicon controlled rectifier is improved, so that the novel grid-constrained silicon controlled rectifier provided by the invention is more suitable for the anti-static protection design of a 55LP advanced CMOS process integrated circuit core device.
FIG. 6 is a flowchart illustrating steps of a method for implementing a gate-tied SCR according to the present invention. As shown in fig. 6, the method for implementing a gate-tied scr of the present invention includes the following steps:
in step S1, a semiconductor substrate, in this embodiment of the invention, a P-type substrate (P-Sub)80 is provided.
In step 2, two wells, i.e., N-Well (N-Well)60 and P-Well (P-Well)70, are formed in the semiconductor substrate, wherein in the embodiment of the present invention, the N-Well (N-Well)60 and the P-Well (P-Well)70 are formed in the P-type substrate (P-Sub)80, the N-Well (N-Well)60 is formed on the left side of the P-type substrate (P-Sub)80, and the P-Well (P-Well)70 is formed on the right side of the P-type substrate (P-Sub) 80.
In step S3, an equivalent PNP triode structure is formed in the N-Well (N-Well)60, and an equivalent NPN triode structure is formed in the P-Well 70. Specifically, a high concentration N-type dopant (N +)28, a high concentration P-type dopant (P +)20 are disposed on the upper portion of an N-Well (N-Well)60, the high concentration P-type dopant (P +)20, the N-Well (N-Well)60 and a P-Well (P-Well)70 constitute an equivalent PNP triode structure, a Shallow Trench Isolation (STI) 10 is disposed on the left side of the high concentration N-type dopant (N +)28, the high concentration N-type dopant (N +)28 and the high concentration P-type dopant (P +)20 are separated by the N-Well (N-Well)60 (i.e., a portion of the interval therebetween is 60), a first P-type gate 40 is disposed above the portion of the N-Well, the right side of the high concentration P-type dopant (P +)20 is a portion of the N-Well (N-Well)60, the right side of the high concentration P-type dopant (P +)20 is a width a to the boundary between the N-Well (N-Well)60 and the P-Well (P-Well)70, the high-concentration N-type doping (N +)24 and the high-concentration P-type doping (P +)26 are arranged on the upper portion of a P Well (P-Well)70, the high-concentration N-type doping (N +)24 and the high-concentration P-type doping (P +)26 are separated by a Shallow Trench Isolation (STI) 10, the Shallow Trench Isolation (STI) 10 is arranged on the right side of the high-concentration P-type doping (P +)26, the left side of the high-concentration N-type doping (N +)24 is a part of the P Well (P-Well)70, and the width from the left side of the high-concentration N-type doping (N +)24 to the boundary of the N Well (N-Well)60 and the P Well (P-Well)70 is B.
In step S4, 4 metal silicides 30 are formed above the high concentration N-type dopant (N +)28, above the high concentration P-type dopant (P +)20, above the high concentration N-type dopant (N +)24, and above the high concentration P-type dopant (P +)26, and a second P-type gate 50 is disposed above the N-well with a width a on the right side of the high concentration P-type dopant (P +) 20.
Step S5, the leading-out electrode of the metal silicide 30 above the high-concentration N-type dopant (N +)28 is connected to a power supply Vdd, the leading-out electrode of the metal silicide 30 above the high-concentration P-type dopant (P +)20 is connected to the second P-type gate 50 and the leading-out electrode forms an Anode of the new gate-tied scr ESD device, the metal silicide 30 above the high-concentration N-type dopant (N +)24 and the metal silicide 30 above the high-concentration P-type dopant (P +)26 are connected and the leading-out electrode forms a Cathode of the existing gate-tied scr ESD device, and the Cathode Vss is grounded when the device is in use.
Therefore, on the basis of the original gate-constrained silicon controlled rectifier (as shown in fig. 2), the part of the N-type gate covering the P-well in the original gate-constrained silicon controlled rectifier is removed, the part covering the N-well is reserved, the N-type gate and the P +20 are connected to the anode of the gate-constrained silicon controlled rectifier together, the critical dimension A, B determines the holding voltage Vh and the trigger voltage Vt1 of the hysteresis effect of the gate-constrained silicon controlled rectifier, and the typical value range of A, B is 0.2um to 1 um.
When in use, in order to protect the IO port, the Cathode Cathodode of the grid-constrained silicon controlled rectifier of the invention is grounded Vss, the Vdd end (namely the metal silicide 30 above the high-concentration N-type doping (N +) 28) is connected with the power voltage Vdd, and the Anode Anode is connected with the external IO (input/output end); in order to protect the power supply, some other ESD protection device can be connected after the new gate-tied scr ESD device to obtain the required characteristics, as shown in fig. 7.
By applying the gate-tied SCR of the present invention to a 55LP advanced process platform, in practical verification, a hysteresis effect characteristic curve of the gate-tied SCR of the present invention is obtained as shown in FIG. 8, which indicates that the trigger voltage Vt1 of the gate-tied SCR of the present invention is 3.59V, the sustain voltage Vh is 1.42V, the leakage current is 5nA/um, and the second breakdown current It2 is 38mA/um, which further indicates that the gate-tied SCR of the present invention is fully applicable to the anti-static protection design of the core device (1.2V MOSFET) of the 55LP advanced process platform.
In summary, the gate-tied silicon controlled rectifier and the implementation method thereof remove the part of the N-type gate covering the P-well in the existing gate-tied silicon controlled rectifier, remain to cover the N-well, and connect the N-type gate and the high-concentration P-type dopant 20 to the anode of the novel gate-tied silicon controlled rectifier together.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A gate-tied silicon controlled rectifier, the rectifier comprising:
a semiconductor substrate (80);
an N-well (60) and a P-well (70) formed in the semiconductor substrate (80);
the high-concentration N-type doping (28) and the high-concentration P-type doping (20) are sequentially arranged on the upper portion of an N well (60), the high-concentration N-type doping (24) and the high-concentration P-type doping (26) are sequentially arranged on the upper portion of a P well (70), the right side of the high-concentration P-type doping (20) is a part of the N well (60), the width from the right side of the high-concentration P-type doping (20) to the boundary of the N well (60) and the P well (70) is A, the left side of the high-concentration N-type doping (24) is a part of the P well (70), and the width from the left side of the high-concentration N-type doping (24) to the boundary of the N well (60) and the P well (70) is B;
respectively generating metal silicides (30) above the high-concentration N-type doping (28), the high-concentration P-type doping (20), the high-concentration N-type doping (24) and the high-concentration P-type doping (26), and arranging a second grid (50) above the N well (60) with the width of A;
the metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) is connected to a power supply, the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) is connected with the second P-type grid electrode (50) and forms an anode of the grid-constrained silicon controlled rectifier, and the metal silicide (30) above the high-concentration N-type doping (24) is connected with the metal silicide (30) above the high-concentration P-type doping (26) and forms a cathode of the grid-constrained silicon controlled rectifier.
2. The gate-tied scr of claim 1 wherein: the high concentration P-type doping (20), the N-well (60), and the P-well (70) form an equivalent PNP triode structure.
3. The gate-tied scr of claim 1 wherein: the N well (60), the P well (70) and the high-concentration N-type doping (24) form an equivalent NPN triode structure.
4. The gate-tied scr of claim 1 wherein: the second gate (50) is a P-type gate.
5. The gate-tied scr of claim 1 wherein: a shallow channel isolation layer (10) is arranged on the left side of the high-concentration N-type doping (28), the high-concentration N-type doping (28) and the high-concentration P-type doping (20) are isolated by the N well (60), and a first grid electrode (40) is arranged above the part of the N well.
6. The gate-tied scr of claim 5 wherein: the first gate (40) is a P-type gate.
7. The gate-tied scr of claim 5 wherein: shallow channel isolation layers (10) are arranged on the right sides of the high-concentration P-type dopings (26), and the high-concentration N-type dopings (24) and the high-concentration P-type dopings (26) are isolated by the shallow channel isolation layers (10).
8. The gate-tied scr of claim 7 wherein: A. the value range of the holding voltage Vh and the trigger voltage Vt1, A, B of the gate-constrained silicon controlled rectifier hysteresis effect is determined by the size of B to be 0.2 um-1 um.
9. A method for realizing a grid-constrained silicon controlled rectifier is characterized by comprising the following steps: the part of a second P-type grid electrode (50) covering the P well in the existing novel grid-constrained silicon controlled rectifier is removed, the part of the second P-type grid electrode covering the N well is reserved, and the second P-type grid electrode (50) is connected with high-concentration P-type doping (20) and an electrode is led out to form the anode of the grid-constrained silicon controlled rectifier.
10. The method of claim 9, wherein the method comprises:
step S1, providing a semiconductor substrate (80);
step S2, generating an N-well (60) and a P-well (70) in the semiconductor substrate (80);
step S3, sequentially placing high-concentration N-type doping (28) and high-concentration P-type doping (20) on the upper portion of an N well (60), placing high-concentration N-type doping (24) and high-concentration P-type doping (26) on the upper portion of a P well (70), wherein the right side of the high-concentration P-type doping (20) is a part of the N well (60), the width from the right side of the high-concentration P-type doping (20) to the boundary of the N well (60) and the P well (70) is A, the left side of the high-concentration N-type doping (24) is a part of the P well (70), and the width from the left side of the high-concentration N-type doping (24) to the boundary of the N well (60) and the P well (70) is B;
step S4, respectively generating metal silicides (30) above the high-concentration N-type doping (28), above the high-concentration P-type doping (20), above the high-concentration N-type doping (24) and above the high-concentration P-type doping (26), and arranging the second P-type grid (50) above the N well (60) with the width of A;
and step S5, connecting a metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) to a power supply, connecting the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) with the second P-type grid (50) and leading-out electrode to form an anode of the grid-constrained silicon controlled rectifier, and connecting the metal silicide (30) above the high-concentration N-type doping (24) with the metal silicide (30) above the high-concentration P-type doping (26) and leading-out electrode to form a cathode of the grid-constrained silicon controlled rectifier.
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