CN110518012B - Grid-constrained silicon controlled rectifier ESD device and implementation method thereof - Google Patents
Grid-constrained silicon controlled rectifier ESD device and implementation method thereof Download PDFInfo
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- CN110518012B CN110518012B CN201910809608.1A CN201910809608A CN110518012B CN 110518012 B CN110518012 B CN 110518012B CN 201910809608 A CN201910809608 A CN 201910809608A CN 110518012 B CN110518012 B CN 110518012B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 35
- 239000010703 silicon Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 41
- 238000000605 extraction Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 24
- 238000002955 isolation Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 12
- 230000000694 effects Effects 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 description 19
- 230000008569 process Effects 0.000 description 8
- 230000007547 defect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention discloses a grid-constrained silicon controlled rectifier ESD device and a realization method thereof, wherein high-concentration P-type doping of a connecting anode of the existing grid-constrained silicon controlled rectifier ESD device is replaced by low-concentration P-type light doping (20), a metal silicide (30) is formed on the upper surface of the grid-constrained silicon controlled rectifier ESD device, and an extraction electrode is taken as the anode of the grid-constrained silicon controlled rectifier ESD device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit technology, and in particular, to a novel gate-tied silicon controlled rectifier (ESD) device and an implementation method thereof.
Background
In the field of esd protection design of integrated circuits, an esd protection design window generally depends on a working voltage and a Gate oxide thickness of an internal protected circuit, and for example, the working voltage of an integrated circuit in an advanced CMOS process is about 1V, and the Gate oxide thickness is about 14A (angstroms, 0.1nm), the esd protection design window of the integrated circuit in the advanced CMOS process is generally between 1.2V and 2.8V, and a trigger voltage (Vt1) of a hysteresis effect of a typical GGNMOS (group-Gate NMOS) esd protection device in the advanced CMOS process is generally greater than 2.8V, so the industry first proposed a Gate-constrained silicon controlled rectifier as shown in fig. 1 to solve the problem.
As shown in fig. 1, the conventional gate-tied scr ESD device includes a plurality of Shallow Trench Isolation (STI) layers 10, high-concentration N-type dopants (N +)28, high-concentration P-type dopants (P +)20, high-concentration N-type dopants (N +)24, high-concentration P-type dopants (P +)26, N-wells (N-Well)60, P-wells (P-Well)70, P-type substrates (P-Sub)80, a first floating gate 40, a second gate 50, and a plurality of metal silicides (Silicide)30 connecting doped regions and electrodes.
The whole ESD device is arranged on a P-type substrate (P-Sub)80, an N-Well (N-Well)60 is generated on the left side of the P-type substrate (P-Sub)80, a P-Well (P-Well)70 is generated on the right side of the P-type substrate (P-Sub)80, high-concentration N-type doping (N +)28 and high-concentration P-type doping (P +)20 are arranged on the upper portion of the N-Well (N-Well)60, high-concentration P-type doping (P +)20, the N-Well (N-Well)60 and the P-Well (P-Well)70 form an equivalent PNP triode structure, high-concentration N-type doping (N +)24 and high-concentration P-type doping (P +)26 are arranged on the upper portion of the P-Well (P-Well)70, and the N-Well (N-Well)60, the P-Well (P-Well)70 and the high-concentration N-type doping (N +)24 form an equivalent NPN triode structure;
shallow channel Isolation layer (STI) 10 is placed on the left side of high concentration N-type doping (N +)28, N-Well 60 (i.e. a part of interval 60 between N-Well and P-Well) 20 of high concentration N-type doping (N +)28 and P-Well) 20, first floating gate 40 is placed above the N-Well of the part, the right side of high concentration P-type doping (P +)20 is a part of N-Well 60, the width of N-Well 60 of the part is A, Shallow channel Isolation layer (STI, Shallow channel Isolation layer) 10 is placed on the right side of high concentration P-type doping (P +)26, high concentration N-type doping (N +)24 and high concentration P-type doping (P +)26 are separated by Shallow channel Isolation layer (STI, Shallow channel Isolation layer) 10 is placed on the left side of high concentration N-type doping (N +)24, and P-Well 70 is placed on the left side of high concentration N-type doping (N +)24, the width of the portion of the P-Well (P-Well)70 is B;
4 metal silicides 30 are generated above the high-concentration N-type doping (N +)28, above the high-concentration P-type doping (P +)20, above the high-concentration N-type doping (N +)24 and above the high-concentration P-type doping (P +)26, and a second grid 50 is arranged above a P well with the width of B on the left side of the high-concentration N-type doping (N +)24 and above an N well with the width of A on the right side of the high-concentration P-type doping (P +)20, namely the second grid 50 is arranged above the boundary of the N well and the P well and does not cover the high-concentration P-type doping (P +)20 and the high-concentration N-type doping (N +) 24;
the leading-out electrode of the metal silicide 30 above the high-concentration N-type doping (N +)28 is connected to a power supply Vdd, the leading-out electrode of the metal silicide 30 above the high-concentration P-type doping (P +)20 is used as an Anode Anode of the novel grid-constraint silicon controlled rectifier ESD device, the second grid 50 is connected with the metal silicide 30 above the high-concentration N-type doping (N +)24 and the metal silicide 30 above the high-concentration P-type doping (P +)26 and is led out to form a Cathode Cathode of the conventional grid-constraint silicon controlled rectifier ESD device, and the Cathode is grounded Vss when the grid-constraint silicon controlled rectifier ESD device is used.
The measurement results show that the maintaining voltage (Vh) is too low, and is only about 1.2V.
At present, the industry also proposes an improved Schottky Junction embedded scr as shown in fig. 2 to raise the sustain voltage (Vh) based on the gate-tied scr as shown in fig. 1, i.e. a metal layer 22 is formed directly above a P-Well (P-Well)70 on the left side of a high concentration N-type dopant (N +)24 to form a Schottky Junction (Schottky Junction), and a second gate (floating gate) 50 is formed above a P-Well (P-Well)70 with a width of B-S on the left side of the metal layer 22 and above an N-Well (N-Well)60 with a width of a on the right side of the high concentration P-type dopant (P +) 20.
The hysteresis effect characteristics of the gate-tied scr as shown in fig. 1 and the improved gate-tied scr as shown in fig. 2 are shown in fig. 3, the left side is the characteristic curve of fig. 1, and the right side is the characteristic curve of fig. 2, as can be seen from fig. 3, the improved gate-tied scr with embedded schottky junction as shown in fig. 2 can raise the holding voltage of the hysteresis effect from 1.2V to 2V, while the trigger voltage is controlled at 2.4V, which is still lower than 2.8V, so the gate-tied scr with embedded schottky junction as shown in fig. 2 is more suitable for the anti-static protection design of the advanced CMOS process integrated circuit. However, the introduction of the schottky junction causes the process to be more complicated, in addition, interface defects are easily introduced into a metal semiconductor contact interface, and the contact resistance of the schottky junction is higher.
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a gate-tied scr ESD device and a method for implementing the same, so as to improve the holding voltage, simplify the manufacturing process, reduce the interface defect caused by the introduction of the schottky junction, and reduce the contact resistance.
To achieve the above and other objects, the present invention provides a gate-tied scr ESD device, comprising:
a semiconductor substrate (80);
an N-well (60) and a P-well (70) formed in the semiconductor substrate (80);
high-concentration N-type doping (28) and low-concentration P-type light doping (20) are arranged on the upper portion of an N well (60), and high-concentration N-type doping (24) and high-concentration P-type doping (26) are arranged on the upper portion of a P well (70);
respectively generating metal silicides (30) above the high-concentration N-type doping (28), above the low-concentration P-type light doping (20), above the high-concentration N-type doping (24) and above the high-concentration P-type doping (26);
and the metal silicide (30) extraction electrode above the high-concentration N-type doping (28) is connected to a connecting power supply, the metal silicide (30) extraction electrode above the low-concentration P-type light doping (20) is used as an anode of the grid-constrained silicon controlled rectifier ESD device, and the metal silicide (30) above the high-concentration N-type doping (24) is connected with the metal silicide (30) above the high-concentration P-type doping (26) and the extraction electrode forms a cathode of the grid-constrained silicon controlled rectifier ESD device.
Preferably, the low concentration P-type light doping (20), the N-well (60), and the P-well (70) constitute an equivalent PNP triode structure.
Preferably, the N well (60), the P well (70) and the high-concentration N-type doping (24) form an equivalent NPN triode structure.
Preferably, a shallow channel isolation layer (10) is arranged on the left side of the high-concentration N-type doping (28), the high-concentration N-type doping (28) and the low-concentration P-type lightly doping (20) are isolated by the N well (60), a first floating gate (40) is arranged above the part of the N well, the right side of the low-concentration P-type lightly doping (20) is a part of the N well (60), and the width of the part of the N well is A.
Preferably, the high-concentration N-type doping (24) and the high-concentration P-type doping (26) are isolated by a shallow trench isolation layer (10), the shallow trench isolation layer (10) is arranged on the right side of the high-concentration P-type doping (26), the left side of the high-concentration N-type doping (24) is a part of the P well (70), and the width of the part of the P well is B
Preferably, the hysteresis effect characteristic of the ESD device is determined by A, B and the doping concentration of the low-concentration P-type light doping (20), wherein A is 0.1-0.5 um, B is 0.1-0.5 um, and the dosage range of the doping concentration is 1E12-1E15/cm2。
Preferably, a second floating gate (50) is placed over the width B P-well on the left side of the high concentration N-type doping (24) and over the width A N-well on the right side of the low concentration P-type lightly doping (20).
In order to achieve the purpose, the invention also provides a method for realizing the grid-tied silicon controlled rectifier ESD device, which replaces high-concentration P-type doping of a connecting anode of the existing grid-tied silicon controlled rectifier ESD device with low-concentration P-type light doping (20), forms metal silicide (30) on the upper surface of the grid-tied silicon controlled rectifier ESD device, and takes an extraction electrode as the anode of the grid-tied silicon controlled rectifier ESD device.
Preferably, the method comprises:
step 502 of forming an N-well (60) and a P-well (70) in the semiconductor substrate (80);
and 505, connecting a metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) to a connecting power supply, taking the metal silicide (30) leading-out electrode above the low-concentration P-type light doping (20) as an anode of the grid-restrained silicon controlled rectifier ESD device, connecting the metal silicide (30) above the high-concentration N-type doping (24) with the metal silicide (30) above the high-concentration P-type doping (26), and forming a cathode of the grid-restrained silicon controlled rectifier ESD device by the leading-out electrode.
Preferably, the gate-tied scr ESD device is used with the cathode grounded.
Compared with the prior art, the grid-constrained silicon controlled rectifier ESD device and the implementation method thereof replace high-concentration P-type doping of the connecting anode of the existing grid-constrained silicon controlled rectifier ESD device with low-concentration P-type lightly doped region (PLDD), so that the manufacturing process can be simplified while the maintaining voltage of the ESD device is improved, the interface defect caused by the introduction of the Schottky junction is reduced, the contact resistance of the ESD device is reduced, and the grid-constrained silicon controlled rectifier ESD device is more suitable for the anti-static protection design of an integrated circuit of an advanced CMOS process.
Drawings
FIG. 1 is a schematic diagram of a prior art ESD device;
FIG. 2 is a schematic diagram of another prior art ESD device;
FIG. 3 is a schematic diagram of the relationship between hysteresis effect characteristics of a gate-tied SCR and Schottky junction in the prior art;
FIG. 4 is a diagram of a device structure of a preferred embodiment of a gate-tied SCR ESD device according to the present invention;
FIG. 5 is a flowchart illustrating steps of a method for implementing a gate-tied SCR ESD device according to the present invention;
fig. 6 is a schematic view of an application scenario of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 4 is a diagram of a device structure of a gate-tied SCR ESD device according to a preferred embodiment of the present invention. As shown in fig. 4, the ESD device of the gate-tied scr according to the present invention includes: a plurality of Shallow Trench Isolation (STI) layers 10, a high concentration N-type dopant (N +)28, a low concentration P-type light dopant (PLDD)20, a high concentration N-type dopant (N +)24, a high concentration P-type dopant (P +)26, an N-Well 60, a P-Well 70, a P-substrate 80, a first floating gate 40, a second floating gate 50, and a plurality of metal silicides 30 connecting the doped regions and the electrodes.
The entire ESD device is placed on a P-type substrate (P-Sub)80, and two wells are created in the P-type substrate (P-Sub) 80: an N Well (N-Well)60 and a P Well (P-Well)70, wherein the N Well (N-Well)60 is generated on the left side of a P-type substrate (P-Sub)80, the P Well (P-Well)70 is generated on the right side of the P-type substrate (P-Sub)80, the high-concentration N-type doping (N +)28 and the low-concentration P-type lightly doping (PLDD)20 are arranged on the upper portion of the N Well (N-Well)60, the low-concentration P-type lightly doping (PLDD)20, the N Well (N-Well)60 and the P Well (P-Well)70 form an equivalent PNP triode structure, the high-concentration N-type doping (N +)24 and the high-concentration P-type doping (P +)26 are arranged on the upper portion of the P Well (P-Well)70, and the N Well (N-Well)60, the P Well (P-Well)70 and the high-concentration N-type doping (N +)24 form an equivalent PNP triode structure;
shallow Trench Isolation (STI) 10 is disposed on the left side of the high concentration N-type dopant (N +)28, the high concentration N-type dopant (N +)28 and the low concentration P-type lightly doped (PLDD)20 are separated by N-Well (N-Well)60 (i.e., a portion of the space therebetween is 60), a first floating gate 40 is disposed above the portion of N-Well, the right side of the low concentration P-type lightly doped (PLDD)20 is a portion of the N-Well (N-Well)60, the width of the portion of N-Well (N-Well)60 is a, the high concentration N-type dopant (N +)24 and the high concentration P-type dopant (P +)26 are separated by STI, the Shallow Trench Isolation (STI) 10 is disposed on the right side of the high concentration P-type dopant (P +)26, the left side of the high concentration N-type dopant (N +)24 is a portion of the P-Well (P-Well)70, the width of the portion of the P-Well (P-Well)70 is B;
4 metal silicides 30 are generated above the high-concentration N-type doping (N +)28, above the low-concentration P-type light doping (PLDD)20, above the high-concentration N-type doping (N +)24 and above the high-concentration P-type doping (P +)26, and a second floating gate 50 is placed above a P well with the width of B on the left side of the high-concentration N-type doping (N +)24 and above an N well with the width of A on the right side of the low-concentration P-type light doping (PLDD)20, namely the second floating gate 50 is above the boundary of the N well and the P well;
the leading-out electrode of the metal silicide 30 above the high-concentration N-type doping (N +)28 is connected to a power supply Vdd, the leading-out electrode of the metal silicide 30 above the low-concentration P-type light doping (PLDD)20 is used as an Anode Anode of the grid-restrained silicon controlled rectifier ESD device, the metal silicide 30 above the high-concentration N-type doping (N +)24 is connected with the metal silicide 30 above the high-concentration P-type doping (P +)26 and the leading-out electrode forms a Cathode Cathodode of the grid-restrained silicon controlled rectifier ESD device, and the Cathode is grounded Vss when the grid-restrained silicon controlled rectifier ESD device is used.
It can be seen that the present invention replaces the high concentration P-type doping (P +)20 connecting the anode in the prior art gate-tied scr as shown in fig. 1 with the lightly doped low concentration P-type lightly doped region (PLDD)20, and the low concentration P-type lightly doped region (PLDD)20 is used as the emitter of the parasitic PNP (low concentration P-type lightly doped (PLDD) 20/N-Well (N-Well) 60/P-Well (P-Well)70) triode inside the gate-tied scr, and the efficiency of emitting holes is reduced due to the reduction of the P-type doping concentration, which reduces the efficiency of emitting holes in the scrThe current gain (beta) of an internal parasitic PNP (low-concentration P-type lightly doped (PLDD)20/N Well (N-Well)60/P Well (P-Well)70) triode improves the maintaining voltage (Vh) of the silicon controlled rectifier, in addition, because a Schottky junction is not required to be introduced, the manufacturing process is simplified while the maintaining voltage is improved, and the diffusion rate of the low-concentration P-type lightly doped region (PLDD)20 is lower because of lighter doping, so the distance A (playing an electrical isolation role) of the N Well (N-Well)60 containing the low-concentration P-type lightly doped region (PLDD)20 can be shortened, and the layout area is further saved, so the grid-constrained silicon controlled rectifier provided by the invention is more suitable for the anti-static protection design of an integrated circuit in an advanced CMOS process. The device size A, B and the PLDD (20) doping concentration (dosage range 1E12-1E 15/cm) of the gate-confined SCR of the invention2) Together determine their hysteresis response characteristics.
FIG. 5 is a flowchart illustrating steps of a method for implementing a gate-tied SCR ESD device according to the present invention. As shown in fig. 5, the method for implementing an ESD device of a gate-tied scr according to the present invention includes the following steps:
in step 501, a semiconductor substrate is provided, and in the embodiment of the present invention, a P-type substrate (P-Sub)80 is provided.
In step 502, two wells, i.e., N-Well 60 and P-Well 70, are formed in the semiconductor substrate, i.e., N-Well 60 and P-Well 70, in the P-type substrate 80, N-Well 60 and P-Well 70 are formed in the P-type substrate 80, N-Well 60 is formed on the left side of P-type substrate 80, and P-Well 70 is formed on the right side of P-type substrate 80.
In step 503, an equivalent PNP triode structure is formed in the N Well (N-Well)60, and an equivalent NPN triode structure is formed in the P Well 70. Specifically, a high-concentration N-type dopant (N +)28, a low-concentration P-type lightly-doped (PLDD)20 are disposed on the upper portion of an N-Well (N-Well)60, the low-concentration P-type lightly-doped (PLDD)20, the N-Well (N-Well)60, and the P-Well (P-Well)70 constitute an equivalent PNP triode structure, a Shallow Trench Isolation (STI) 10 is disposed on the left side of the high-concentration N-type dopant (N +)28, the high-concentration N-type dopant (N +)28 and the low-concentration P-type lightly-doped (PLDD)20 are separated by the N-Well (N-Well)60 (i.e., a portion of a space 60 therebetween), a first floating gate 40 is disposed above the portion of the N-Well, the right side of the low-concentration P-type lightly-doped (PLDD)20 is a portion of the N-Well (N-Well)60, and the width of the portion of the N-Well (N-Well)60 is a; the high-concentration N-type doping (N +)24 and the high-concentration P-type doping (P +)26 are arranged on the upper portion of a P Well (P-Well)70, the N Well (N-Well)60, the P Well (P-Well)70 and the high-concentration N-type doping (N +)24 form an equivalent NPN triode structure, the high-concentration N-type doping (N +)24 and the high-concentration P-type doping (P +)26 are isolated by a Shallow Trench Isolation layer (STI) 10, the Shallow Trench Isolation layer (STI 10) is arranged on the right side of the high-concentration P-type doping (P +)26, the left side of the high-concentration N-type doping (N +)24 is a portion of the P Well (P-Well)70, and the width of the portion of the P Well (P-Well)70 is B.
505, connecting the leading-out electrode of the metal silicide 30 above the high-concentration N-type doping (N +)28 to a power supply Vdd, using the leading-out electrode of the metal silicide 30 above the low-concentration P-type lightly doping (PLDD)20 as an Anode of the gate-tied scr ESD device, connecting the metal silicide 30 above the high-concentration N-type doping (N +)24 with the metal silicide 30 above the high-concentration P-type doping (P +)26, and leading out an electrode to form a Cathode of the gate-tied scr ESD device, and grounding Vss during use
When in use, in order to protect an IO port, the Cathode Cathaode of the ESD device of the grid-constrained silicon controlled rectifier is grounded Vss, the Vdd end (namely the metal silicide 30 above the high-concentration N-type doping (N +) 28) is connected with a power voltage Vdd, and the Anode Anode is connected with an external IO (input/output end); to protect the power supply, some other ESD protection device may be connected after the gate-tied scr ESD device to obtain the desired characteristics, as shown in fig. 6.
In summary, the gate-tied scr ESD device and the implementation method thereof according to the present invention replace the high-concentration P-type doping of the connection anode of the existing gate-tied scr ESD device with the low-concentration P-type lightly doped region (PLDD), so that the manufacturing process can be simplified while the sustain voltage is increased, the interface defect caused by the introduction of the schottky junction is reduced, the contact resistance is reduced, and the ESD protection device is more suitable for the anti-static protection design of the integrated circuit in the advanced CMOS process.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (9)
1. A gate-tied silicon controlled rectifier (ESD) device, the ESD device comprising:
a semiconductor substrate (80);
an N-well (60) and a P-well (70) formed in the semiconductor substrate (80);
high-concentration N-type doping (28) and low-concentration P-type light doping (20) are arranged on the upper portion of an N well (60), and high-concentration N-type doping (24) and high-concentration P-type doping (26) are arranged on the upper portion of a P well (70);
respectively generating metal silicides (30) above the high-concentration N-type doping (28), above the low-concentration P-type light doping (20), above the high-concentration N-type doping (24) and above the high-concentration P-type doping (26);
and the metal silicide (30) extraction electrode above the high-concentration N-type doping (28) is connected to a connecting power supply, the metal silicide (30) extraction electrode above the low-concentration P-type light doping (20) is used as an anode of the grid-constrained silicon controlled rectifier ESD device, and the metal silicide (30) above the high-concentration N-type doping (24) is connected with the metal silicide (30) above the high-concentration P-type doping (26) and the extraction electrode forms a cathode of the grid-constrained silicon controlled rectifier ESD device.
2. A gate-tied scr ESD device as claimed in claim 1, wherein: the low-concentration P-type lightly doped layer (20), the N-well (60), and the P-well (70) form an equivalent PNP triode structure.
3. A gate-tied scr ESD device as claimed in claim 1, wherein: the N well (60), the P well (70) and the high-concentration N-type doping (24) form an equivalent NPN triode structure.
4. A gate-tied scr ESD device as claimed in claim 1, wherein: a shallow channel isolation layer (10) is arranged on the left side of the high-concentration N-type doping (28), the high-concentration N-type doping (28) and the low-concentration P-type light doping (20) are isolated by the N well (60), a first floating gate (40) is arranged above part of the N well, the right side of the low-concentration P-type light doping (20) is a part of the N well (60), and the width of part of the N well is A.
5. The ESD device of claim 4, wherein: the high-concentration N-type doping (24) and the high-concentration P-type doping (26) are isolated by a shallow channel isolation layer (10), the shallow channel isolation layer (10) is arranged on the right side of the high-concentration P-type doping (26), the left side of the high-concentration N-type doping (24) is a part of the P well (70), and the width of part of the P well is B.
6. A gate-tied SCR ESD device as recited in claim 5, wherein: the hysteresis effect characteristic of the ESD device is determined by A, B and the doping concentration of the low-concentration P-type light doping (20), wherein A is 0.1-0.5 um, B is 0.1-0.5 um, and the dosage range of the doping concentration is 1E12-1E15/cm2。
7. A gate-tied SCR ESD device as recited in claim 5, wherein: and placing a second floating gate (50) above the P well with the width of B on the left side of the high-concentration N-type doping (24) and above the N well with the width of A on the right side of the low-concentration P-type light doping (20).
8. A method for realizing a grid-constrained silicon controlled rectifier ESD device is characterized by comprising the following steps:
step 501, providing a semiconductor substrate (80);
step 502 of forming an N-well (60) and a P-well (70) in the semiconductor substrate (80);
step 503, placing high-concentration N-type doping (28) and low-concentration P-type light doping (20) on the upper part of an N well (60), and placing high-concentration N-type doping (24) and high-concentration P-type doping (26) on the upper part of a P well (70);
step 504, respectively generating metal silicides (30) above the high-concentration N-type doping (28), above the low-concentration P-type light doping (20), above the high-concentration N-type doping (24) and above the high-concentration P-type doping (26);
and 505, connecting a metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) to a connecting power supply, taking the metal silicide (30) leading-out electrode above the low-concentration P-type light doping (20) as an anode of the grid-restrained silicon controlled rectifier ESD device, connecting the metal silicide (30) above the high-concentration N-type doping (24) with the metal silicide (30) above the high-concentration P-type doping (26), and forming a cathode of the grid-restrained silicon controlled rectifier ESD device by the leading-out electrode.
9. The method of claim 8, wherein the ESD device comprises: and when the grid constraint silicon controlled rectifier ESD device is used, the cathode is grounded.
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| CN104704636A (en) * | 2012-11-02 | 2015-06-10 | 德州仪器公司 | ESD protection circuit with isolated SCR for negative voltage operation |
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| CN101667600A (en) * | 2009-09-09 | 2010-03-10 | 上海宏力半导体制造有限公司 | Schottky diode structure |
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