TWI506776B - Semiconductor device and manufacturing method of the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having low substrate leakage and a method of fabricating the same.

With the development of semiconductor technology, various semiconductor components continue to evolve. For example, components such as memory, transistors, and diodes have been widely used in various electronic devices.

In the development of semiconductor technology, researchers are constantly trying to improve on various components, such as reducing the size, increasing/decreasing the startup voltage, increasing/decreasing the breakdown voltage, reducing leakage, and electrostatic protection.

The disclosure relates to a semiconductor device and a method of fabricating the same. In an embodiment, the semiconductor device includes a thyristor, and a base of the equivalent NPN transistor of the thyristor is electrically connected to the collector (corresponding to the base of the equivalent PNP transistor) via a resistive element, so that the two There is a voltage difference between them, so that the unnecessary current can be directed to the collector of the equivalent NPN transistor, thereby reducing the substrate leakage of the semiconductor device and also improving the electrostatic discharge (ESD) protection effect.

According to an embodiment of the present disclosure, a semiconductor device is proposed. The semiconductor device includes a substrate, a first doping region, a first well, a first heavily doped region, a second heavily doped region, and a third weight. a doped region and a resistive element. The first doping region is disposed on the substrate, and the first well is disposed in the first doping region. The first heavily doped region is disposed within the first well. The second heavily doped region is disposed in the first well, and the second heavily doped region is spaced apart from the first heavily doped region. The third heavily doped region is disposed in the first doped region, and the second heavily doped region is electrically connected to the third heavily doped region via the resistive element. The substrate, the first well and the second heavily doped region have a first doping type, and the first doping region, the first heavily doped region and the third heavily doped region have a second doping type, A doped form is complementary to the second doped type.

In accordance with another embodiment of the present disclosure, a semiconductor device is presented. The semiconductor device includes a thyristor and a resistive element. The thyristor has an equivalent NPN transistor and an equivalent PNP transistor. The base of the equivalent NPN transistor is electrically connected to the base of the equivalent PNP transistor via a resistive element.

According to still another embodiment of the present disclosure, a method of fabricating a semiconductor device is proposed. A method of manufacturing a semiconductor device includes the following steps. Providing a substrate; forming a first doped region on the substrate; forming a first well in the first doping region; forming a first heavily doped region in the first well; forming a second heavily doped region In the first well, the second heavily doped region is separated from the first heavily doped region; a third heavily doped region is formed in the first doped region; and a resistive element is formed, the second heavily doped The inter-cell is electrically connected to the third heavily doped region via the resistive element. The substrate, the first well and the second heavily doped region have a first doping type, and the first doping region, the first heavily doped region and the third heavily doped region have a second doping type, A doped form is complementary to the second doped type.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100, 200, 300, 400‧‧‧ semiconductor devices
110P‧‧‧Substrate
120‧‧‧ epitaxial layer
121P‧‧‧First Well
123P‧‧‧Second well
125N‧‧‧ third well
130N, 230N‧‧‧ first doped area
141N‧‧‧First heavily doped area
143P‧‧‧Second heavily doped area
145N‧‧‧ third heavily doped area
147P‧‧‧4th heavily doped area
150‧‧‧resistive components
160,161‧‧‧ field oxide layer
171‧‧‧First electrode
172‧‧‧second electrode
173‧‧‧ third electrode
181, 183‧‧‧ equivalent NPN transistor
231N‧‧‧ buried layer
I, II‧‧‧ Curve
ML1, ML2‧‧‧ metal layer
Vanode‧‧‧Anode voltage

Fig. 1 is a cross-sectional view showing the semiconductor device of the first embodiment.

2A to 2D are flowcharts showing a method of manufacturing the semiconductor device of the first embodiment.
Fig. 3 is a cross-sectional view showing the semiconductor device of the second embodiment.
4A to 4F are flowcharts showing a method of manufacturing the semiconductor device of the second embodiment.
Fig. 5 is a cross-sectional view showing the semiconductor device of the third embodiment.
Fig. 6 is a cross-sectional view showing the semiconductor device of the fourth embodiment.
FIG. 7 is a schematic view showing an equivalent transistor of the semiconductor device of the second embodiment.
FIG. 8 is an equivalent circuit diagram of a semiconductor device in accordance with some embodiments of the present disclosure.
Fig. 9 is a view showing an IV chart of the semiconductor device of the second embodiment.

In an embodiment of the disclosure, a semiconductor device and a method of fabricating the same are provided. In an embodiment, the semiconductor device includes a thyristor, and a base of the equivalent NPN transistor of the thyristor is electrically connected to the collector (corresponding to the base of the equivalent PNP transistor) via a resistive element, so that the two There is a voltage difference between them, so that the unnecessary current can be directed to the collector of the equivalent NPN transistor, thereby reducing the substrate leakage of the semiconductor device and also improving the electrostatic discharge protection effect. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments are omitted in order to clearly show the technical features of the present invention.

First embodiment

Referring to FIG. 1, a cross-sectional view of a semiconductor device 100 of a first embodiment is shown. The semiconductor device 100 includes a substrate 110P, a first doping region 130N, a first well 121P, a first heavily doped region 141N, a second heavily doped region 143P, and a third weight. Doped region 145N and resistive element 150.

The material of the substrate 110P is, for example, a P-type N or an N-type 矽. The first doping region 130N is disposed on the substrate 110P, and the first well 121P is disposed in the first doping region 130N. The first doping region 130N and the first well 121P are, for example, a P-type well or a N-type well, and the first doping region 130N may also be, for example, a N-type deep well (deep N type well). The first well 121P may also be, for example, a P-type well/P-type heavily doped buried layer (P+ buried layer) stacked layer, a P-type heavily doped layer (P+ implant layer), an N-type well/N-type heavily doped buried Layer (N+ buried layer) stacked layer, N-type implanted layer (N+ implant layer) or N-type deep well.

The first heavily doped region 141N is disposed in the first well 121P, the second heavily doped region 143P is disposed in the first well 121P, and the second heavily doped region 143P is spaced apart from the first heavily doped region 141N. The third heavily doped region 145N is disposed within the first doped region 130N. The doping concentrations of the first heavily doped region 141N, the second heavily doped region 143P, and the third heavily doped region 145N are greater than the doping concentrations of the first well 121P and the first doped region 130N to provide good ohmic contact. (Ohmic contact). The first heavily doped region 141N, the second heavily doped region 143P, and the third heavily doped region 145N are, for example, a P type heavily doping region (P+) or an N type heavily doped region (N type). Heavy doping region, N+).

The second heavily doped region 143P is electrically connected to the third heavily doped region 145N via the resistive element 150. The resistive element 150 is, for example, a polysilicon layer.

The substrate 110P, the first well 121P and the second heavily doped region 143P have a first doping type (for example, P-type or N-type), a first doping region 130N, a first heavily doped region 141N, and a third The heavily doped region 145N has a second doping profile (eg, N-type or P-type), and the first doped profile is complementary to the second doped profile. In this embodiment, the first doping type is a P type, and the second doping type is an N type.

As shown in FIG. 1 , in the embodiment, the semiconductor device 100 further includes a field oxide layer (FOX) 161 disposed on the first well 121P and located in the first heavily doped region 141N and The second heavily doped regions 143P are spaced apart from each other. In addition, in the semiconductor device 100 of the embodiment, the field oxide layer 160 may be further disposed, and the field oxide layer 160 may be disposed on the adjacent portion of the first well 121P and the first doping region 130N. The material of the field oxide layers 160 and 161 is, for example, cerium oxide (SiO ₂ ), and its structure is, for example, a region yttrium oxide (LOCOS) as shown in FIG. 1 or a shallow trench isolation (STI).

In an embodiment, the resistive element 150 may be disposed in the internal structure of the semiconductor device 100 or in an external structure. In the present embodiment, as shown in FIG. 1, a polysilicon layer (resistive element 150) is disposed on the field oxide layer 161 over the first well 121P, and the resistive element 150 is disposed on the semiconductor device 100 as compared to the external structure. In the internal structure, the size of the overall structure can be effectively reduced.

In an embodiment, as shown in FIG. 1, the semiconductor device 100 may further include a second well 123P. The second well 123P is disposed on the substrate 110P. The first doping region 130N is disposed between the first well 121P and the second well 123P, and the second well 123P has a first doping type.

In an embodiment, as shown in FIG. 1, the semiconductor device 100 further includes a fourth heavily doped region 147P. The fourth heavily doped region 147P is disposed in the second well 123P, and the fourth heavily doped region 147P has a first doping profile.

As shown in FIG. 1, the paths of the first electrode 171, the first heavily doped region 141N, the first well 121P, the second heavily doped region 143P, the resistive element 150, and the second electrode 172 form an insulating transistor (isolation) Diode). In the forward bias, there will be at least 0.7 volts (V) of impedance; in the reverse bias, there will be at least 30 volts of impedance.

In addition, the first heavily doped region 141N is electrically connected to the first electrode 171, and the second heavily doped region 143P is electrically connected to the second electrode 172 via the resistive element 150. The second electrode 172 is electrically connected to the second electrode 172 at the same time. The triple doped region 145N is electrically connected to the fourth heavily doped region 147P to the third electrode 173. The first electrode 171 is, for example, a cathode, the second electrode 172 is, for example, an anode, and the third electrode 173 is, for example, a ground terminal. Due to the resistive element 150, there is a voltage difference between the first doped region 130N where the third heavily doped region 145N is located and the first well 121P, such that in the forward bias, the potential of the first doped region 130N is higher than The potential of the first well 121P can guide the unnecessary current to the second electrode 172, thereby reducing the substrate leakage and improving the electrostatic discharge (ESD) protection effect. The detailed mechanism of action will be discussed in the following paragraphs of this paper.

In addition, the configuration of the polysilicon layer (resistive element 150), in addition to the effect of reducing substrate leakage and improving electrostatic discharge protection as described herein, can also improve the insulating transistor due to the effect of the field effect electric plate on the polycrystalline germanium layer. Crash voltage.

Referring to FIGS. 2A-2D, a flow chart of a method of fabricating the semiconductor device 100 of the first embodiment is shown. First, as shown in FIG. 2A, a substrate 110P is provided.

Next, as shown in FIG. 2B, a first doping region 130N is formed on the substrate 110P, and a first well 121P is formed in the first doping region 130N. In the embodiment, the second well 123P is formed on the substrate 110P, and the first doping region 130N is formed between the first well 121P and the second well 123P. In the embodiment, the first doping region 130N, the first well 121P, and the second well 123P are fabricated, for example, in a triple well process, and the manufacturing cost can be reduced without adding an additional epitaxial step.

Next, as shown in FIG. 2C, the field oxide layer 161 is formed on the first well 121P and located between the first heavily doped region 141N and the second heavily doped region 143P, and the field oxide layer 160 may be formed first. The well 121P and the first doping region 130N are adjacent to each other.

Then, as shown in FIG. 2C, the first heavily doped region 141N and the second heavily doped region 143P are formed in the first well 121P, and the second heavily doped region 143P is spaced apart from the first heavily doped region 141N. Forming a third heavily doped region 145N within the first doped region 130N. In an embodiment, a fourth heavily doped region 147P may also be formed in the second well 123P.

Next, as shown in FIG. 2D, the resistive element 150 is formed on the field oxide layer 161. In another embodiment, the resistive element 150 may be formed on the field oxide layer 161 before the heavily doped regions 141N, 143P, 145N, and 147P are formed. In an embodiment, the resistive element 150 is formed, for example, from a polysilicon layer. Through the above steps, the semiconductor device 100 of the present embodiment can be successfully completed.

Second embodiment

Referring to FIG. 3, a cross-sectional view of the semiconductor device 200 of the second embodiment is shown. The semiconductor device 200 of the present embodiment is different from the semiconductor device 100 of the first embodiment in the design of the first doping region 230N, and the rest of the same is not repeated.

As shown in FIG. 3, the first doping region 230N includes a buried layer 231N and a third well 125N. In an embodiment, the doping concentration of the buried layer 231N is greater than the doping concentration of the third well 125N. The buried layer 231N is disposed below the first well 121P, the third well 125N is disposed on the buried layer 231N, and the third well 125N is disposed between the first well 121P and the second well 123P. The materials of the buried layer 231N and the third well 125N of the present embodiment are substantially the same. In this embodiment, the buried layer 231N is, for example, an N type buried layer (NBL), an N type epitaxial layer (N-epi), an N type deep well (deep N type well), or an N type. Doped stacked layers (multiple N+ stacked layers).

Referring to FIGS. 4A-4F, a flow chart of a method of fabricating the semiconductor device 200 of the second embodiment is shown. First, as shown in Fig. 4A, a substrate 110P is provided.

Then, as shown in FIG. 4B, a buried layer 231N is formed on the substrate 110P. In the embodiment, the buried layer 231N is formed below the first well 121P that is to be formed.

Then, as shown in FIG. 4C, an epitaxial layer 120 is formed on the substrate 110P and the buried layer 231N.

Next, as shown in FIG. 4D, the first well 121P and the third well 125N are formed on the buried layer 231N, and the buried layer 231N and the third well 125N form the first doping region 230N. In the embodiment, the second well 123P is formed on the substrate 110P, and the third well 125N is formed between the first well 121P and the second well 123P. In an embodiment, the first well 121P and the second well 123P are fabricated, for example, in a twin well process without the need for additional reticle or steps.

Next, as shown in FIG. 4E, the field oxide layer 161 is formed on the first well 121P and located between the first heavily doped region 141N and the second heavily doped region 143P, and the field oxide layer 160 may be formed first. The well 121P and the first doped region 230N (the third well 125N) are adjacent to each other.

Then, as shown in FIG. 4E, the first heavily doped region 141N and the second heavily doped region 143P are formed in the first well 121P, and the second heavily doped region 143P is spaced apart from the first heavily doped region 141N. The third heavily doped region 145N is formed in the first doped region 230N. In an embodiment, a fourth heavily doped region 147P may also be formed in the second well 123P.

Next, as shown in FIG. 4F, the resistive element 150 is formed on the field oxide layer 161. In an embodiment, the resistive element 150 is formed, for example, from a polysilicon layer. Through the above steps, the semiconductor device 200 of the present embodiment can be successfully completed.

Third embodiment

Referring to FIG. 5, a cross-sectional view of the semiconductor device 300 of the third embodiment is shown. The semiconductor device 300 of the present embodiment is different from the semiconductor device 100 of the first embodiment in the configuration of the resistive element 150, and the rest of the same is not repeated.

In the embodiment, as shown in FIG. 5, the polysilicon layer (resistive element 150) is disposed on the first well 121P and located between the first heavily doped region 141N and the second heavily doped region 143P. They are spaced apart.

The method of manufacturing the semiconductor device 300 of the present embodiment differs from the semiconductor device 100 of the first embodiment mainly in that the field oxide layer 161 as shown in FIG. 1 is not formed. In other words, in the manufacturing process of the semiconductor device 300, the field oxide layer 160 is formed, and the resistive element 150 is formed on the first well 121P, and the resistive element 150 is located in the first heavily doped region 141N which is formed and the second weight which is predetermined to be formed. Between the doped regions 143P, each heavily doped region is then formed. The first formed resistive element 150 may have an effect similar to a field oxide layer (for example, the field oxide layer 161 as shown in FIG. 1), and each of the heavily doped layers may be formed according to the arrangement positions of the field oxide layer 160 and the resistive element 150. Area. The rest of the manufacturing method of the present embodiment and the manufacturing method of the first embodiment will not be repeatedly described.

Fourth embodiment

Referring to FIG. 6, a cross-sectional view of a semiconductor device 400 of a fourth embodiment is shown. The semiconductor device 400 of the present embodiment is different from the semiconductor device 200 of the second embodiment in the configuration of the resistive element 150, and the rest of the same is not repeated.

In the embodiment, as shown in FIG. 6, the polysilicon layer (resistive element 150) is disposed on the first well 121P and located between the first heavily doped region 141N and the second heavily doped region 143P. They are spaced apart.

The manufacturing method of the semiconductor device 400 of the present embodiment is mainly different from the semiconductor device 200 of the first embodiment in that the field oxide layer 161 as shown in FIG. 2 is not formed. In other words, in the manufacturing process of the semiconductor device 400, the field oxide layer 160 is formed, and the resistive element 150 is formed on the first well 121P, and the resistive element 150 is located in the first heavily doped region 141N which is formed and the second weight which is to be formed. Between the doped regions 143P, each heavily doped region is then formed. The first formed resistive element 150 may have an effect similar to a field oxide layer (for example, the field oxide layer 161 as shown in FIG. 2), and each of the heavily doped layers may be formed according to the arrangement positions of the field oxide layer 160 and the resistive element 150. Area. The rest of the manufacturing method of the present embodiment and the manufacturing method of the second embodiment will not be repeatedly described.

Hereinafter, the electrical characteristics of the structure of the present disclosure will be described by taking the semiconductor device 200 as an example. However, the electrical characteristics described above are not limited to the semiconductor device 200, and the semiconductor device 100 to the semiconductor device 400 and structural modifications and retouchings are possible without departing from the spirit and scope of the present invention.

Referring to FIG. 7, a schematic diagram of an equivalent transistor of the semiconductor device 200 of the second embodiment is shown. As shown in FIG. 7, the substrate 110P, the first doping region 230N, the first well 121P, and the first heavily doped region 141N form a thyristor having an equivalent NPN transistor (for example, Equivalent NPN transistors 181, 183) and an equivalent PNP transistor (eg, equivalent NPN transistors 185, 187). The equivalent NPN transistor is formed, for example, by the first doping region 230N, the first well 121P, and the first heavily doped region 141N, and the equivalent PNP transistor is formed, for example, by the substrate 110P, the first doping region 230N, and the first well 121P. . The base of the equivalent NPN transistor (eg, the second heavily doped region 143P) is electrically coupled to the base of the equivalent PNP transistor (eg, the third heavily doped region 145N) via the resistive element 150. In the thyristor, the base of the equivalent PNP transistor is also the collector of an equivalent NPN transistor.

As shown in FIG. 7, the resistive element 150 is disposed on the field oxide layer 161, and the first doped region 230N (eg, the third well 125N and/or the buried layer 231N) passes through the metal layer ML2, the resistive element 150, and the metal layer ML1. Electrically connected to the first well 121P, the resistive element 150 is such that the first well 121P (eg, the base of the equivalent NPN transistor 181, 183) and the first doped region 230N (eg, an equivalent NPN transistor 181, 183) A voltage difference is generated between the collectors, and the potential of the first doping region 230N is higher than the potential of the first well 121P, so that the first well 121P (for example, the base of the equivalent NPN transistors 181, 183) Forming a depletion region between the first doped region 230N (for example, the collector of the equivalent NPN transistors 181, 183) facilitates the flow of current, thereby facilitating an equivalent NPN transistor (eg, equivalent NPN) The operation of crystal 181 and equivalent NPN transistor 183). In this way, based on the operation of the equivalent NPN transistor, the current is driven to flow through the first doping region 230N through the metal layer ML2 to the second electrode 172 end (eg, the collector terminal of the equivalent NPN transistor 181, 183). The current can be reduced to flow through the second well 123P and/or the substrate 110P to the third electrode 173 end, thereby reducing the leakage of the substrate and improving the overall electrostatic discharge protection effect.

Please refer to FIG. 8 , which illustrates an equivalent circuit diagram of a semiconductor device in accordance with some embodiments of the present disclosure. As shown in FIG. 8, the resistive element 150 causes a voltage difference between the base and the collector of the NPN equivalent transistor, thereby achieving the effect of reducing substrate leakage.

Please refer to FIG. 9 , which is a graph showing the IV of the semiconductor device 200 of the second embodiment, wherein the curve I represents the relationship between the substrate leakage of the conventional insulated transistor and the applied anode voltage Vanode, and the curve II represents The relationship between the substrate leakage of the semiconductor device 200 with respect to the anode voltage Vanode applied to the second electrode 172. In the embodiment, the third electrode 173 as shown in FIG. 7 is, for example, a test electrode, and the current value of the substrate leakage is measured by the third electrode 173. As shown in Figure 9, when the anode voltage Vanode rises from 5 volts to more than about 6.2 volts, the substrate leakage shown by curve I has reached the milliamperes (mA) level, while the substrate leakage shown by curve II is still The microampere (μA) level, which differs by two orders or more. In other words, the semiconductor device of the embodiment of the present disclosure can effectively reduce the substrate leakage of the insulating transistor.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor device

110P‧‧‧Substrate

121P‧‧‧First Well

123P‧‧‧Second well

130N‧‧‧First doped area

141N‧‧‧First heavily doped area

143P‧‧‧Second heavily doped area

145N‧‧‧ third heavily doped area

147P‧‧‧4th heavily doped area

150‧‧‧resistive components

160,161‧‧‧ field oxide layer

171‧‧‧First electrode

172‧‧‧second electrode

173‧‧‧ third electrode

ML1, ML2‧‧‧ metal layer

Claims (18)

A semiconductor device comprising:
a substrate;
a first doping region disposed on the substrate;
a first well disposed in the first doping region;
a first heavily doping region disposed in the first well;
a second heavily doped region disposed in the first well, the second heavily doped region being spaced apart from the first heavily doped region;
a third heavily doped region is disposed in the first doped region; and a resistive element, the second heavily doped region is electrically connected to the third heavily doped region via the resistive element;
The substrate, the first well and the second heavily doped region have a first doping type, and the first doping region, the first heavily doped region and the third heavily doped region have a first A two-doping type, the first doping profile being complementary to the second doping profile. The semiconductor device of claim 1, further comprising a second well disposed on the substrate, wherein the first doped region is disposed between the first well and the second well, the second The well has the first doping profile. The semiconductor device of claim 2, further comprising a fourth heavily doped region disposed in the second well, the fourth heavily doped region having the first doped type. The semiconductor device of claim 1, wherein the resistive element is a polysilicon layer. The semiconductor device of claim 4, wherein the polysilicon layer is disposed on the first well and between the first heavily doped region and the second heavily doped region. The semiconductor device of claim 1, further comprising a field oxide (FOX) disposed on the first well and located in the first heavily doped region and the second heavily doped Between the miscellaneous areas. The semiconductor device according to claim 6, wherein the resistive element is a polysilicon layer, and the polysilicon layer is disposed on the field oxide layer. The semiconductor device of claim 1, wherein the first doped region comprises:
a buried layer disposed below the first well; and a third well disposed on the buried layer, wherein the third well is disposed between the first well and the second well. A semiconductor device comprising:
a thyristor having an equivalent NPN transistor and an equivalent PNP transistor; and a resistive element, the base of the equivalent NPN transistor being electrically connected to the equivalent PNP transistor via the resistive element The base. The semiconductor device of claim 9, wherein the thyristor comprises:
a substrate;
a first doped region disposed on the substrate;
a first well disposed in the first doping region; and a first heavily doped region disposed in the first well;
Wherein the substrate and the first well have a first doping profile, the first doped region and the first heavily doped region have a second doping profile, the first doping profile being complementary to the The second doping type. A method of fabricating a semiconductor device, comprising:
Providing a substrate;
Forming a first doped region on the substrate;
Forming a first well in the first doping region;
Forming a first heavily doped region in the first well;
Forming a second heavily doped region in the first well, the second heavily doped region being spaced apart from the first heavily doped region;
Forming a third heavily doped region in the first doped region; and forming a resistive element, the second heavily doped region being electrically connected to the third heavily doped region via the resistive element;
The substrate, the first well and the second heavily doped region have a first doping type, and the first doping region, the first heavily doped region and the third heavily doped region have a first A two-doping type, the first doping profile being complementary to the second doping profile. The method for manufacturing a semiconductor device according to claim 11, further comprising:
Forming a second well on the substrate, wherein the first doped region is formed between the first well and the second well, the second well having the first doping profile. The method for manufacturing a semiconductor device according to claim 12, further comprising:
Forming a fourth heavily doped region in the second well, the fourth heavily doped region having the first doped profile. The method of fabricating a semiconductor device according to claim 11, wherein the resistive element is a polysilicon layer. The method of manufacturing a semiconductor device according to claim 14, wherein the step of forming the resistive element comprises:
The polysilicon layer is formed on the first well and between the first heavily doped region and the second heavily doped region. The method for manufacturing a semiconductor device according to claim 14, further comprising:
An oxide layer is formed on the first well and between the first heavily doped region and the second heavily doped region. The method of manufacturing a semiconductor device according to claim 16, wherein the step of forming the resistive element comprises:
The polysilicon layer is formed on the field oxide layer. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the first doped region on the substrate comprises:
Forming a buried layer below the first well; and forming a third well on the buried layer, wherein the third well is formed between the first well and the second well.