CN110518011B - Grid-constrained silicon controlled rectifier ESD device and implementation method thereof - Google Patents
Grid-constrained silicon controlled rectifier ESD device and implementation method thereof Download PDFInfo
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- CN110518011B CN110518011B CN201910809013.6A CN201910809013A CN110518011B CN 110518011 B CN110518011 B CN 110518011B CN 201910809013 A CN201910809013 A CN 201910809013A CN 110518011 B CN110518011 B CN 110518011B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Abstract
The invention discloses a gate-constrained silicon controlled rectifier ESD device and a realization method thereof, wherein a Schottky junction of the existing gate-constrained silicon controlled rectifier ESD device is removed, a low-concentration P-type light doping (22) is inserted between a high-concentration N-type doping (24) and a second floating gate (50), a metal silicide is formed on the upper surface of the low-concentration P-type light doping (22), and the metal silicide and the high-concentration N-type doping (24) are connected to a cathode of the gate-constrained silicon controlled rectifier ESD device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit technology, and in particular, to a novel gate-tied silicon controlled rectifier (ESD) device and an implementation method thereof.
Background
In the field of esd protection design of integrated circuits, an esd protection design window generally depends on a working voltage and a Gate oxide thickness of an internal protected circuit, and for example, the working voltage of an integrated circuit in an advanced CMOS process is about 1V, and the Gate oxide thickness is about 14A (angstroms, 0.1nm), the esd protection design window of the integrated circuit in the advanced CMOS process is generally between 1.2V and 2.8V, and a trigger voltage (Vt1) of a hysteresis effect of a typical GGNMOS (group-Gate NMOS) esd protection device in the advanced CMOS process is generally greater than 2.8V, so the industry first proposed a Gate-constrained silicon controlled rectifier as shown in fig. 1 to solve the problem.
As shown in fig. 1, the conventional gate-tied scr ESD device includes a plurality of Shallow Trench Isolation (STI) layers 10, high-concentration N-type dopants (N +)28, high-concentration P-type dopants (P +)20, high-concentration N-type dopants (N +)24, high-concentration P-type dopants (P +)26, N-wells (N-Well)60, P-wells (P-Well)70, P-type substrates (P-Sub)80, a first floating gate 40, a second gate 50, and a plurality of metal silicides (Silicide)30 connecting doped regions and electrodes.
The whole ESD device is arranged on a P-type substrate (P-Sub)80, an N-Well (N-Well)60 is generated on the left side of the P-type substrate (P-Sub)80, a P-Well (P-Well)70 is generated on the right side of the P-type substrate (P-Sub)80, high-concentration N-type doping (N +)28 and high-concentration P-type doping (P +)20 are arranged on the upper portion of the N-Well (N-Well)60, high-concentration P-type doping (P +)20, the N-Well (N-Well)60 and the P-Well (P-Well)70 form an equivalent PNP triode structure, high-concentration N-type doping (N +)24 and high-concentration P-type doping (P +)26 are arranged on the upper portion of the P-Well (P-Well)70, and the N-Well (N-Well)60, the P-Well (P-Well)70 and the high-concentration N-type doping (N +)24 form an equivalent NPN triode structure;
shallow channel Isolation layer (STI) 10 is placed on the left side of high concentration N-type doping (N +)28, N-Well 60 (i.e. a part of interval 60 between N-Well and P-Well) 20 of high concentration N-type doping (N +)28 and P-Well) 20, first floating gate 40 is placed above the N-Well of the part, the right side of high concentration P-type doping (P +)20 is a part of N-Well 60, the width of N-Well 60 of the part is A, Shallow channel Isolation layer (STI, Shallow channel Isolation layer) 10 is placed on the right side of high concentration P-type doping (P +)26, high concentration N-type doping (N +)24 and high concentration P-type doping (P +)26 are separated by Shallow channel Isolation layer (STI, Shallow channel Isolation layer) 10 is placed on the left side of high concentration N-type doping (N +)24, and P-Well 70 is placed on the left side of high concentration N-type doping (N +)24, the width of the portion of the P-Well (P-Well)70 is B;
4 metal silicides 30 are generated above the high-concentration N-type doping (N +)28, above the high-concentration P-type doping (P +)20, above the high-concentration N-type doping (N +)24 and above the high-concentration P-type doping (P +)26, and a second grid 50 is arranged above a P well with the width of B on the left side of the high-concentration N-type doping (N +)24 and above an N well with the width of A on the right side of the high-concentration P-type doping (P +)20, namely the second grid 50 is arranged above the boundary of the N well and the P well and does not cover the high-concentration P-type doping (P +)20 and the high-concentration N-type doping (N +) 24;
the leading-out electrode of the metal silicide 30 above the high-concentration N-type doping (N +)28 is connected to a power supply Vdd, the leading-out electrode of the metal silicide 30 above the high-concentration P-type doping (P +)20 is used as an Anode Anode of the novel grid-constraint silicon controlled rectifier ESD device, the second grid 50 is connected with the metal silicide 30 above the high-concentration N-type doping (N +)24 and the metal silicide 30 above the high-concentration P-type doping (P +)26 and is led out to form a Cathode Cathode of the conventional grid-constraint silicon controlled rectifier ESD device, and the Cathode is grounded Vss when the grid-constraint silicon controlled rectifier ESD device is used.
The measurement results show that the maintaining voltage (Vh) is too low, and is only about 1.2V.
At present, the industry also proposes an improved Schottky Junction embedded scr as shown in fig. 2 to raise the sustain voltage (Vh) based on the gate-tied scr as shown in fig. 1, i.e. a metal layer 22 is formed directly above a P-Well (P-Well)70 on the left side of a high concentration N-type dopant (N +)24 to form a Schottky Junction (Schottky Junction), and a second gate (floating gate) 50 is formed above a P-Well (P-Well)70 with a width of B-S on the left side of the metal layer 22 and above an N-Well (N-Well)60 with a width of a on the right side of the high concentration P-type dopant (P +) 20.
The hysteresis effect characteristics of the gate-tied scr as shown in fig. 1 and the improved gate-tied scr as shown in fig. 2 are shown in fig. 3, the left side is the characteristic curve of fig. 1, the right side is the characteristic curve of fig. 2, and it can be obtained from fig. 3 that the improved gate-tied scr with embedded schottky junction as shown in fig. 2 can raise the holding voltage of the hysteresis effect from 1.2V to 2V, and the trigger voltage is controlled at 2.4V and still lower than 2.8V, so the gate-tied scr with embedded schottky junction as shown in fig. 2 is more suitable for the anti-static protection design of the advanced CMOS process integrated circuit, but the introduction of the schottky junction in the improved gate-tied scr leads to a more complicated process, and in addition, interface defects are easily introduced at the metal-semiconductor contact interface, and the contact resistance of the schottky junction is higher.
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a gate-tied scr ESD device and a method for implementing the same, so as to improve the holding voltage, simplify the manufacturing process, reduce the interface defect caused by the introduction of the schottky junction, and reduce the contact resistance.
To achieve the above and other objects, the present invention provides a gate-tied scr ESD device, comprising:
a semiconductor substrate (80);
an N-well (60) and a P-well (70) formed in the semiconductor substrate (80);
a high-concentration N-type doping (28) and a high-concentration P-type doping (20) are arranged at the upper part of the N well (60), a low-concentration P-type light doping (22) and a high-concentration N-type doping (24) are arranged at the upper part of the P well (70), the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) are isolated by the P well (70), and a second floating gate (50) is arranged above the upper part of the left side of the low-concentration P-type light doping (22), the upper part of the P well (70) with the width of B at the left side and the upper part of the N well (60) with the width of A at the right side of the high-concentration P-type doping (20);
respectively generating metal silicides (30) above the high-concentration N-type doping (28), the high-concentration P-type doping (20), the part above the low-concentration P-type light doping (22) and the high-concentration N-type doping (24);
and the metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) is connected to a connecting power supply, the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) is used as an anode of the grid-constrained silicon controlled rectifier ESD device, and the metal silicide (30) above the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) are connected and lead-out electrode to form a cathode of the grid-constrained silicon controlled rectifier ESD device.
Preferably, the width of the portion of the P-well (70) between the low concentration P-type light doping (22) and the high concentration N-type doping (24) is S2, and an N-type gate (90) is disposed above the portion of the P-well (70).
Preferably, the high concentration P-type doping (20), the N-well (60), and the P-well (70) constitute an equivalent PNP triode structure.
Preferably, the N well (60), the P well (70) and the high-concentration N-type doping (24) form an equivalent NPN triode structure.
Preferably, a shallow channel isolation layer (10) is arranged on the left side of the high-concentration N-type doping (28), the high-concentration N-type doping (28) and the high-concentration P-type doping (20) are isolated by the N well (60), and a first floating gate (40) is placed above the part of the N well.
Preferably, the hysteresis effect characteristic of the ESD device is determined by A, B, S2 and the width S1 of the low-concentration P-type light doping (22), wherein A is 0.1-0.5 um, B is 0.1-0.5 um, S1 is 0.05-1 um, and S2 is 0.1-5 um.
In order to achieve the above object, the present invention further provides a method for implementing a gate-tied scr ESD device, in which a schottky junction of an existing gate-tied scr ESD device is removed, a low-concentration P-type lightly doped layer (22) is inserted between a high-concentration N-type doped layer (24) and a second floating gate (50), and a metal silicide is formed on an upper surface of the low-concentration P-type lightly doped layer (22) and is connected to a cathode of the gate-tied scr ESD device together with the high-concentration N-type doped layer (24).
Preferably, the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) are isolated by a P well (70), and an N-type grid (90) is arranged above the P well (70).
Preferably, the method comprises:
step 502 of forming an N-well (60) and a P-well (70) in the semiconductor substrate (80);
and 505, connecting a metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) to a connecting power supply, taking the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) as an anode of the grid-restrained silicon controlled rectifier ESD device, and connecting the metal silicide (30) above the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) and leading-out electrode to form a cathode of the grid-restrained silicon controlled rectifier ESD device.
Preferably, the width of the portion of the P-well (70) between the low concentration P-type light doping (22) and the high concentration N-type doping (24) is S2, and the N-type gate (90) is disposed above the portion of the P-well (70).
Compared with the prior art, the gate-constrained silicon controlled rectifier ESD device and the implementation method thereof remove the Schottky junction of the existing gate-constrained silicon controlled rectifier ESD device, and insert the low-concentration P-type light doping (PLDD) between the high-concentration N-type doping (24) and the second floating gate (50), so that the manufacturing process can be simplified while the maintenance voltage of the ESD device is improved, the interface defect caused by the introduction of the Schottky junction is reduced, the contact resistance of the ESD device is reduced, and the ESD device is more suitable for the anti-static protection design of an advanced CMOS process integrated circuit.
Drawings
FIG. 1 is a schematic diagram of a prior art ESD device;
FIG. 2 is a schematic diagram of another prior art ESD device;
FIG. 3 is a schematic diagram of the relationship between hysteresis effect characteristics of a gate-tied SCR and Schottky junction in the prior art;
FIG. 4 is a diagram of a device structure of a preferred embodiment of a gate-tied SCR ESD device according to the present invention;
FIG. 5 is a flowchart illustrating steps of a method for implementing a gate-tied SCR ESD device according to the present invention;
fig. 6 is a schematic view of an application scenario of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 4 is a diagram of a device structure of a gate-tied SCR ESD device according to a preferred embodiment of the present invention. As shown in fig. 4, the ESD device of the gate-tied scr according to the present invention includes: a plurality of Shallow Trench Isolation (STI) layers 10, a high concentration N-type dopant (N +)28, a high concentration P-type dopant (P +)20, a low concentration P-type light dopant (PLDD)22, a high concentration N-type dopant (N +)24, an N-Well 60, a P-Well 70, a P-substrate 80, a first floating gate 40, a second floating gate 50, an N-gate 90, and a plurality of metal silicides 30 connecting the doped regions and the electrodes.
The entire ESD device is placed on a P-type substrate (P-Sub)80, and two wells are created in the P-type substrate (P-Sub) 80: the N-Well (N-Well)60 and the P-Well (P-Well)70, wherein the N-Well (N-Well)60 is generated on the left side of a P-type substrate (P-Sub)80, the P-Well (P-Well)70 is generated on the right side of the P-type substrate (P-Sub)80, the high-concentration N-type doping (N +)28 and the high-concentration P-type doping (P +)20 are arranged on the upper part of the N-Well (N-Well)60, the high-concentration P-type doping (P +)20, the N-Well (N-Well)60 and the P-Well (P-Well)70 form an equivalent PNP triode structure, the low-concentration P-type light doping (PLDD)22 and the high-concentration N-type doping (N +)24 are arranged on the upper part of the P-Well (P-Well)70, and the N-Well (N-Well)60, the P-Well (P-Well)70 and the high-concentration N-type doping (N +)24 form an equivalent triode structure;
a Shallow Trench Isolation (STI) 10 is disposed on the left side of the high concentration N-type dopant (N +)28, the high concentration N-type dopant (N +)28 and the high concentration P-type dopant (P +)20 are separated by an N-Well (N-Well)60 (i.e., a portion of the N-Well 60 is spaced therebetween), a first floating gate 40 is disposed over the N-Well, the high concentration P-type dopant (P +)20 is separated on the right side by a portion of the N-Well (N-Well)60, the N-Well (N-Well)60 has a width a, the low concentration P-type lightly doped (PLDD)22 and the high concentration N-type dopant (N +)24 are separated by a P-Well (P-Well)70 (i.e., a portion of the N-Well 70 is spaced therebetween), the P-Well (P-Well)70 has a width S2, an N-type floating gate 90 is disposed over the P-Well (P-Well)70, and the high concentration N-type dopant (P +)24 is disposed on the right side of the Shallow Trench Isolation (STI) (i.e., a portion of the N-Well) (P-Well) 24 is spaced therebetween, shallow Trench Isolation)10, the width of the low concentration P-type lightly doped drain (PLDD)22 is S1, the left side of the low concentration P-type lightly doped drain (PLDD)22 is a part of the P-Well (P-Well)70, and the width of the part of the P-Well (P-Well)70 is B;
4 metal silicides 30 are generated above the high-concentration N-type doping (N +)28, above the high-concentration P-type doping (P +)20, above the right side of the low-concentration P-type lightly doping (PLDD)22 and above the high-concentration N-type doping (N +)24, a second floating gate 50 is arranged above the left side of the low-concentration P-type lightly doping (PLDD)22, above a P well with the width of B on the left side of the low-concentration P-type lightly doping (PLDD)22 and above an N well with the width of A on the right side of the high-concentration P-type doping (P +)20, namely the second floating gate 50 is arranged above the boundary of the N well and the P well and covers a part of the left side of the low-concentration P-type lightly doping (PLDD)22, and the second floating gate 50 is an N-type gate;
the leading-out electrode of the metal silicide 30 above the high-concentration N-type doping (N +)28 is connected to a power supply Vdd, the leading-out electrode of the metal silicide 30 above the high-concentration P-type doping (P +)20 is used as an Anode Anode of the grid-constraint silicon controlled rectifier ESD device, the upper right side of the low-concentration P-type light doping (PLDD)22 is connected with the metal silicide 30 above the high-concentration N-type doping (N +)24 and the leading-out electrode forms a Cathode Cathode of the grid-constraint silicon controlled rectifier ESD device, and the Cathode is grounded Vss when the grid-constraint silicon controlled rectifier ESD device is used.
It can be seen that, in the present invention, the schottky junction of the gate-constrained scr (as shown in fig. 2) in the prior art is removed, and a low-concentration P-type lightly doped region (PLDD)22 formed by P-type lightly doping is inserted between the high-concentration N-type doping (N +)24 and the second floating gate 50 (N-type gate 50), the low-concentration P-type lightly doped region (PLDD)22 is separated from the high-concentration N-type doping (N +)24 by a P-Well (P-Well)70, an N-type gate 90 is disposed above the part of the P-Well (P-Well)70, a metal silicide is formed on the upper surface of the low-concentration P-type lightly doped region (PLDD)22, and then the metal silicide is connected to the cathode of the scr together with the high-concentration N-type doping (N +)24, the high-concentration N-type doping (N +)24 serves as the emitter of the parasitic NPN transistor in the gate-constrained scr, and the additionally inserted low-concentration P-type lightly doped region (PLDD)22 reduces the emission of the high-concentration N-type doping (N24) to emit electrons to the P + emitter The Well 70 migrates to the interface between the P-Well and the N-Well, thereby reducing the current gain (β) of the parasitic NPN transistor (high concentration N-type doping (N +) 24/P-Well (P-Well) 70/N-Well (N-Well)60) inside the scr, increasing the holding voltage (Vh) of the gate-tied scr, and the low concentration P-type lightly doped region (PLDD)22 can also function as the P-Well 70 junction, so that the P-Well 70 junction (i.e., the high concentration P-type doping (P +)26 in fig. 2) originally located on the right side of the high concentration N-type doping (N +)24 can be removed.
The gate-constrained silicon controlled rectifier provided by the invention has the advantages that the low-concentration P-type lightly doped region (PLDD)22 formed by P-type light doping is inserted between the high-concentration N-type doping (N +)24 and the N-type grid 50, so that the maintenance voltage of the gate-constrained silicon controlled rectifier can be improved, the manufacturing process can be simplified, the interface defect caused by the introduction of a Schottky junction can be reduced, the contact resistance of the Schottky junction can be reduced, and the layout area can be reduced.
FIG. 5 is a flowchart illustrating steps of a method for implementing a gate-tied SCR ESD device according to the present invention. As shown in fig. 5, the method for implementing an ESD device of a gate-tied scr according to the present invention includes the following steps:
in step 501, a semiconductor substrate is provided, and in the embodiment of the present invention, a P-type substrate (P-Sub)80 is provided.
In step 502, two wells, i.e., N-Well 60 and P-Well 70, are formed in the semiconductor substrate, i.e., N-Well 60 and P-Well 70, in the P-type substrate 80, N-Well 60 and P-Well 70 are formed in the P-type substrate 80, N-Well 60 is formed on the left side of P-type substrate 80, and P-Well 70 is formed on the right side of P-type substrate 80.
In step 503, an equivalent PNP triode structure is formed in the N Well (N-Well)60, and an equivalent NPN triode structure is formed in the P Well 70. Specifically, a high-concentration N-type dopant (N +)28, a high-concentration P-type dopant (P +)20 are disposed on the upper portion of an N-Well (N-Well)60, the high-concentration P-type dopant (P +)20, the N-Well (N-Well)60 and a P-Well (P-Well)70 form an equivalent PNP triode structure, a Shallow Trench Isolation layer (STI) 10 is disposed on the left side of the high-concentration N-type dopant (N +)28, the high-concentration N-type dopant (N +)28 and the high-concentration P-type dopant (P +)20 are separated by the N-Well (N-Well)60 (i.e., a portion of the interval therebetween is 60), a first floating gate 40 is disposed above the portion of the N-Well, the right side of the high-concentration P-type dopant (P +)20 is a portion of the N-Well (N-Well)60, and the portion of the N-Well (N-Well)60 has a width a; placing a low-concentration P-type lightly doped drain (PLDD)22 and a high-concentration N-type doped drain (N +)24 on the upper part of a P-Well (P-Well)70, wherein the N-Well (N-Well)60, the P-Well (P-Well)70 and the high-concentration N-type doped drain (N +)24 form an equivalent NPN triode structure, the low-concentration P-type lightly doped drain (PLDD)22 and the high-concentration N-type doped drain (N +)24 are separated by the P-Well (P-Well)70 (i.e. a part of the interval between the P-Well and the high-concentration N-type doped drain is 70), the width of the part of the P-Well (P-Well)70 is S2, an N-type floating gate 90 is placed above the part of the P-Well (P-Well)70, a Shallow channel Isolation layer (STI, Shallow Trench Isolation)10 is placed on the right side of the high-concentration N-type doped drain (N +)24, the width of the low-concentration P-type lightly doped drain (PLDD)22 is S1, and the left side of the low-concentration P-type lightly doped drain (PLDD)22 is a part of the P-Well (P-Well 70, the width of the portion of the P-Well (P-Well)70 is B;
When in use, in order to protect an IO port, the Cathode Cathaode of the ESD device of the grid-constrained silicon controlled rectifier is grounded Vss, the Vdd end (namely the metal silicide 30 above the high-concentration N-type doping (N +) 28) is connected with a power voltage Vdd, and the Anode Anode is connected with an external IO (input/output end); to protect the power supply, some other ESD protection device may be connected after the gate-tied scr ESD device to obtain the desired characteristics, as shown in fig. 6.
In summary, according to the gate-tied silicon controlled rectifier ESD device and the implementation method thereof, the schottky junction of the existing gate-tied silicon controlled rectifier ESD device is removed, and the low-concentration P-type lightly doped drain (PLDD) is inserted between the high-concentration N-type doped region (24) and the second floating gate (50), so that the manufacturing process can be simplified while the holding voltage of the device is increased, the interface defect caused by the introduction of the schottky junction is reduced, the contact resistance of the device is reduced, and the device is more suitable for the anti-static protection design of the integrated circuit in the advanced CMOS process.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (8)
1. A gate-tied silicon controlled rectifier (ESD) device, the ESD device comprising:
a semiconductor substrate (80);
an N-well (60) and a P-well (70) formed in the semiconductor substrate (80);
a high-concentration N-type doping (28) and a high-concentration P-type doping (20) are arranged at the upper part of the N well (60), a low-concentration P-type light doping (22) and a high-concentration N-type doping (24) are arranged at the upper part of the P well (70), the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) are isolated by the P well (70), and a second floating gate (50) is arranged above the upper part of the left side of the low-concentration P-type light doping (22), the upper part of the P well (70) with the width of B at the left side and the upper part of the N well (60) with the width of A at the right side of the high-concentration P-type doping (20);
respectively generating metal silicides (30) above the high-concentration N-type doping (28), the high-concentration P-type doping (20), the part above the low-concentration P-type light doping (22) and the high-concentration N-type doping (24);
and the metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) is connected to a connecting power supply, the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) is used as an anode of the grid-constrained silicon controlled rectifier ESD device, and the metal silicide (30) above the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) are connected and lead-out electrode to form a cathode of the grid-constrained silicon controlled rectifier ESD device.
2. A gate-tied scr ESD device as claimed in claim 1, wherein: the portion of the P-well (70) between the low concentration P-type lightly doped region (22) and the high concentration N-type doped region (24) has a width S2, and an N-type gate (90) is disposed over a portion of the P-well (70).
3. A gate-tied scr ESD device as claimed in claim 2, wherein: the high concentration P-type doping (20), the N-well (60), and the P-well (70) form an equivalent PNP triode structure.
4. A gate-tied scr ESD device as claimed in claim 2, wherein: the N well (60), the P well (70) and the high-concentration N-type doping (24) form an equivalent NPN triode structure.
5. A gate-tied scr ESD device as claimed in claim 2, wherein: a shallow channel isolation layer (10) is arranged on the left side of the high-concentration N-type doping (28), the high-concentration N-type doping (28) and the high-concentration P-type doping (20) are isolated by the N well (60), and a first floating gate (40) is arranged above part of the N well.
6. A gate-tied SCR ESD device as recited in claim 5, wherein: the hysteresis effect characteristic of the ESD device is jointly determined by A, B, S2 and the width S1 of the low-concentration P-type light doping (22), wherein A is 0.1-0.5 um, B is 0.1-0.5 um, S1 is 0.05-1 um, and S2 is 0.1-5 um.
7. A method for realizing a grid-constrained silicon controlled rectifier ESD device is characterized by comprising the following steps:
step 501, providing a semiconductor substrate (80);
step 502 of forming an N-well (60) and a P-well (70) in the semiconductor substrate (80);
step 503, placing high-concentration N-type doping (28) and high-concentration P-type doping (20) on the upper part of an N well (60), placing low-concentration P-type light doping (22) and high-concentration N-type doping (24) on the upper part of the P well (70), wherein the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) are isolated by the P well (70), and placing a second floating gate (50) above the left side of the low-concentration P-type light doping (22) and above the P well (70) with the width of B on the left side and above the N well (60) with the width of A on the right side of the high-concentration P-type doping (20);
step 504, respectively generating metal silicides (30) above the high-concentration N-type doping (28), above the high-concentration P-type doping (20), above the low-concentration P-type light doping (22) and above the high-concentration N-type doping (24);
and 505, connecting a metal silicide (30) leading-out electrode above the high-concentration N-type doping (28) to a connecting power supply, taking the metal silicide (30) leading-out electrode above the high-concentration P-type doping (20) as an anode of the grid-restrained silicon controlled rectifier ESD device, and connecting the metal silicide (30) above the low-concentration P-type light doping (22) and the high-concentration N-type doping (24) and leading-out electrode to form a cathode of the grid-restrained silicon controlled rectifier ESD device.
8. The method of claim 7, wherein the ESD device comprises: the width of the portion of the P-well (70) between the low concentration P-type lightly doped region (22) and the high concentration N-type doped region (24) is S2, and the N-type gate (90) is disposed over a portion of the P-well (70).
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| CN101667600A (en) * | 2009-09-09 | 2010-03-10 | 上海宏力半导体制造有限公司 | Schottky diode structure |
| CN104704636A (en) * | 2012-11-02 | 2015-06-10 | 德州仪器公司 | ESD protection circuit with isolated SCR for negative voltage operation |
| CN107369682A (en) * | 2017-08-23 | 2017-11-21 | 上海华力微电子有限公司 | A kind of new thyristor type esd protection structure and its implementation |
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