CN111799256B - Protection ring for improving negative current latch-up prevention capability of high-voltage integrated circuit and implementation method - Google Patents

Protection ring for improving negative current latch-up prevention capability of high-voltage integrated circuit and implementation method Download PDF

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CN111799256B
CN111799256B CN202010693328.1A CN202010693328A CN111799256B CN 111799256 B CN111799256 B CN 111799256B CN 202010693328 A CN202010693328 A CN 202010693328A CN 111799256 B CN111799256 B CN 111799256B
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concentration
voltage
type doping
well
type
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CN111799256A (en
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朱天志
黄冠群
陈昊瑜
邵华
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

The invention discloses a guard ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit and an implementation method thereof.

Description

Protection ring for improving negative current latch-up prevention capability of high-voltage integrated circuit and implementation method
Technical Field
The invention relates to the field of integrated circuit design, in particular to a protection ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit and an implementation method thereof.
Background
Dual guard ring structures are used in IO circuits of almost all integrated circuit process platforms to enhance the latch-up prevention capability of integrated circuits. However, even if the dual protection bad structure is applied in the high-voltage integrated circuit, failure caused by insufficient latch-up prevention capability of the negative current impact prevention mode of the high-voltage IO terminal often occurs, and failure analysis finds that the failure cause is often caused by that the drain electrode of the NLDMOS (hereinafter, for convenience of description, the high-voltage device is an LDMOS) in the IO circuit of the high-voltage integrated circuit, and the parasitic NPN triode formed by the high-voltage P-well and the outer protection ring (NGR 2) is easily triggered and kept on due to larger current gain, as shown in fig. 1.
As shown in fig. 1, a conventional protection ring structure for preventing negative current latch-up at the IO terminal of a high-voltage integrated circuit in the prior art includes: a plurality of shallow trench isolation layers (STI, shallowTrenchIsolation) 10, a high concentration P-type doping (p+) 22, a high concentration P-type doping (p+) 23, a high concentration N-type doping (n+) 24, a high concentration P-type doping (p+) 25, a P-type diffusion region (Pdrift) 40, a high concentration N-type doping (n+) 26, a high concentration P-type doping (p+) 27, a high concentration N-type doping (n+) 28, a high concentration N-type doping (n+) 29, an N-type diffusion region (Ndrift) 50, a first high voltage N-well (HVNW) 60, a second high voltage N-well (HVNW) 61, a first high voltage P-well (HVPW) 70, a second high voltage P-well (HVPW) 71, a P-type substrate (P-Sub) 80, and a first gate 30 and a second gate 31.
The entire guard ring structure is placed on a P-type substrate (P-Sub) 80, two high voltage wells are created in the P-type substrate (P-Sub) 80: high voltage N-wells (HVNW) 60/61 and high voltage P-wells (HVPW) 70/71, two each, wherein a first high voltage N-well (HVNW) 60 is generated on the left side of a P-type substrate (P-Sub) 80, a first high voltage P-well (HVPW) 70 is generated on the right side of the P-type substrate (P-Sub) 80, a second high voltage P-well (HVPW) 71 is on the right side of the first high voltage N-well (HVNW) 60, a second high voltage N-well (HVNW) 61 is on the right side of the second high voltage P-well (HVPW) 71, and a first high voltage P-well (HVPW) 70 is on the right side of the second high voltage N-well (HVNW) 61; the shallow trench isolation layer (STI, shallowTrenchIsolation) 10 is used for isolating the upper right side of the first high-voltage N well (HVNW) 60 from the upper left side of the second high-voltage P well (HVPW) 71, the upper right side of the second high-voltage P well (HVPW) 71 from the upper left side of the second high-voltage N well (HVNW) 61, and the upper right side of the second high-voltage N well (HVNW) 61 from the upper left side of the first high-voltage P well (HVPW) 70;
the P-type diffusion region (Pdrift) 40 is disposed in the middle of the upper portion of the first High Voltage N Well (HVNW) 60, the high concentration P-type dopant (p+) 22 is disposed on the left side of the upper portion of the first High Voltage N Well (HVNW) 60, and the first High Voltage N Well (HVNW) 60 is not in contact with the boundary of other regions around the high concentration P-type dopant (p+) 22; the high-concentration P-type doping (P+) 23 is arranged in the upper region in the P-type diffusion region (Pdrift) 40, the left side of the upper region is provided with a shallow trench isolation layer (STI, shallowTrenchIsolation) 10, the left side of the shallow trench isolation layer (STI, shallowTrenchIsolation) 10 and the right side of the high-concentration P-type doping (P+) 23 are provided with the P-type diffusion region (Pdrift) 40, namely the upper region is surrounded by the P-type diffusion region (Pdrift) 40; the high-concentration N-type doped (N+) 24 is arranged on the right side of the upper part of the high-voltage N-well (HVNW) 60, the right side of the high-concentration N-type doped (N+) is a shallow channel isolation layer (STI, shallowTrenchIsolation) 10 for separating the second high-voltage P-well 71 from the first high-voltage N-well 60, and the left side of the high-concentration N-type doped (N+) is isolated from the right side of a P-type diffusion region (Pdrift) 40 in the first high-voltage N-well 60 by the shallow channel isolation layer (STI, shallow TrenchIsolation);
the high-concentration P-type doping (P+) 25 is positioned over the whole second high-voltage P-well (HVPW) 71, and two sides of the high-concentration P-type doping are provided with shallow trench isolation layers (STI, shallowTrenchIsolation) 10 for isolation; the high-concentration N-type doping (N+) 26 is positioned on the whole upper part of the second high-voltage N well (HVNW) 61, and two sides of the high-concentration N-type doping are provided with shallow channel isolation layers (STI, shallowTrenchIsolation) 10 for isolation;
an N-type diffusion region (Ndrift) 50 is arranged in the middle of the upper part of the first high-voltage P-well (HVPW) 70, a high-concentration N-type doping (N+) 29 is arranged on the right side of the upper part of the first high-voltage P-well (HVPW) 70, and the first high-voltage P-well (HVPW) 70 is not contacted with the boundary of other areas around the high-concentration N-type doping (N+) 29; the high-concentration N-type doping (N+) 28 is arranged in the upper region in the N-type diffusion region (Ndrift) 50, the right side of the high-concentration N-type doping (N+) 28 is provided with a shallow trench isolation layer (STI, shallowTrenchIsolation) 10, the right side of the shallow trench isolation layer (STI, shallowTrenchIsolation) 10 and the left side of the high-concentration N-type doping (N+) 28 are provided with N-type diffusion regions (Ndrift) 50, namely the N-type diffusion regions (Ndrift) 50 are surrounded by the N-type diffusion regions (Ndrift); the high-concentration P-type doped (P+) 27 is arranged at the left side of the upper part of the first high-voltage P-well (HVPW) 70, the left side of the high-concentration P-type doped is a shallow channel isolation layer (STI, shallowTrenchIsolation) 10 for separating the second high-voltage N-well 61 from the first high-voltage P-well 70, and the right side of the high-concentration P-type doped is isolated from the left side of an N-type diffusion region (Ndrift) 50 in the first high-voltage P-well 70 by the shallow channel isolation layer (STI, shallowTrenchIsolation);
the first gate 30 is located above the right side of the high concentration P-type doping (p+) 22 and above the left side of the P-type diffusion region (Pdrift) 40; the second gate 31 is located above the left side of the high concentration N-type doping (n+) 29 and above the right side of the N-type diffusion region (Ndrift) 50;
connecting wires are led out above the high-concentration P-type doping (P+) 22 and the high-concentration N-type doping (N+) 29, and a power supply Vcc and a ground Vss are respectively led out; connecting lines PGR1, PGR2, NGR2 and NGR1 are led out above a high-concentration N-type doping (N+) 24 (width GW 1), a high-concentration P-type doping (P+) 25 (width GW 2), a high-concentration N-type doping (N+) 26 (width GW 2) and a high-concentration P-type doping (P+) 27 (width GW 1) and respectively connected with a power supply Vcc, a ground Vss, a power supply Vcc and a ground Vss; the connecting wires are led out from the upper parts of the high-concentration P-type doping (P+) 23 and the high-concentration N-type doping (N+) 28, are connected together and are connected to a bonding pad, namely an IO end;
in this structure, the high-concentration N-type doping (n+) 26, the first high-voltage P-well 70 and the high-concentration N-type doping (n+) 28 form a parasitic NPN transistor structure, the high-concentration N-type doping (28) forms an emitter of the parasitic NPN transistor, the high-concentration N-type doping (26) forms a collector of the parasitic NPN transistor, and the first high-voltage P-well (70) forms a base of the parasitic NPN transistor.
In order to reduce the width of the inner guard ring at the periphery of the high-voltage device to achieve the purpose of saving layout area, the industry proposes a novel guard ring structure of a high-voltage integrated circuit as shown in fig. 3, wherein the outer guard ring of the high-voltage NLDMOS in the IO circuit is grounded to Vss by high-concentration N-type doping (n+) 26, that is, NGR2, instead of being connected to power Vcc, which has the advantages of reducing the voltage of the collector of the parasitic NPN transistor (high-concentration N-type doping (n+) 28, that is, NLDMOSDrain/HVPW70/NGR 2), reducing the probability of triggering the parasitic NPN transistor, but increasing the risk of positive current impact mode latch-up at the high-voltage IO terminal, because the current gain (β) of the parasitic NPN transistor (HVNW 60/HVPW 71/ngpw 2) in the parasitic silicon controlled rectifier (PLDMOS drain [ that is, high-concentration P-type doping (p+) 23]/HVNW60/HVPW 71/ngpw 2) is too large.
The industry then proposes, based on the prior art high voltage integrated circuit guard ring structure 1 as shown in fig. 3, a prior art high voltage integrated circuit guard ring structure as shown in fig. 4, which removes the high concentration N-type doping (n+) 26 in the outer guard ring of the NLDMOS of the prior art high voltage integrated circuit guard ring structure of fig. 3, forming a schottky junction (schottky) because the schottky junction is formed by a metal electrode in direct contact with the second high voltage N-well 61, which reduces the efficiency of electron emission from the electrode 26 into the second high voltage P-well 71, i.e. reduces the current gain (β) of the parasitic transistor NPN (HVNW 60/HVPW71// NGR 2), which reduces the risk of positive current impact mode latch-up at the high voltage IO terminal, but this approach is prone to interface defects due to the introduction of the schottky junction, which additionally increases the process complexity.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a protection ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit and an implementation method thereof, so as to achieve the purposes of improving the latch-up prevention capability of the high-voltage integrated circuit in a negative current impact mode, reducing the width of the protection ring in a high-voltage device NLDMOS and saving the layout area.
In order to achieve the above-mentioned object, the present invention provides a protection ring for improving the negative current latch-up prevention capability of a high voltage integrated circuit, comprising:
a semiconductor substrate;
the first high-voltage N well, the second high-voltage P well, the second high-voltage N well and the first high-voltage P well are sequentially generated in the semiconductor substrate, and shallow trench isolation layers are arranged above the high-voltage wells;
the high-concentration P-type doping, the P-type diffusion region and the high-concentration N-type doping are sequentially arranged at the upper part of the first high-voltage N well, the high-concentration P-type doping is arranged at the inner upper part of the P-type diffusion region, the P-type diffusion region and the high-concentration N-type doping are isolated by a shallow trench isolation layer, the other side of the high-concentration N-type doping is a shallow trench isolation layer for separating the first high-voltage N well and the second high-voltage P well, the high-concentration P-type doping and the high-concentration N-type doping are respectively arranged at the upper parts of the second high-voltage P well and the second high-voltage N well, the high-concentration P-type doping, the N-type diffusion region and the high-concentration N-type doping are sequentially arranged at the upper part of the first high-voltage P well, the shallow trench isolation layer is arranged between the shallow trench isolation layer for separating the second high-voltage N well and the first high-voltage P well and the left side of the shallow trench isolation layer in the first high-voltage P well;
a first grid is arranged above the high-concentration P-type doping and P-type diffusion region, and a second grid is arranged above the high-concentration N-type doping and N-type diffusion region;
leading out connecting wires above the high-concentration P-type doping and the high-concentration N-type doping, and respectively connecting a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping, the high-concentration P-type doping and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; the high-concentration N-type doped upper lead-out connecting wire is connected with a resistor R and then connected to a power supply Vcc, and the high-concentration P-type doped upper lead-out connecting wire and the high-concentration N-type doped upper lead-out connecting wire are connected together and connected to an IO end.
Preferably, the resistor R is a non-metal silicided polysilicon resistor.
Preferably, the resistance value of the resistor R ranges from 100 to 5000 ohms.
Preferably, the first high-voltage N-well, the second high-voltage P-well, the second high-voltage N-well and the first high-voltage P-well are sequentially generated from left to right in the semiconductor substrate.
Preferably, a shallow channel isolation layer is arranged on the left side of the high-concentration P-type doping and in the P-type diffusion region.
Preferably, a shallow channel isolation layer is disposed on the right side of the high-concentration N-type doping and in the N-type diffusion region, the high-concentration N-type doping, the first high-voltage P-well and the high-concentration N-type doping form a parasitic NPN triode structure, the high-concentration N-type doping forms an emitter of the parasitic NPN triode, the high-concentration N-type doping forms a collector of the parasitic NPN triode, and the first high-voltage P-well forms a base of the parasitic NPN triode.
Preferably, the high-concentration P-type doping, the P-type diffusion region and the high-concentration N-type doping are sequentially arranged on the upper portion of the first high-voltage N-well from left to right.
Preferably, the high-concentration P-type doping, the N-type diffusion region and the high-concentration N-type doping are sequentially arranged on the upper portion of the first high-voltage P-well from left to right.
In order to achieve the above objective, the present invention further provides a method for implementing a protection ring for improving the negative current latch-up prevention capability of a high voltage integrated circuit, which is characterized in that: a non-metal silicided polysilicon resistor is connected in series on the high-concentration N-type doping of the existing guard ring structure and then connected to a power supply Vcc, so that the parasitic NPN triode is prevented from entering a maintaining conduction state after being triggered by mistake.
Preferably, the implementation method comprises the following steps:
step S1, a semiconductor substrate is provided, and a first high-voltage N well, a second high-voltage P well, a second high-voltage N well and a first high-voltage P well are sequentially generated in the semiconductor substrate, wherein shallow trench isolation layers are used for isolating the upper parts among the high-voltage wells.
S2, sequentially arranging high-concentration P-type doping, a P-type diffusion region and high-concentration N-type doping at the upper part of a first high-voltage N well (HVNW), arranging shallow trench isolation layers between the P-type diffusion region and the high-concentration N-type doping, arranging shallow trench isolation layers at the upper part of the N-type diffusion region, wherein the other side of the high-concentration N-type doping is used for separating the first high-voltage N well from a second high-voltage P well, arranging high-concentration P-type doping and high-concentration N-type doping at the upper parts of the second high-voltage P well and the second high-voltage N well respectively, arranging high-concentration P-type doping, N-type diffusion region and high-concentration N-type doping at the upper part of the first high-voltage P well, arranging shallow trench isolation layers between the high-concentration P-type doping and the shallow trench isolation layers at the lower part of the N-type diffusion region, and the shallow trench isolation layers at the left side of the N-type diffusion region in the first high-voltage P well;
and S3, arranging a first grid above the high-concentration P-type doping and P-type diffusion region and arranging a second grid above the high-concentration N-type doping and N-type diffusion region.
Step S4, leading out connecting wires above the high-concentration P-type doping and the high-concentration N-type doping, and respectively connecting the connecting wires with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping, the high-concentration P-type doping and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; the high-concentration N-type doped upper lead-out connecting wire is connected with the nonmetal silicided polysilicon resistor R and then connected to a power supply Vcc, and the high-concentration P-type doped upper lead-out connecting wire and the high-concentration N-type doped upper lead-out connecting wire are connected together and connected to an IO end.
Compared with the prior art, the invention has the following advantages:
(1) According to the invention, the non-metal silicided polysilicon resistor is connected in series with the outer guard ring of the existing high-voltage NLDMOS and then connected to the power supply Vcc, so that the voltage of the parasitic NPN triode which is directly dropped on the collector of the parasitic NPN triode (the outer guard ring of the N-type device) after being triggered by the negative current impact of the IO end once is triggered by mistake can be reduced, the parasitic NPN triode is prevented from entering a maintenance conducting state after being triggered by mistake, the latching capability of the high-voltage IO end in a negative current impact prevention mode is improved, the width of the guard ring in the high-voltage device NLDMOS is reduced, and the layout area is saved.
(2) The resistance of the nonmetal silicided polysilicon resistor influences the capability of the IO end of the high-voltage integrated circuit for preventing negative current impact mode latch-up.
(3) The width (GW 1) of the guard ring (NGR 1) in the high-voltage device influences the latch-up capability of the IO end of the high-voltage integrated circuit for preventing negative current impact mode.
Drawings
FIG. 1 is a block diagram of a guard ring structure of a conventional high voltage integrated circuit of the prior art;
FIG. 2 is a graph of the negative current impact mode latch-up prevention capability versus inner guard ring width for a conventional guard ring structure of a high voltage integrated circuit in the prior art;
FIG. 3 is a block diagram of another prior art high voltage integrated circuit guard ring structure;
FIG. 4 is a block diagram of another prior art high voltage integrated circuit guard ring structure;
FIG. 5 is a circuit diagram of a guard ring for improving negative current latch-up prevention capability of a high voltage integrated circuit according to the present invention;
FIG. 6 is a flow chart illustrating steps of a method for implementing a guard ring for improving negative current latch-up prevention capability of a high voltage integrated circuit according to the present invention;
fig. 7 is a schematic diagram of an application scenario of the present invention.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following disclosure, when considered in light of the accompanying drawings, by describing embodiments of the present invention with specific embodiments thereof. The invention may be practiced or carried out in other embodiments and details within the scope and range of equivalents of the various features and advantages of the invention.
FIG. 5 is a circuit diagram of a guard ring for improving negative current latch-up prevention capability of a high voltage integrated circuit according to the present invention. As shown in fig. 5, a guard ring for improving the negative current latch-up prevention capability of a high voltage integrated circuit according to the present invention includes: a plurality of shallow trench isolation layers (STI, shallowTrenchIsolation), a high-concentration P-type dopant (p+) 22, a high-concentration P-type dopant (p+) 23, a high-concentration N-type dopant (n+) 24, a high-concentration P-type dopant (p+) 25, a P-type diffusion region (Pdrift) 40, a high-concentration N-type dopant (n+) 26, a high-concentration P-type dopant (p+) 27, a high-concentration N-type dopant (n+) 28, a high-concentration N-type dopant (n+) 29, an N-type diffusion region (Ndrift) 50, a first high-voltage N-well (HVNW) 60, a second high-voltage N-well (HVNW) 61, a first high-voltage P-well (HVPW) 70, a second high-voltage P-well (HVPW) 71, a P-type substrate (P-Sub) 80, a first gate 30, a second gate 31, and a resistor R connected to the high-concentration N-type dopant (n+) 26.
The entire guard ring structure is placed on a P-type substrate (P-Sub) 80, two high voltage wells are created in the P-type substrate (P-Sub) 80: high voltage N-wells (HVNW) 60/61 and high voltage P-wells (HVPW) 70/71, two each, wherein a first high voltage N-well (HVNW) 60 is generated on the left side of a P-type substrate (P-Sub) 80, a first high voltage P-well (HVPW) 70 is generated on the right side of the P-type substrate (P-Sub) 80, a second high voltage P-well (HVPW) 71 is on the right side of the first high voltage N-well (HVNW) 60, a second high voltage N-well (HVNW) 61 is on the right side of the second high voltage P-well (HVPW) 71, and a first high voltage P-well (HVPW) 70 is on the right side of the second high voltage N-well (HVNW) 61; the shallow trench isolation layer (STI, shallowTrenchIsolation) 10 is used for isolating the upper right side of the first high-voltage N well (HVNW) 60 from the upper left side of the second high-voltage P well (HVPW) 71, the upper right side of the second high-voltage P well (HVPW) 71 from the upper left side of the second high-voltage N well (HVNW) 61, and the upper right side of the second high-voltage N well (HVNW) 61 from the upper left side of the first high-voltage P well (HVPW) 70;
the P-type diffusion region (Pdrift) 40 is disposed in the middle of the upper portion of the first High Voltage N Well (HVNW) 60, the high concentration P-type dopant (p+) 22 is disposed on the left side of the upper portion of the first High Voltage N Well (HVNW) 60, and the first High Voltage N Well (HVNW) 60 is not in contact with the boundary of other regions around the high concentration P-type dopant (p+) 22; the high-concentration P-type doping (P+) 23 is arranged in the upper region in the P-type diffusion region (Pdrift) 40, the left side of the upper region is provided with a shallow trench isolation layer (STI, shallowTrenchIsolation) 10, the left side of the shallow trench isolation layer (STI, shallowTrenchIsolation) 10 and the right side of the high-concentration P-type doping (P+) 23 are provided with the P-type diffusion region (Pdrift) 40, namely the upper region is surrounded by the P-type diffusion region (Pdrift) 40; the high-concentration N-type doped (N+) 24 is arranged on the right side of the upper part of the high-voltage N-well (HVNW) 60, the right side of the high-concentration N-type doped (N+) is a shallow channel isolation layer (STI, shallowTrenchIsolation) 10 for separating the second high-voltage P-well 71 from the first high-voltage N-well 60, and the left side of the high-concentration N-type doped (N+) is isolated from the right side of a P-type diffusion region (Pdrift) 40 in the first high-voltage N-well 60 by the shallow channel isolation layer (STI, shallow TrenchIsolation);
the high-concentration P-type doping (P+) 25 is positioned over the whole second high-voltage P-well (HVPW) 71, and two sides of the high-concentration P-type doping are provided with shallow trench isolation layers (STI, shallowTrenchIsolation) 10 for isolation; the high-concentration N-type doping (N+) 26 is positioned on the whole upper part of the second high-voltage N well (HVNW) 61, and two sides of the high-concentration N-type doping are provided with shallow channel isolation layers (STI, shallowTrenchIsolation) 10 for isolation;
an N-type diffusion region (Ndrift) 50 is arranged in the middle of the upper part of the first high-voltage P-well (HVPW) 70, a high-concentration N-type doping (N+) 29 is arranged on the right side of the upper part of the first high-voltage P-well (HVPW) 70, and the first high-voltage P-well (HVPW) 70 is not contacted with the boundary of other areas around the high-concentration N-type doping (N+) 29; the high-concentration N-type doping (N+) 28 is arranged in the upper region in the N-type diffusion region (Ndrift) 50, the right side of the high-concentration N-type doping (N+) 28 is provided with a shallow trench isolation layer (STI, shallowTrenchIsolation) 10, the right side of the shallow trench isolation layer (STI, shallowTrenchIsolation) 10 and the left side of the high-concentration N-type doping (N+) 28 are provided with N-type diffusion regions (Ndrift) 50, namely the N-type diffusion regions (Ndrift) 50 are surrounded by the N-type diffusion regions (Ndrift); the high-concentration P-type doped (P+) 27 is arranged at the left side of the upper part of the first high-voltage P-well (HVPW) 70, the left side of the high-concentration P-type doped is a shallow channel isolation layer (STI, shallowTrenchIsolation) 10 used for isolating the second high-voltage N-well 61 from the first high-voltage P-well 70, and the right side of the high-concentration P-type doped is isolated from the left side of an N-type diffusion region (Ndrift) 50 in the first high-voltage P-well 70 by the shallow channel isolation layer (STI, shallowTrenchIsolation) 10;
the first gate 30 is located above the right side of the high concentration P-type doping (p+) 22 and above the left side of the P-type diffusion region (Pdrift) 40; the second gate 31 is located above the left side of the high concentration N-type doping (n+) 29 and above the right side of the N-type diffusion region (Ndrift) 50;
leading out connecting wires above the high-concentration P-type doping (P+) 22 and the high-concentration N-type doping (N+) 29, and respectively connecting a power supply end Vcc and a ground end Vss; connecting lines PGR1, PGR2 and NGR1 are led out above a high-concentration N-type doping (N+) 24 (width GW 1), a high-concentration P-type doping (P+) 25 (width GW 2) and a high-concentration P-type doping (P+) 27 (width GW 1) and respectively connected with a power supply Vcc, a ground Vss and a ground Vss; the lead-out connection wire above the high-concentration N-type doping (N+) 26 (width GW 2) is connected with a resistor R and then connected with a power supply Vcc, and the lead-out connection wires above the high-concentration P-type doping (P+) 23 and the high-concentration N-type doping (N+) 28 are connected together and connected with a bonding pad, namely an IO end.
The high-concentration N-type doping (n+) 26, the first high-voltage P-well (HVPW) 70, and the high-concentration N-type doping (n+) 28 form a parasitic NPN transistor structure, the high-concentration N-type doping 28 forms an emitter of the parasitic NPN transistor, the high-concentration N-type doping 26 forms a collector of the parasitic NPN transistor, and the first high-voltage P-well 70 forms a base of the parasitic NPN transistor.
In the specific embodiment of the invention, the resistor R is a nonmetallic siliconized polysilicon resistor (Non-silicidedPoly resistor) with a resistance value ranging from 100 to 5000 ohms.
The invention relates to a realization method of a guard ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit, which is to connect a nonmetal silicided polysilicon resistor in series on a high-concentration N-type doping 26 of the prior guard ring structure and then connect the nonmetal silicided polysilicon resistor to a power supply Vcc so as to prevent a parasitic NPN triode from entering a maintenance conducting state after being triggered by mistake, as shown in figure 6, and comprises the following specific realization steps:
in step S1, a semiconductor substrate is provided, and a first high-voltage N-well 60, a second high-voltage P-well 71, a second high-voltage N-well 61, and a first high-voltage P-well 70 are sequentially formed in the semiconductor substrate, wherein the upper parts of the high-voltage wells are isolated by a shallow trench isolation layer 10.
Step S2, a high-concentration P-type doping 22, a P-type diffusion region 40 and a high-concentration N-type doping 24 are sequentially arranged at the upper part of a first high-voltage N-well (HVNW) 60, a shallow trench isolation layer 10 is arranged between the P-type diffusion region 40 and the high-concentration N-type doping 24 for isolation, the other side of the high-concentration N-type doping 24 is a shallow trench isolation layer 10 for separating a first high-voltage N-well 60 and a second high-voltage P-well 71, a high-concentration P-type doping 25 and a high-concentration N-type doping 26 are respectively arranged at the upper parts of the second high-voltage P-well 71 and the second high-voltage N-well 61, a high-concentration P-type doping 27, an N-type diffusion region 50 and a high-concentration N-type doping 29 are sequentially arranged at the upper part of the first high-voltage P-well 70, a channel isolation layer 10 is arranged between the high-concentration P-type doping 27 and the N-type diffusion region 50, a high-concentration N-type doping 28 is arranged at the upper part in the N-type diffusion region 50, and the high-concentration P-type doping 27 is arranged at the side of the shallow trench isolation layer 10 for separating the second high-voltage N-well 61 and the first high-voltage P-well 70;
in step S3, a first gate 30 is disposed above the high-concentration P-type dopant 22 and the P-type diffusion region 40, and a second gate 31 is disposed above the high-concentration N-type dopant 29 and the N-type diffusion region 50.
Step S4, leading out connecting wires above the high-concentration P-type doping 22 and the high-concentration N-type doping 29, and respectively connecting the connecting wires with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping 24, the high-concentration P-type doping 25 and the high-concentration P-type doping 27 and respectively connected with a power supply Vcc, a ground Vss and a ground Vss; the lead-out connection line above the high-concentration N-type doping 26 is connected with a resistor R and then connected with a power supply Vcc, and the lead-out connection lines above the high-concentration P-type doping 23 and the high-concentration N-type doping 28 are connected together and connected with an IO end.
In application, as shown in fig. 7, in order to protect the IO port, the ground terminal Vss of the guard ring structure of the present invention is connected to the high voltage power supply ground terminal hv_vss of the applied chip, the power supply terminal Vcc of the guard ring structure of the present invention is connected to the high voltage power supply terminal hv_vdd of the applied chip, and the IO terminal of the guard ring structure of the present invention is connected to the input/output terminal of the applied chip to protect the input/output terminal of the chip; or the power supply voltage is subjected to amplitude limiting protection (PowerClamp) without connecting the input end and the output end of the chip and is connected between the high-voltage power supply end HV_Vdd and the high-voltage power supply ground end HV_Vss of the chip in a bridging way.
Therefore, the invention connects in series a Non-metal silicided polysilicon resistor (Non-silicon polysilicon resistor) to the power supply Vcc in series on the high concentration N-doped (N+) 26 of the outer guard ring of the existing high voltage NLDMOS, which can reduce the latch-up capability of the parasitic NPN triode (NLDMOS Drain [ high concentration N-doped (N+) 28]/HVPW70/NGR 2) in the negative current impact mode of the high voltage NLDMOS, once the parasitic NPN triode is triggered by the negative current impact of the IO end by mistake, the parasitic NPN triode falls on the collector (N+ 26 of the N-doped (N+) 28[ namely NLDMOS Drain Drain ]/HVPW70/NGR 2) of the parasitic NPN triode, thereby avoiding the parasitic NPN triode from entering the maintaining on state after being triggered by mistake, reducing the width of the guard ring in the high voltage device NLDMOS and saving layout area.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be indicated by the appended claims.

Claims (9)

1. A guard ring for improving negative current latch-up prevention capability of a high voltage integrated circuit, comprising:
a semiconductor substrate (80);
a first high-voltage N-well (60), a second high-voltage P-well (71), a second high-voltage N-well (61) and a first high-voltage P-well (70) which are sequentially generated in the semiconductor substrate (80), wherein the upper parts of the high-voltage wells are isolated by a shallow trench isolation layer (10);
the high-concentration P-type doping (22), the P-type diffusion region (40) and the high-concentration N-type doping (24) are sequentially arranged at the upper part of the first high-voltage N-well (60), the high-concentration P-type doping (23) is arranged at the upper part in the P-type diffusion region (40), the P-type diffusion region (40) and the high-concentration N-type doping (24) are isolated by a shallow trench isolation layer (10), the other side of the high-concentration N-type doping (24) is the shallow trench isolation layer (10) for separating the first high-voltage N-well (60) and the second high-voltage P-well (71), the high-concentration P-type doping (25) and the high-concentration N-type doping (26) are respectively arranged at the upper part of the second high-voltage P-well (71), the high-concentration P-type doping (27), the N-type diffusion region (50) and the high-concentration N-type doping (29) are sequentially arranged at the upper part of the first high-voltage P-well (70), the high-concentration N-type doping region (27) and the high-concentration N-type doping (50) are sequentially arranged at the upper part of the first high-voltage P-well (70), the high-concentration N-type doping region (50) is separated by the shallow trench isolation layer (10), the high-concentration P-type doping (27) is arranged between a shallow trench isolation layer (10) for separating the second high-voltage N well (61) from the first high-voltage P well (70) and the shallow trench isolation layer (10) at the left side of the N-type diffusion region (50) in the first high-voltage P well (70);
a first grid electrode (30) is arranged above the high-concentration P-type doping (22) and the P-type diffusion region (40), and a second grid electrode (31) is arranged above the high-concentration N-type doping (29) and the N-type diffusion region (50);
leading out connecting wires above the high-concentration P-type doping (22) and the high-concentration N-type doping (29), and respectively connecting a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (24), the high-concentration P-type doping (25) and the high-concentration P-type doping (27) and respectively connected with a power supply Vcc, a ground Vss and a ground Vss; the lead-out connecting wire above the high-concentration N-type doping (26) is connected with a resistor R and then connected with a power supply Vcc, and the lead-out connecting wires above the high-concentration P-type doping (23) and the high-concentration N-type doping (28) are connected together and connected with an IO end.
2. The guard ring of claim 1 for improving negative current latch-up protection of a high voltage integrated circuit, wherein: the resistor R is a nonmetallic siliconized polysilicon resistor.
3. The guard ring of claim 2 for improving negative current latch-up protection of a high voltage integrated circuit, wherein: the resistance value of the resistor R ranges from 100 to 5000 ohms.
4. A guard ring for improving negative current latch-up prevention capability of a high voltage integrated circuit as recited in claim 3, wherein: the first high-voltage N-well (60), the second high-voltage P-well (71), the second high-voltage N-well (61) and the first high-voltage P-well (70) are sequentially generated from left to right in the semiconductor substrate (80).
5. The guard ring of claim 4 for improving negative current latch-up protection of a high voltage integrated circuit, wherein: a shallow channel isolation layer (10) is arranged at the left side of the high-concentration P-type doping (23) and in the P-type diffusion region (40).
6. The guard ring of claim 5 for improving negative current latch-up prevention capability of a high voltage integrated circuit, wherein: a shallow channel isolation layer (10) is arranged on the right side of the high-concentration N-type doping (28) and in the N-type diffusion region (50), the high-concentration N-type doping (26), the first high-voltage P well (70) and the high-concentration N-type doping (28) form a parasitic NPN triode structure, the high-concentration N-type doping (28) forms an emitter of the parasitic NPN triode, the high-concentration N-type doping (26) forms a collector of the parasitic NPN triode, and the first high-voltage P well (70) forms a base of the parasitic NPN triode.
7. The guard ring of claim 1 for improving negative current latch-up protection of a high voltage integrated circuit, wherein: the high-concentration P-type doping (22), the P-type diffusion region (40) and the high-concentration N-type doping (24) are sequentially arranged on the upper portion of the first high-voltage N well (60) from left to right.
8. The guard ring of claim 1 for improving negative current latch-up protection of a high voltage integrated circuit, wherein: the high-concentration P-type doping (27), the N-type diffusion region (50) and the high-concentration N-type doping (29) are sequentially arranged on the upper portion of the first high-voltage P well (70) from left to right.
9. A realization method of a protection ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit is characterized in that: a non-metal silicided polysilicon resistor is connected in series on the high-concentration N-type doping (26) of the existing guard ring structure and then connected to a power supply Vcc, so as to avoid the parasitic NPN triode from entering a maintenance conducting state after being triggered by mistake;
the implementation method comprises the following steps:
step S1, providing a semiconductor substrate, and sequentially generating a first high-voltage N well (60), a second high-voltage P well (71), a second high-voltage N well (61) and a first high-voltage P well (70) in the semiconductor substrate, wherein the upper parts of the high-voltage wells are isolated by a shallow trench isolation layer (10);
step S2, high-concentration P-type doping (22), a P-type diffusion region (40) and high-concentration N-type doping (24) are sequentially arranged at the upper part of a first high-voltage N-well (HVNW) 60, shallow trench isolation layers (10) are arranged between the P-type diffusion region (40) and the high-concentration N-type doping (24), the other side of the high-concentration N-type doping (24) is a shallow trench isolation layer (10) for separating the first high-voltage N-well (60) and a second high-voltage P-well (71), high-concentration P-type doping (25), high-concentration N-type doping (26) are respectively arranged at the upper parts of the second high-voltage P-well (71) and the second high-voltage N-well (61), high-concentration P-type doping (27), N-type diffusion region (50) and high-concentration N-type doping (29) are sequentially arranged at the upper part of the first high-voltage P-well (70), the shallow trench isolation layers (10) are arranged between the high-concentration P-type doping (27) and the N-type diffusion region (50), the high-concentration N-type doping region (28) is arranged at the upper part of the high-concentration N-type doping region (50), the high-concentration P-type doping (27) is arranged between a shallow trench isolation layer (10) for separating the second high-voltage N well (61) from the first high-voltage P well (70) and the shallow trench isolation layer (10) at the left side of the N-type diffusion region (50) in the first high-voltage P well (70);
step S3, a first grid electrode (30) is arranged above the high-concentration P-type doping (22) and the P-type diffusion region (40), and a second grid electrode (31) is arranged above the high-concentration N-type doping (29) and the N-type diffusion region (50);
step S4, leading out connecting wires above the high-concentration P-type doping (22) and the high-concentration N-type doping (29) respectively connected with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (24), the high-concentration P-type doping (25) and the high-concentration P-type doping (27) and respectively connected with a power supply Vcc, a ground Vss and a ground Vss; the lead-out connecting wire above the high-concentration N-type doping (26) is connected with the nonmetal silicided polysilicon resistor R and then connected to a power supply Vcc, and the lead-out connecting wires above the high-concentration P-type doping (23) and the high-concentration N-type doping (28) are connected together and connected to an IO end.
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