CN111799256A - Protection ring for improving negative current latching prevention capability of high-voltage integrated circuit and implementation method - Google Patents
Protection ring for improving negative current latching prevention capability of high-voltage integrated circuit and implementation method Download PDFInfo
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- 230000002265 prevention Effects 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000003071 parasitic effect Effects 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 229910052755 nonmetal Inorganic materials 0.000 claims abstract description 14
- 230000001960 triggered effect Effects 0.000 claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims description 78
- 238000002955 isolation Methods 0.000 claims description 67
- 239000002019 doping agent Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 13
- 101100127672 Arabidopsis thaliana LAZY2 gene Proteins 0.000 claims description 8
- 101100516503 Danio rerio neurog1 gene Proteins 0.000 claims description 8
- 101100364400 Mus musculus Rtn4r gene Proteins 0.000 claims description 8
- 101100516512 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NGR1 gene Proteins 0.000 claims description 8
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- 101000987090 Homo sapiens MORF4 family-associated protein 1 Proteins 0.000 claims description 7
- 101000887427 Homo sapiens Probable G-protein coupled receptor 142 Proteins 0.000 claims description 7
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- 238000010586 diagram Methods 0.000 description 6
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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Abstract
The invention discloses a protection ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit and an implementation method thereof, the invention can reduce the voltage of a parasitic NPN triode falling on the collector of the parasitic NPN triode after the parasitic NPN triode is triggered by mistake by connecting a non-metal silicide polysilicon resistor in series with a high-concentration N-type doping (26) of the outer protection ring of the existing high-voltage NLDMOS and then connecting the non-metal silicide polysilicon resistor to a power supply terminal Vcc, thereby preventing the parasitic NPN triode from entering a maintained conducting state after being triggered by mistake, improving the latch-up capability of a negative current impact prevention mode of a high-voltage IO terminal, reducing the width of the protection ring in the high-voltage NL.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a protection ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit and an implementation method thereof.
Background
The double guard ring structure is used in IO circuits of almost all integrated circuit technology platforms to enhance the latch-up prevention capability of the integrated circuit. However, even if a dual protection structure is applied in a high voltage integrated circuit, failure often occurs due to insufficient latch-up prevention capability in a negative current surge prevention mode at a high voltage IO terminal, and the failure reason is found through failure analysis to be that a parasitic NPN transistor formed by a drain of an NLDMOS (hereinafter, referred to as an LDMOS for convenience), a high voltage P-well thereof, and an outer protection ring (NGR2) in the IO circuit of the high voltage integrated circuit is easily triggered and maintained to be on due to a large current gain, as shown in fig. 1.
As shown in fig. 1, a conventional protection ring structure for preventing negative current latch at IO terminal of a high voltage integrated circuit in the prior art includes: a plurality of Shallow Trench Isolation layers (STI) 10, high-concentration P-type dopants (P +)22, high-concentration P-type dopants (P +)23, high-concentration N-type dopants (N +)24, high-concentration P-type dopants (P +)25, P-type diffusion regions (Pdrift)40, high-concentration N-type dopants (N +)26, high-concentration P-type dopants (P +)27, high-concentration N-type dopants (N +)28, high-concentration N-type dopants (N +)29, N-type diffusion regions (Ndrift)50, first high-voltage N-wells (HVNW)60, second high-voltage N-wells (HVNW)61, first high-voltage P-wells (HVPW)70, second high-voltage P-wells (HVNW) 71, P-type substrates (P-Sub)80, and first and second gates 30 and 31.
The whole guard ring structure is placed on a P-type substrate (P-Sub)80, and two kinds of high-voltage wells are generated in the P-type substrate (P-Sub) 80: a High Voltage N Well (HVNW)60/61 and a High Voltage P Well (HVPW)70/71, two for each high voltage well, wherein the first High Voltage N Well (HVNW)60 is formed on the left side of the P-type substrate (P-Sub)80, the first High Voltage P Well (HVPW)70 is formed on the right side of the P-type substrate (P-Sub)80, the second High Voltage P Well (HVPW)71 is on the right side of the first High Voltage N Well (HVNW)60, the second High Voltage N Well (HVNW)61 is on the right side of the second High Voltage P Well (HVPW)71, and the first High Voltage P Well (HVPW)70 is on the right side of the second High Voltage N Well (HVNW) 61; a Shallow Trench Isolation (STI) 10 is used for isolating the space between the upper right side of the first High Voltage N Well (HVNW)60 and the upper left side of the second High Voltage P Well (HVPW)71, the space between the upper right side of the second High Voltage P Well (HVPW)71 and the upper left side of the second High Voltage N Well (HVNW)61, and the space between the upper right side of the second High Voltage N Well (HVNW)61 and the upper left side of the first High Voltage P Well (HVPW) 70;
the P-type diffusion region (Pdrift)40 is disposed in the middle of the upper portion of the first High Voltage N Well (HVNW)60, the high concentration P-type dopant (P +)22 is disposed on the left side of the upper portion of the first High Voltage N Well (HVNW)60, and the first High Voltage N Well (HVNW)60 is not in contact with other region boundaries around the high concentration P-type dopant (P +) 22; the high-concentration P-type doping (P +)23 is disposed in an upper region of the P-type diffusion region (Pdrift)40, a Shallow Trench Isolation (STI) 10 is disposed on the left side of the high-concentration P-type doping (P +)23, and the P-type diffusion region (Pdrift)40 is disposed on the left side of the Shallow Trench Isolation (STI) 10 and the right side of the high-concentration P-type doping (P +)23, i.e., surrounded by the P-type diffusion region (Pdrift) 40; the high-concentration N-type doping (N +)24 is arranged on the right side of the upper part of a high-voltage N well (HVNW)60, the right side of the high-concentration N-type doping (N +) is a Shallow Trench Isolation layer (STI) 10 for separating a second high-voltage P well (71) from a first high-voltage N well (60), and the left side of the high-concentration N-type doping (N +) is isolated from the right side of a P-type diffusion region (Pdrift)40 in the first high-voltage N well (60) by the Shallow Trench Isolation layer (STI, Shallow Trench Isolation) 10;
the high-concentration P-type doping (P +)25 is located above the second high-voltage P-well (HVPW)71, and both sides thereof are Shallow Trench Isolation (STI) layers 10 for Isolation; the high concentration N-type doping (N +)26 is located above the second High Voltage N Well (HVNW)61, and both sides thereof are Shallow Trench Isolation (STI) 10 for isolation;
an N-type diffusion region (Ndrift)50 is arranged in the middle of the upper part of a first high-voltage P well (HVPW)70, high-concentration N-type doping (N +)29 is arranged on the right side of the upper part of the first high-voltage P well (HVPW)70, and the first high-voltage P well (HVPW)70 is not in contact with the boundary of other regions around the high-concentration N-type doping (N +) 29; the high concentration N-type dopant (N +)28 is disposed in an upper region of the N-type diffusion region (Ndrift)50, and a Shallow Trench Isolation (STI) 10 is disposed at the right side of the high concentration N-type dopant (N +)28, and the N-type diffusion region (Ndrift)50 is disposed at the right side of the Shallow Trench Isolation (STI) 10 and the left side of the high concentration N-type dopant (N +)28, i.e., surrounded by the N-type diffusion region (Ndrift) 50; the high-concentration P-type doping (P +)27 is arranged on the left side of the upper part of the first high-voltage P well (HVPW)70, the left side of the high-concentration P-type doping (P +) is a Shallow Trench Isolation layer (STI) 10 for separating the second high-voltage N well (61) from the first high-voltage P well (70), and the right side of the high-concentration P-type doping (P +) is isolated from the left side of the N-type diffusion region (Ndrift)50 in the first high-voltage P well (70) by the Shallow Trench Isolation layer (STI) 10;
the first gate 30 is located over the right side of the high concentration P-type doping (P +)22 and over the left side of the P-type diffusion region (Pdrift) 40; a second gate 31 is located over the left side of the high concentration N-type doping (N +)29 and over the right side of the N-type diffusion region (Ndrift) 50;
connecting wires are respectively led out above the high-concentration P-type doping (P +)22 and the high-concentration N-type doping (N +)29, and a power supply Vcc and a ground Vss are respectively led out; connecting wires PGR1, PGR2, NGR2 and NGR1 are led out above the high-concentration N-type doping (N +)24 (width GW1), the high-concentration P-type doping (P +)25 (width GW2), the high-concentration N-type doping (N +)26 (width GW2) and the high-concentration P-type doping (P +)27 (width GW1), and are respectively connected with a power supply Vcc, a ground Vss, a power supply Vcc and a ground Vss; leading out connecting wires above the high-concentration P-type doping (P +)23 and the high-concentration N-type doping (N +)28 to be connected together and connected to a bonding pad (IO terminal);
in the structure, the high-concentration N-type doping (N +)26, the first high-voltage P well 70 and the high-concentration N-type doping (N +)28 form a parasitic NPN triode structure, the high-concentration N-type doping (28) forms an emitter of the parasitic NPN triode, the high-concentration N-type doping (26) forms a collector of the parasitic NPN triode, and the first high-voltage P well (70) forms a base of the parasitic NPN triode.
In order to reduce the width of the inner guard ring at the periphery of the high-voltage device to achieve the purpose of saving layout area, the industry proposes a novel high-voltage integrated circuit guard ring structure as shown in fig. 3, the outer guard ring of the high-voltage NLDMOS in the IO circuit is grounded to Vss by high-concentration N-type doping (N +)26, i.e. NGR2, instead of the power supply Vcc, this approach has the benefit of reducing the voltage at the collector of the parasitic NPN transistor (high concentration N-type dopant (N +)28, i.e., NLDMOS Drain/HVPW70/NGR2), reducing the probability of the parasitic NPN transistor being triggered, but increases the risk of positive current surge mode latch-up at the high voltage IO terminal due to excessive current gain (β) of the parasitic transistor NPN (HVNW 60/HVPW 71/NGR2) in the parasitic silicon controlled rectifier (PLDMOS drain [ i.e., high concentration P-type dopant (P +)23]/HVNW 60/HVPW 71/NGR 2).
The industry has then proposed a conventional high voltage integrated circuit guard ring structure as shown in figure 4 based on the conventional high voltage integrated circuit guard ring structure 1 as shown in figure 3, the high-concentration N-type doping (N +)26 in the outer protective ring of the NLDMOS of the existing high-voltage integrated circuit protective ring structure of figure 3 is removed to form a Schottky junction, since the schottky junction is formed by the metal electrode in direct contact with the second high voltage nwell 61, this reduces the efficiency of electron emission from the electrode 26 into the second high voltage pwell 71, i.e. this reduces the current gain (β) of the parasitic transistor NPN (HVNW 60/HVPW 71// NGR2), which also reduces the risk of positive current surge mode latch-up at the high voltage IO terminal, however, this method is prone to interface defects due to the introduction of schottky junctions, and also increases the process complexity.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a protection ring for improving the negative current latch-up prevention capability of a high-voltage integrated circuit and an implementation method thereof, so as to achieve the purposes of improving the latch-up prevention capability of the high-voltage integrated circuit in a negative current impact prevention mode, reducing the width of the protection ring in an NLDMOS (non-linear laterally diffused metal oxide semiconductor) device and saving the layout area.
To achieve the above object, the present invention provides a protection ring for improving negative current latch-up prevention capability of a high voltage integrated circuit, comprising:
a semiconductor substrate (80);
a first high-voltage N well (60), a second high-voltage P well (71), a second high-voltage N well (61) and a first high-voltage P well (70) which are sequentially generated in the semiconductor substrate (80), wherein shallow trench isolation layers (10) are used for isolating the upper parts of the high-voltage N wells;
high concentration P type doping (22), P type diffusion region (40) and high concentration N type doping (24) set gradually in first high pressure N trap (60) upper portion, upper portion sets up high concentration P type doping (23) in P type diffusion region (40), isolate with shallow trench isolation layer (10) between P type diffusion region (40) and the high concentration N type doping (24), high concentration N type doping (24) opposite side is shallow trench isolation layer (10) for separating first high pressure N trap (60) and second high pressure P trap (71), high concentration P type doping (25), high concentration N type doping (26) set respectively in second high pressure P trap (71), second high pressure N trap (61) upper portion, high concentration P type doping (27), N type diffusion region (50) and high concentration N type doping (29) set gradually in first high pressure P trap (70) upper portion, the high-concentration P-type doping (27) and the N-type diffusion region (50) are isolated by a shallow trench isolation layer (10), the high-concentration N-type doping (28) is arranged at the upper part in the N-type diffusion region (50), and the high-concentration P-type doping (27) is arranged between the shallow trench isolation layer (10) for separating the second high-voltage N well (61) and the first high-voltage P well (70) and the shallow trench isolation layer (10) on the left side of the N-type diffusion region (50) in the first high-voltage P well (70);
a first grid (30) is arranged above the position between the high-concentration P-type doping region (22) and the P-type diffusion region (40), and a second grid (31) is arranged above the position between the high-concentration N-type doping region (29) and the N-type diffusion region (50);
connecting wires are respectively led out above the high-concentration P-type doping (22) and the high-concentration N-type doping (29) and are respectively connected with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (24), the high-concentration P-type doping (25) and the high-concentration P-type doping (27) and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; and a connecting wire is led out above the high-concentration N-type doping (26), connected with a resistor R and then connected to a power supply Vcc, and is led out above the high-concentration P-type doping (23) and the high-concentration N-type doping (28), connected together and connected to an IO end.
Preferably, the resistor R is a non-metal silicide polysilicon resistor.
Preferably, the resistance value of the resistor R ranges from 100 to 5000 ohm.
Preferably, the first high-voltage N well (60), the second high-voltage P well (71), the second high-voltage N well (61) and the first high-voltage P well (70) are sequentially generated in the semiconductor substrate (80) from left to right.
Preferably, a shallow trench isolation layer (10) is arranged in the P-type diffusion region (40) on the left side of the high-concentration P-type doping (23).
Preferably, a shallow trench isolation layer (10) is arranged in the N-type diffusion region (50) on the right side of the high-concentration N-type doping (28), the high-concentration N-type doping (26), the first high-voltage P-well (70) and the high-concentration N-type doping (28) form a parasitic NPN triode structure, the high-concentration N-type doping (28) forms an emitter of the parasitic NPN triode, the high-concentration N-type doping (26) forms a collector of the parasitic NPN triode, and the first high-voltage P-well (70) forms a base of the parasitic NPN triode.
Preferably, the high-concentration P-type doping (22), the P-type diffusion region (40) and the high-concentration N-type doping (24) are sequentially arranged at the upper part of the first high-voltage N-well (60) from left to right.
Preferably, the high-concentration P-type doping (27), the N-type diffusion region (50) and the high-concentration N-type doping (29) are sequentially arranged on the upper portion of the first high-voltage P-well (70) from left to right.
In order to achieve the above object, the present invention further provides a method for implementing a protection ring for improving negative current latch prevention capability of a high voltage integrated circuit, comprising: a non-metal silicide polysilicon resistor is connected in series with a high-concentration N-type doping (26) of the existing protective ring structure and then connected to a power supply Vcc, so that a parasitic NPN triode is prevented from entering a state of maintaining conduction after being triggered by mistake.
Preferably, the implementation method comprises the following steps:
step S1, a semiconductor substrate is provided, and a first high voltage N well (60), a second high voltage P well (71), a second high voltage N well (61), and a first high voltage P well (70) are sequentially formed in the semiconductor substrate, and the upper portions of the high voltage N wells are isolated by a shallow trench isolation layer (10).
Step S2, sequentially arranging a high-concentration P-type doping (22), a P-type diffusion region (40) and a high-concentration N-type doping (24) on the upper portion of a first high-voltage N well (HVNW)60, arranging a shallow trench isolation layer (10) isolation between the P-type diffusion region (40) and the high-concentration N-type doping (24), arranging a high-concentration P-type doping (25) and a high-concentration N-type doping (26) on the upper portions of a second high-voltage P well (71) and a second high-voltage N well (61) respectively, sequentially arranging a high-concentration P-type doping (27), an N-type diffusion region (50) and a high-concentration N-type doping (29) on the upper portion of the first high-voltage P well (70), and arranging a shallow trench isolation layer (10) isolation between the high-concentration P-type doping (27) and the N-type diffusion region (50), a high-concentration N-type doping (28) is arranged at the upper part in the N-type diffusion region (50), and a high-concentration P-type doping (27) is arranged between a shallow channel isolation layer (10) for separating the second high-voltage N well (61) and the first high-voltage P well (70) and a shallow channel isolation layer (10) on the left side of the N-type diffusion region (50) in the first high-voltage P well (70);
in step S3, a first gate (30) is disposed over the high concentration P-type dopant (22) and the P-type diffusion region (40), and a second gate (31) is disposed over the high concentration N-type dopant (29) and the N-type diffusion region (50).
Step S4, leading out connecting wires above the high-concentration P-type doping (22) and the high-concentration N-type doping (29), and respectively connecting the connecting wires with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (24), the high-concentration P-type doping (25) and the high-concentration P-type doping (27) and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; and a connecting wire is led out above the high-concentration N-type doping (26) and connected with the non-metal silicification polysilicon resistor R, then the non-metal silicification polysilicon resistor R is connected with a power supply Vcc, and the connecting wires are led out above the high-concentration P-type doping (23) and the high-concentration N-type doping (28) and connected together and connected to an IO end.
Compared with the prior art, the invention has the following advantages:
(1) according to the invention, the outer protection ring of the existing high-voltage NLDMOS is connected with the non-metal silicide polysilicon resistor in series and then connected to the power supply Vcc, so that the voltage which directly falls on the collector of the parasitic NPN triode (the outer protection ring of an N-type device) after the parasitic NPN triode is impacted and mis-triggered by the negative current of the IO end once can be reduced, the parasitic NPN triode is prevented from entering a maintained conducting state after being mis-triggered, the latching capability of a negative current impact prevention mode of the high-voltage IO end is improved, the width of the inner protection ring of the high-voltage NLDMOS is reduced, and the.
(2) The resistance value of the non-metal silicification polysilicon resistor influences the negative current impact prevention mode latching capacity of the IO end of the high-voltage integrated circuit.
(3) The width (GW1) of an inner protection ring (NGR1) of the high-voltage device influences the latching capacity of an IO end of a high-voltage integrated circuit for preventing negative current impact modes.
Drawings
FIG. 1 is a block diagram of a guard ring structure of a conventional prior art high voltage integrated circuit;
FIG. 2 is a diagram of the relationship between the negative current impact mode latch-up prevention capability and the inner guard ring width of a conventional guard ring structure of a high voltage integrated circuit in the prior art;
FIG. 3 is a block diagram of another prior art high voltage integrated circuit guard ring structure;
FIG. 4 is a block diagram of another prior art high voltage integrated circuit guard ring structure;
FIG. 5 is a circuit diagram of a protection ring for improving the negative current latch-up prevention capability of a high voltage integrated circuit according to the present invention;
FIG. 6 is a flowchart illustrating a method for implementing a protection ring for improving negative current latch prevention capability of a high voltage integrated circuit according to the present invention;
fig. 7 is a schematic view of an application scenario of the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 5 is a circuit diagram of a protection ring for improving the negative current latch-up prevention capability of a high voltage integrated circuit according to the present invention. As shown in fig. 5, the protection ring for improving the negative current latch-up prevention capability of the high voltage integrated circuit of the present invention comprises: a plurality of Shallow Trench Isolation layers (STI) 10, high-concentration P-type dopants (P +)22, high-concentration P-type dopants (P +)23, high-concentration N-type dopants (N +)24, high-concentration P-type dopants (P +)25, P-type diffusion regions (Pdrift)40, high-concentration N-type dopants (N +)26, high-concentration P-type dopants (P +)27, high-concentration N-type dopants (N +)28, high-concentration N-type dopants (N +)29, N-type diffusion regions (Ndrift)50, first high-voltage N-wells (HVNW)60, second high-voltage N-wells (HVNW)61, first high-voltage P-wells (HVPW)70, second high-voltage P-wells (HVNW) 71, P-type substrates (P-Sub)80, first gates 30, second gates 31, and resistors R connected to the high-concentration N-type dopants (N +) 26.
The whole guard ring structure is placed on a P-type substrate (P-Sub)80, and two kinds of high-voltage wells are generated in the P-type substrate (P-Sub) 80: a High Voltage N Well (HVNW)60/61 and a High Voltage P Well (HVPW)70/71, two for each high voltage well, wherein the first High Voltage N Well (HVNW)60 is formed on the left side of the P-type substrate (P-Sub)80, the first High Voltage P Well (HVPW)70 is formed on the right side of the P-type substrate (P-Sub)80, the second High Voltage P Well (HVPW)71 is on the right side of the first High Voltage N Well (HVNW)60, the second High Voltage N Well (HVNW)61 is on the right side of the second High Voltage P Well (HVPW)71, and the first High Voltage P Well (HVPW)70 is on the right side of the second High Voltage N Well (HVNW) 61; a Shallow Trench Isolation (STI) 10 is used for isolating the space between the upper right side of the first High Voltage N Well (HVNW)60 and the upper left side of the second High Voltage P Well (HVPW)71, the space between the upper right side of the second High Voltage P Well (HVPW)71 and the upper left side of the second High Voltage N Well (HVNW)61, and the space between the upper right side of the second High Voltage N Well (HVNW)61 and the upper left side of the first High Voltage P Well (HVPW) 70;
the P-type diffusion region (Pdrift)40 is disposed in the middle of the upper portion of the first High Voltage N Well (HVNW)60, the high concentration P-type dopant (P +)22 is disposed on the left side of the upper portion of the first High Voltage N Well (HVNW)60, and the first High Voltage N Well (HVNW)60 is not in contact with other region boundaries around the high concentration P-type dopant (P +) 22; the high-concentration P-type doping (P +)23 is disposed in an upper region of the P-type diffusion region (Pdrift)40, a Shallow Trench Isolation (STI) 10 is disposed on the left side of the high-concentration P-type doping (P +)23, and the P-type diffusion region (Pdrift)40 is disposed on the left side of the Shallow Trench Isolation (STI) 10 and the right side of the high-concentration P-type doping (P +)23, i.e., surrounded by the P-type diffusion region (Pdrift) 40; the high-concentration N-type doping (N +)24 is arranged on the right side of the upper part of a high-voltage N well (HVNW)60, the right side of the high-concentration N-type doping (N +) is a Shallow Trench Isolation layer (STI) 10 for separating a second high-voltage P well (71) from a first high-voltage N well (60), and the left side of the high-concentration N-type doping (N +) is isolated from the right side of a P-type diffusion region (Pdrift)40 in the first high-voltage N well (60) by the Shallow Trench Isolation layer (STI, Shallow Trench Isolation) 10;
the high-concentration P-type doping (P +)25 is located above the second high-voltage P-well (HVPW)71, and both sides thereof are Shallow Trench Isolation (STI) layers 10 for Isolation; the high concentration N-type doping (N +)26 is located above the second High Voltage N Well (HVNW)61, and both sides thereof are Shallow Trench Isolation (STI) 10 for isolation;
an N-type diffusion region (Ndrift)50 is arranged in the middle of the upper part of a first high-voltage P well (HVPW)70, high-concentration N-type doping (N +)29 is arranged on the right side of the upper part of the first high-voltage P well (HVPW)70, and the first high-voltage P well (HVPW)70 is not in contact with the boundary of other regions around the high-concentration N-type doping (N +) 29; the high concentration N-type dopant (N +)28 is disposed in an upper region of the N-type diffusion region (Ndrift)50, and a Shallow Trench Isolation (STI) 10 is disposed at the right side of the high concentration N-type dopant (N +)28, and the N-type diffusion region (Ndrift)50 is disposed at the right side of the Shallow Trench Isolation (STI) 10 and the left side of the high concentration N-type dopant (N +)28, i.e., surrounded by the N-type diffusion region (Ndrift) 50; the high-concentration P-type doping (P +)27 is arranged on the left side of the upper part of the first high-voltage P well (HVPW)70, the left side of the high-concentration P-type doping (P +) is a Shallow Trench Isolation layer (STI) 10 for isolating the second high-voltage N well (61) from the first high-voltage P well (70), and the right side of the high-concentration P-type doping (P +) is isolated from the left side of the N-type diffusion region (Ndrift)50 in the first high-voltage P well (70) by the Shallow Trench Isolation layer (STI) 10;
the first gate 30 is located over the right side of the high concentration P-type doping (P +)22 and over the left side of the P-type diffusion region (Pdrift) 40; a second gate 31 is located over the left side of the high concentration N-type doping (N +)29 and over the right side of the N-type diffusion region (Ndrift) 50;
connecting wires are respectively led out above the high-concentration P-type doping (P +)22 and the high-concentration N-type doping (N +)29 and are respectively connected with a power supply end Vcc and a ground end Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (N +)24 (width GW1), the high-concentration P-type doping (P +)25 (width GW2) and the high-concentration P-type doping (P +)27 (width GW1), and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; a connecting wire is led out above the high-concentration N-type doping (N +)26 (the width GW2), connected with a resistor R and then connected with a power supply Vcc, and the connecting wires are led out above the high-concentration P-type doping (P +)23 and the high-concentration N-type doping (N +)28, connected together and connected to a bonding pad, namely an IO terminal.
The high-concentration N-type doping (N +)26, the first high-voltage P-well (HVPW)70 and the high-concentration N-type doping (N +)28 form a parasitic NPN triode structure, the high-concentration N-type doping (28) forms an emitter of the parasitic NPN triode, the high-concentration N-type doping (26) forms a collector of the parasitic NPN triode, and the first high-voltage P-well (70) forms a base of the parasitic NPN triode.
In the embodiment of the present invention, the resistor R is a Non-silicided polysilicon resistor (Non-silicided polysilicon) with a resistance value range of 100-5000 ohm.
The invention relates to a method for realizing a protection ring for improving the negative current latching prevention capability of a high-voltage integrated circuit, which is characterized in that a non-metal silicification polysilicon resistor is connected in series with high-concentration N-type doping (26) of the existing protection ring structure and then connected to a power supply Vcc (Vcc) so as to prevent a parasitic NPN triode from entering a state of maintaining conduction after being triggered by mistake, as shown in figure 6, the method comprises the following specific implementation steps:
step S1, a semiconductor substrate is provided, and a first high voltage N well (60), a second high voltage P well (71), a second high voltage N well (61), and a first high voltage P well (70) are sequentially formed in the semiconductor substrate, and the upper portions of the high voltage N wells are isolated by a shallow trench isolation layer (10).
Step S2, sequentially arranging a high-concentration P-type doping (22), a P-type diffusion region (40) and a high-concentration N-type doping (24) on the upper portion of a first high-voltage N well (HVNW)60, arranging a shallow trench isolation layer (10) isolation between the P-type diffusion region (40) and the high-concentration N-type doping (24), arranging a high-concentration P-type doping (25) and a high-concentration N-type doping (26) on the upper portions of a second high-voltage P well (71) and a second high-voltage N well (61) respectively, sequentially arranging a high-concentration P-type doping (27), an N-type diffusion region (50) and a high-concentration N-type doping (29) on the upper portion of the first high-voltage P well (70), and arranging a shallow trench isolation layer (10) isolation between the high-concentration P-type doping (27) and the N-type diffusion region (50), a high-concentration N-type doping (28) is arranged at the upper part in the N-type diffusion region (50), and a high-concentration P-type doping (27) is arranged between a shallow channel isolation layer (10) for separating the second high-voltage N well (61) and the first high-voltage P well (70) and a shallow channel isolation layer (10) on the left side of the N-type diffusion region (50) in the first high-voltage P well (70);
in step S3, a first gate (30) is disposed over the high concentration P-type dopant (22) and the P-type diffusion region (40), and a second gate (31) is disposed over the high concentration N-type dopant (29) and the N-type diffusion region (50).
Step S4, leading out connecting wires above the high-concentration P-type doping (22) and the high-concentration N-type doping (29), and respectively connecting the connecting wires with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (24), the high-concentration P-type doping (25) and the high-concentration P-type doping (27) and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; and a connecting wire is led out above the high-concentration N-type doping (26), connected with a resistor R and then connected to a power supply Vcc, and is led out above the high-concentration P-type doping (23) and the high-concentration N-type doping (28), connected together and connected to an IO end.
In application, as shown in fig. 7, in order to protect the IO port, the ground terminal Vss of the protection ring structure of the present invention is connected to the high voltage power supply ground terminal HV _ Vss of the chip to which the present invention is applied, the power supply terminal Vcc of the protection ring structure of the present invention is connected to the high voltage power supply terminal HV _ Vdd of the chip to which the present invention is applied, and the IO port of the protection ring structure of the present invention is connected to the input/output terminal of the chip to which the present invention is applied, so as to protect the input; or the Power supply voltage is not connected with the input end and the output end of the chip and is bridged between the high-voltage Power supply end HV _ Vdd and the high-voltage Power supply ground end HV _ Vss of the chip to carry out amplitude limiting protection (Power Clamp).
Therefore, according to the invention, a Non-metal silicide polysilicon resistor (Non-silicon doped polysilicon resistor) is connected in series with the high-concentration N-type doped device (N +)26 of the outer protection ring of the existing high-voltage NLDMOS, and then the high-concentration N-type doped device is connected to a power supply Vcc, so that the voltage of a collector (the outer protection ring N +26 of the N protection ring of the parasitic NPN triode (NLDMOS Drain [ high-concentration N + doped (N +)28]/HVPW70/NGR2) of the parasitic NPN triode (the high-concentration N + doped device (N +)28[ NLDMOS Drain ]/HVPW70/NGR2) after being erroneously triggered by negative current impact of an IO end can be reduced, the parasitic NPN type triode is prevented from entering a maintained conduction state after being erroneously triggered, the latching capability of a negative current impact prevention mode of the high-voltage IO end is improved, the width of the protection ring in the high-voltage NLDMOS is reduced, and the layout area.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A guard ring for enhancing negative current latch-up prevention capability of a high voltage integrated circuit, comprising:
a semiconductor substrate (80);
a first high-voltage N well (60), a second high-voltage P well (71), a second high-voltage N well (61) and a first high-voltage P well (70) which are sequentially generated in the semiconductor substrate (80), wherein shallow trench isolation layers (10) are used for isolating the upper parts of the high-voltage N wells;
high concentration P type doping (22), P type diffusion region (40) and high concentration N type doping (24) set gradually in first high pressure N trap (60) upper portion, upper portion sets up high concentration P type doping (23) in P type diffusion region (40), isolate with shallow trench isolation layer (10) between P type diffusion region (40) and the high concentration N type doping (24), high concentration N type doping (24) opposite side is shallow trench isolation layer (10) for separating first high pressure N trap (60) and second high pressure P trap (71), high concentration P type doping (25), high concentration N type doping (26) set respectively in second high pressure P trap (71), second high pressure N trap (61) upper portion, high concentration P type doping (27), N type diffusion region (50) and high concentration N type doping (29) set gradually in first high pressure P trap (70) upper portion, the high-concentration P-type doping (27) and the N-type diffusion region (50) are isolated by a shallow trench isolation layer (10), the high-concentration N-type doping (28) is arranged at the upper part in the N-type diffusion region (50), and the high-concentration P-type doping (27) is arranged between the shallow trench isolation layer (10) for separating the second high-voltage N well (61) and the first high-voltage P well (70) and the shallow trench isolation layer (10) on the left side of the N-type diffusion region (50) in the first high-voltage P well (70);
a first grid (30) is arranged above the position between the high-concentration P-type doping region (22) and the P-type diffusion region (40), and a second grid (31) is arranged above the position between the high-concentration N-type doping region (29) and the N-type diffusion region (50);
connecting wires are respectively led out above the high-concentration P-type doping (22) and the high-concentration N-type doping (29) and are respectively connected with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (24), the high-concentration P-type doping (25) and the high-concentration P-type doping (27) and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; and a connecting wire is led out above the high-concentration N-type doping (26), connected with a resistor R and then connected to a power supply Vcc, and is led out above the high-concentration P-type doping (23) and the high-concentration N-type doping (28), connected together and connected to an IO end.
2. The protection ring for improving the negative current latch-up prevention capability of the high-voltage integrated circuit as claimed in claim 1, wherein: the resistor R is a nonmetal silicification polysilicon resistor.
3. The protection ring for improving the negative current latch-up prevention capability of the high-voltage integrated circuit as claimed in claim 2, wherein: the resistance range of the resistor R is 100-5000 ohm.
4. The protection ring of claim 3, wherein the protection ring is capable of improving negative current latch-up prevention capability of a high voltage integrated circuit, and comprises: and sequentially generating the first high-voltage N well (60), the second high-voltage P well (71), the second high-voltage N well (61) and the first high-voltage P well (70) from left to right in the semiconductor substrate (80).
5. The protection ring for improving the negative current latch-up prevention capability of the high-voltage integrated circuit as claimed in claim 4, wherein: and arranging a shallow trench isolation layer (10) in the P-type diffusion region (40) on the left side of the high-concentration P-type doping (23).
6. The protection ring for improving the negative current latch-up prevention capability of the high voltage integrated circuit as claimed in claim 5, wherein: and arranging a shallow trench isolation layer (10) in the N-type diffusion region (50) on the right side of the high-concentration N-type doping (28), wherein the high-concentration N-type doping (26), the first high-voltage P well (70) and the high-concentration N-type doping (28) form a parasitic NPN triode structure, the high-concentration N-type doping (28) forms an emitting electrode of the parasitic NPN triode, the high-concentration N-type doping (26) forms a collecting electrode of the parasitic NPN triode, and the first high-voltage P well (70) forms a base electrode of the parasitic NPN triode.
7. The protection ring for improving the negative current latch-up prevention capability of the high-voltage integrated circuit as claimed in claim 1, wherein: the high-concentration P-type doping (22), the P-type diffusion region (40) and the high-concentration N-type doping (24) are sequentially arranged on the upper portion of the first high-voltage N well (60) from left to right.
8. The protection ring for improving the negative current latch-up prevention capability of the high-voltage integrated circuit as claimed in claim 1, wherein: the high-concentration P-type doping (27), the N-type diffusion region (50) and the high-concentration N-type doping (29) are sequentially arranged on the upper portion of the first high-voltage P well (70) from left to right.
9. A method for realizing a protection ring for improving the negative current latching prevention capability of a high-voltage integrated circuit is characterized by comprising the following steps: a non-metal silicide polysilicon resistor is connected in series with a high-concentration N-type doping (26) of the existing protective ring structure and then connected to a power supply Vcc, so that a parasitic NPN triode is prevented from entering a state of maintaining conduction after being triggered by mistake.
10. The method of claim 9, wherein the method comprises the steps of:
step S1, a semiconductor substrate is provided, and a first high voltage N well (60), a second high voltage P well (71), a second high voltage N well (61), and a first high voltage P well (70) are sequentially formed in the semiconductor substrate, and the upper portions of the high voltage N wells are isolated by a shallow trench isolation layer (10).
Step S2, sequentially arranging a high-concentration P-type doping (22), a P-type diffusion region (40) and a high-concentration N-type doping (24) on the upper portion of a first high-voltage N well (HVNW)60, arranging a shallow trench isolation layer (10) isolation between the P-type diffusion region (40) and the high-concentration N-type doping (24), arranging a high-concentration P-type doping (25) and a high-concentration N-type doping (26) on the upper portions of a second high-voltage P well (71) and a second high-voltage N well (61) respectively, sequentially arranging a high-concentration P-type doping (27), an N-type diffusion region (50) and a high-concentration N-type doping (29) on the upper portion of the first high-voltage P well (70), and arranging a shallow trench isolation layer (10) isolation between the high-concentration P-type doping (27) and the N-type diffusion region (50), a high-concentration N-type doping (28) is arranged at the upper part in the N-type diffusion region (50), and a high-concentration P-type doping (27) is arranged between a shallow channel isolation layer (10) for separating the second high-voltage N well (61) and the first high-voltage P well (70) and a shallow channel isolation layer (10) on the left side of the N-type diffusion region (50) in the first high-voltage P well (70);
in step S3, a first gate (30) is disposed over the high concentration P-type dopant (22) and the P-type diffusion region (40), and a second gate (31) is disposed over the high concentration N-type dopant (29) and the N-type diffusion region (50).
Step S4, leading out connecting wires above the high-concentration P-type doping (22) and the high-concentration N-type doping (29), and respectively connecting the connecting wires with a power supply Vcc and a ground Vss; connecting wires PGR1, PGR2 and NGR1 are led out above the high-concentration N-type doping (24), the high-concentration P-type doping (25) and the high-concentration P-type doping (27) and are respectively connected with a power supply Vcc, a ground Vss and a ground Vss; and a connecting wire is led out above the high-concentration N-type doping (26) and connected with the non-metal silicification polysilicon resistor R, then the non-metal silicification polysilicon resistor R is connected with a power supply Vcc, and the connecting wires are led out above the high-concentration P-type doping (23) and the high-concentration N-type doping (28) and connected together and connected to an IO end.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023279562A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Identification method for latch-up structure |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230023A (en) * | 1998-03-24 | 1999-09-29 | 日本电气株式会社 | Semiconductor device having protective circuit |
| US20040033666A1 (en) * | 2002-08-14 | 2004-02-19 | Williams Richard K. | Isolated complementary MOS devices in epi-less substrate |
| US20050073007A1 (en) * | 2003-10-01 | 2005-04-07 | Fu-Hsin Chen | Ldmos device with isolation guard rings |
| KR20100064262A (en) * | 2008-12-04 | 2010-06-14 | 주식회사 동부하이텍 | A semiconductor device and method for manufacturing the same |
| CN103370789A (en) * | 2011-02-11 | 2013-10-23 | 美国亚德诺半导体公司 | Apparatus and method for protection of electronic circuits operating under high stress conditions |
| US20140061848A1 (en) * | 2012-09-04 | 2014-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Schottky Isolated NMOS for Latch-Up Prevention |
| CN104852646A (en) * | 2014-02-17 | 2015-08-19 | 精工爱普生株式会社 | Circuit device and electronic apparatus |
| US20170278839A1 (en) * | 2016-03-24 | 2017-09-28 | Nxp B.V. | Electrostatic discharge protection using a guard region |
| CN108091650A (en) * | 2017-12-28 | 2018-05-29 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN109037203A (en) * | 2018-07-13 | 2018-12-18 | 上海华力微电子有限公司 | Thyristor type esd protection structure and implementation method |
| CN113948567A (en) * | 2020-07-17 | 2022-01-18 | 和舰芯片制造(苏州)股份有限公司 | Device for improving breakdown voltage of LDMOS high-voltage side and preparation method thereof |
-
2020
- 2020-07-17 CN CN202010693328.1A patent/CN111799256B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230023A (en) * | 1998-03-24 | 1999-09-29 | 日本电气株式会社 | Semiconductor device having protective circuit |
| US6469354B1 (en) * | 1998-03-24 | 2002-10-22 | Nec Corporation | Semiconductor device having a protective circuit |
| US20040033666A1 (en) * | 2002-08-14 | 2004-02-19 | Williams Richard K. | Isolated complementary MOS devices in epi-less substrate |
| US20050073007A1 (en) * | 2003-10-01 | 2005-04-07 | Fu-Hsin Chen | Ldmos device with isolation guard rings |
| KR20100064262A (en) * | 2008-12-04 | 2010-06-14 | 주식회사 동부하이텍 | A semiconductor device and method for manufacturing the same |
| CN103370789A (en) * | 2011-02-11 | 2013-10-23 | 美国亚德诺半导体公司 | Apparatus and method for protection of electronic circuits operating under high stress conditions |
| US20140061848A1 (en) * | 2012-09-04 | 2014-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Schottky Isolated NMOS for Latch-Up Prevention |
| CN104852646A (en) * | 2014-02-17 | 2015-08-19 | 精工爱普生株式会社 | Circuit device and electronic apparatus |
| US20170278839A1 (en) * | 2016-03-24 | 2017-09-28 | Nxp B.V. | Electrostatic discharge protection using a guard region |
| CN108091650A (en) * | 2017-12-28 | 2018-05-29 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
| CN109037203A (en) * | 2018-07-13 | 2018-12-18 | 上海华力微电子有限公司 | Thyristor type esd protection structure and implementation method |
| CN113948567A (en) * | 2020-07-17 | 2022-01-18 | 和舰芯片制造(苏州)股份有限公司 | Device for improving breakdown voltage of LDMOS high-voltage side and preparation method thereof |
Non-Patent Citations (2)
| Title |
|---|
| SHEN-LI CHEN; YI-HAO CHIU; YU-LIN JHOU; PEI-LIN WU; PO-LIN LIN; YU-JEN CHEN: "ESD-Reliability Enhancement in a High-Voltage 60 V Square-Type PLDMOS by the Guard-Ring Engineering" * |
| 宋慧滨;唐晨;易扬波;孙伟锋: "功率集成电路中一种抗闩锁方法研究" * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023279562A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Identification method for latch-up structure |
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