CN116207090A - Electrostatic discharge protection structure - Google Patents

Electrostatic discharge protection structure Download PDF

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Publication number
CN116207090A
CN116207090A CN202111443893.3A CN202111443893A CN116207090A CN 116207090 A CN116207090 A CN 116207090A CN 202111443893 A CN202111443893 A CN 202111443893A CN 116207090 A CN116207090 A CN 116207090A
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region
well region
protection structure
esd
substrate
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梁旦业
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to CN202111443893.3A priority Critical patent/CN116207090A/en
Priority to PCT/CN2022/115047 priority patent/WO2023098174A1/en
Publication of CN116207090A publication Critical patent/CN116207090A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides an electrostatic discharge protection structure. In the electrostatic discharge protection structure, a substrate has a first conductive type; the source region and the drain region each have a second conductivity type opposite to the first conductivity type and are spaced apart in the substrate; the grid structure is arranged on the substrate between the source electrode region and the drain electrode region; the first doping region is provided with a first conductivity type, is arranged in the substrate at one side of the drain region far away from the gate structure, is spaced from the drain region, and has a doping concentration greater than that of the substrate; the source region and the gate structure are electrically connected to the first potential terminal in common, and the drain region is electrically connected to the second potential terminal. The addition of the first doped region can reduce the avalanche breakdown voltage of the collector junction of the parasitic NPN transistor of the electrostatic discharge protection structure, and is beneficial to reducing the trigger voltage of the electrostatic discharge protection structure.

Description

Electrostatic discharge protection structure
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an electrostatic discharge protection structure.
Background
In chip design, electrostatic protection is related to the reliability of the chip. With the increasing demand for electrostatic protection, there is a need to continuously optimize the protection structure on the chip responsible for electrostatic discharge (ESD).
Fig. 1 shows the structure of an ESD protection network at the I/O port and power clamp. As shown in fig. 1, if a GGNMOS (Gate group NMOS) device with the same operating voltage modified by 5VNMOS is selected for the ESD3 of the ESD3, the trigger voltages of the ESD3 and the MOS transistor M3 of the ESD3 are the same, so that the ESD3 cannot protect the M3. Therefore, there is a need for an electrostatic discharge protection structure using low trigger voltages; meanwhile, the ESD5 is used as a power clamp protection, and an ESD protection structure with better compatibility is required for cost reasons, but an ESD protection structure with low trigger voltage is also required. In addition, from the viewpoints of cost reduction and area reduction, the electrostatic discharge protection structure is required to have strong robustness. From the latch-up protection point of view, the esd protection structure is required to have a high sustain voltage.
Disclosure of Invention
In order to reduce the trigger voltage of the electrostatic discharge protection structure, the invention provides an electrostatic discharge protection structure.
The electrostatic discharge protection structure provided by the invention comprises: a substrate having a first conductivity type; a source region and a drain region, each having a second conductivity type opposite to the first conductivity type, disposed in the substrate at intervals; a gate structure disposed on the substrate between the source region and the drain region, the source region and the gate structure being electrically connected together to a first potential terminal, the drain region being electrically connected to a second potential terminal; the first doped region is of a first conductivity type, is arranged in the substrate at one side of the drain region far away from the gate structure in a floating mode, is arranged between the first doped region and the drain region, and has a doping concentration greater than that of the substrate.
Optionally, a distance between the first doped region and the drain region is set according to a magnitude of a trigger voltage required by the esd protection structure.
Optionally, the electrostatic discharge protection structure includes a second doped region having the first conductivity type disposed in the substrate between the gate structure and the source region, the second doped region being in a floating arrangement.
Optionally, the electrostatic discharge protection structure includes an SAB layer covering the upper surface of the substrate of the first doped region and the second doped region.
Optionally, the electrostatic discharge protection structure comprises a first isolation structure located in the substrate between the gate structure and the source region.
Optionally, the electrostatic discharge protection structure includes a deep well region having a second conductivity type, the deep well region being formed in the substrate; a first well region with a first conductivity type is formed on top of the deep well region, the source region, the drain region and the first doped region are formed on top of the first well region, and the doping concentration of the first doped region is greater than that of the first well region.
Optionally, a first well region lead-out region with a first conductivity type is formed on the top in the first well region, the first well region lead-out region is located at one side of the source region away from the gate structure, and the first well region lead-out region is electrically connected to the first potential end.
Optionally, the esd protection structure includes a second well region of a second conductivity type, the second well region being located on top of the deep well region and surrounding the first well region; a second well region leading-out region with a second conductivity type is formed at the top in the second well region, and the doping concentration of the second well region leading-out region is larger than that of the second well region; the second well region leading-out region is electrically connected to a third potential end; an isolation structure is arranged between the first well region leading-out region and the source region; an isolation structure is arranged between the first well region leading-out region and the second well region leading-out region.
Optionally, the electrostatic discharge protection structure includes a third well region having the first conductivity type, the doping concentration of the third well region being greater than the doping concentration of the substrate; a third well region leading-out region is formed at the top in the third well region, and the third well region leading-out region has a first conductivity type and has a doping concentration larger than that of the third well region; the third well region leading-out region is electrically connected to the fourth potential end.
Optionally, the third potential end has a potential different from the potentials of the first potential end, the second potential end and the fourth potential end; and the first potential end and the fourth potential end are the same or different in potential.
Optionally, the first potential end is a cathode end, the second potential end is an anode end, and a potential of the anode end is different from a potential of the cathode end.
Optionally, the electrostatic discharge protection structure is a GGNMOS.
Optionally, the esd protection structure includes at least two interdigital units, each of which includes one of the gate structures, one of the source regions, and one of the drain regions; every two adjacent interdigital units are in a pair, the drain electrode regions of one pair of interdigital units are close to each other, the first doped region is positioned between the two drain electrode regions close to each other, and the pair of interdigital units are axisymmetric relative to the corresponding first doped region.
In the electrostatic discharge protection structure provided by the invention, the first doped region with the first conductivity type is arranged in the substrate at one side of the drain region with the second conductivity type, which is far away from the gate structure, the first doped region and the drain region are arranged at intervals and are arranged in a floating manner, and the doping concentration of the first doped region is larger than that of the substrate. The addition of the first doped region can reduce the avalanche breakdown voltage of the collector junction (i.e., the PN junction formed between the drain region and the substrate) of the parasitic NPN transistor in the electrostatic discharge protection structure, so that the trigger voltage of the electrostatic discharge protection structure can be reduced, and compared with the traditional electrostatic discharge protection structure (such as the traditional GGNMOS), the electrostatic discharge protection structure has higher ESD robustness under the same chip area.
Drawings
Fig. 1 is a structure of an ESD protection network at the I/O port and power clamp.
Fig. 2 is a schematic cross-sectional view of a GGNMOS device.
Fig. 3 is a schematic diagram of the GGNMOS device and its internal equivalent triode circuit shown in fig. 2.
Fig. 4 is a schematic cross-sectional view of a ggnmos_p+ device.
FIG. 5 is an IV plot of a TLP test for GGNMOS device and GGNMOS_P+ device of the same chip area.
Fig. 6 is a current density simulation diagram of a GGNMOS device after a parasitic NPN junction is turned on.
Fig. 7 is a current density simulation diagram after the parasitic NPN junction of the ggnmos_p+ device is turned on.
Fig. 8 is a TLP test IV graph of a hanging resistance experiment for GGNMOS devices.
Fig. 9 is a graph of TLP test IV for a string resistance experiment for ggnmos_p+ devices.
Fig. 10 is a schematic cross-sectional view of a ggnmos_p+ device with a P-type ESD implant.
Fig. 11 is a schematic diagram of the current path after the ggnmos_p+ device without the P-type ESD implant is turned on.
Fig. 12 is a schematic diagram of the current path after turn-on of a ggnmos_p+ device with a P-type ESD implant.
Fig. 13 is an IV plot of TLP testing for different ggnmos_p+ devices incorporating P-type ESD implant regions of different implant conditions.
Fig. 14 is a schematic cross-sectional view of an esd protection structure according to an embodiment of the invention.
Fig. 15 is a schematic cross-sectional view of an esd protection structure according to another embodiment of the invention.
Reference numerals illustrate: 10-a substrate; a 100-interdigital unit; a 101-gate structure; 102-drain region; 103-source regions; 104-a first doped region; 105-a second doped region; 106-a first well region extraction region; 107-a second isolation structure; a 108-SAB layer; 109-a first well region; 110-a second well region; 111-a second well region lead-out region; 112-a third well region; 113-a third well region exit region; 114-deep well region; 115-a first isolation structure; 116-P type ESD implant.
Detailed Description
The GGNMOS device for ESD protection according to the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 2 is a schematic cross-sectional view of a GGNMOS device. As shown in fig. 2, in the GGNMOS device, a Deep N-well (deep_nwell) is disposed in a P-type substrate 10 (p_substrate), a first well region 109 (Pwell) is disposed in the Deep N-well, at least two interdigital units 100 are formed in and above the first well region 109, and each interdigital unit 100 includes a gate structure 101 formed on the substrate 10, and a source region 103 and a drain region 102 formed in the substrate 10 and respectively located at both sides of the gate structure 101.
Fig. 3 is a schematic diagram of the GGNMOS device and its internal equivalent triode circuit shown in fig. 2. Referring to fig. 2 and 3, the GGNMOS device forms a parasitic NPN transistor Q between the drain region 102, the first well region 109, and the source region 103 during operation. When positive ESD pulse occurs at the Anode terminal (Anode), N+/Pwell junction between the drain region 102 of the drain terminal and the first well region 109 is reversely biased, namely, the collecting junction of Q is reversely biased; when the ESD pulse voltage reaches a certain level, the Q is subjected to avalanche breakdown to generate avalanche current; avalanche current flows through the well resistor R to the first well region extraction region 106, and the potential at the base b of q is raised; when the avalanche current continues to increase, the potential at the base b is raised to reach the forward bias voltage drop of the emitter junction of Q, the whole Q is in an amplified state, an emitter e current is formed, and the GGNMOS device is triggered; since the emitter e current in the Q amplified state is larger than the current flowing out through the first well region outlet region 106 outside the source region (source), a negative resistance region (snapback region, i.e., the back-throw region) appears on the current-voltage (IV) curve of the corresponding Transmission Line Pulse (TLP) test, and the ESD current at the anode terminal will be mainly discharged from Q.
As can be seen from the above analysis, the trigger voltage of the GGNMOS device shown in fig. 2 is determined by the avalanche breakdown voltage of the collector junction of the parasitic NPN transistor Q (i.e., the n+/Pwell PN junction between the drain region 102 and the first well region 109). Accordingly, an improved GGNMOS device reduces the Breakdown Voltage (BV) of Q by adding a p+ ESD implant region below the drain region 102, thereby reducing the trigger voltage of the GGNMOS device. In addition, the triggering of the GGNMOS device can be accelerated by introducing the current generated by other ways, wherein one of the common methods is to couple a certain voltage on the gate structure 101 of the GGNMOS device to introduce the channel current, so that the purpose that the triggering voltage is lower than the breakdown voltage can be achieved.
Fig. 4 is a schematic cross-sectional view of a ggnmos_p+ device. As shown in fig. 4, each of the interdigital cells 100 also includes a gate structure 101 formed on the substrate 10, and a source region 103 and a drain region 102 formed in the substrate 10 and located on both sides of the gate structure 101, respectively, as compared to the GGNMOS structure shown in fig. 2, and the ggnmos_p+ device is formed with a second doped region 105 (P-type) between the gate structure 101 and the source region 103 of each interdigital cell 100, except for the ggnmos_p+ device.
TLP testing was performed on GGNMOS devices and ggnmos_p+ devices of the same chip area, and the test results are shown in fig. 5, which shows that ggnmos_p+ devices have higher over-current capability than GGNMOS devices. Specifically, in the ggnmos_p+ device, after the parasitic NPN junction in each interdigital cell 100 is turned on, the addition of the second doped region 105 at the source terminal in the ggnmos_p+ device causes the electronic current path to go into the first well region 109. Fig. 6 is a current density simulation diagram of a GGNMOS device after a parasitic NPN junction is turned on. Fig. 7 is a current density simulation diagram after the parasitic NPN junction of the ggnmos_p+ device is turned on. As can be seen from comparing fig. 6 and fig. 7, the added second doped region 105 in the ggnmos_p+ device helps to improve the current path distribution, and no current aggregation effect is formed near the surface of the channel region, and referring to fig. 5, the secondary breakdown point may be delayed, which is shown to be more ESD robust for the ggnmos_p+ device. The ggnmos_p+ structure also has the advantage of high sustain voltage because the current path of the ggnmos_p+ device is longer, resulting in an increase in sustain voltage.
For the ggnmos_p+ structure, the source terminal adds the second doped region 105, forming a blocking structure for channel current, and even if the gate structure 101 is coupled to a certain voltage through a resistor under an ESD pulse, the channel current cannot be formed. Therefore, the ggnmos_p+ device cannot lower the trigger voltage by introducing the channel current. Fig. 8 and 9 are TLP test IV graphs of a GGNMOS device and a ggnmos_p+ device hanging resistance (Res) experiment for the same die area in the same process. It can be seen in fig. 8 that when the hanging resistor res=160 k ohms (ohm), the GGNMOS device can achieve a reduction in trigger voltage; in contrast, the ggnmos_p+ structure of fig. 9 cannot achieve a reduction in trigger voltage regardless of the hanging resistance.
Fig. 10 is a schematic cross-sectional view of a ggnmos_p+ device with a P-type ESD implant. For lowering the trigger voltage of the ggnmos_p+ device, one idea is to lower the breakdown voltage of the drain, as shown in fig. 10, a common method is to perform a P-type ESD implantation under the drain region 102 to form a P-type ESD implantation region 116 (p_esd_imp). However, in the manufacturing process, the P-type ESD injection region 116 needs to be added to increase the mask for P-type ESD injection, and meanwhile, due to the co-extrusion effect of the P-type ESD injection region 116 and the second doped region 105 at the source end, the area of the electron current distribution of the parasitic NPN junction after the ggnmos_p+ device is turned on is small, and the current concentration effect is easy to occur, so that the thermal breakdown occurs in advance. Fig. 11 is a schematic diagram of the current path after the ggnmos_p+ device without the P-type ESD implant is turned on. Fig. 12 is a schematic diagram of the current path after turn-on of a ggnmos_p+ device with a P-type ESD implant. As can be seen from fig. 11 and 12, after adding the P-type ESD implant 116, the ggnmos_p+ device current can be distributed in a smaller area.
Fig. 13 is an IV curve of TLP test for different ggnmos_p+ devices incorporating P-type ESD implant regions of different implant conditions. The P-type ESD injection region was subjected to different dose and energy slicing comparison, and actual current flow verification shows that, as shown in fig. 13, the trigger voltage of the ggnmos_p+ device with the P-type ESD injection region 116 is reduced to different extents, but the current capability is severely degraded compared with that of the ggnmos_p+ device without the P-type ESD injection region (no_p_esd_imp). That is, the trigger voltage of the ggnmos_p+ device with the P-type ESD implant 116 can be reduced, but high over-current capability and high sustain voltage cannot be obtained.
Therefore, the ggnmos_p+ device has the advantages of high over-current capability and high sustain voltage, but the trigger voltage cannot be reduced by introducing channel current, and introducing P-type ESD injection region 116 will result in reduced current capability and increased mask, and increased process manufacturing cost. None of the existing devices achieve low trigger voltages while achieving high over-current capability and high sustain voltage.
In order to reduce the trigger voltage of the ESD protection structure and to maintain the ESD protection structure with high ESD robustness, the following embodiments provide an ESD protection structure with high over-current capability and high sustain voltage.
Fig. 14 is a schematic cross-sectional view of an esd protection structure according to an embodiment of the invention. Fig. 15 is a schematic cross-sectional view of an esd protection structure according to another embodiment of the invention. As shown in fig. 14 and 15, the esd protection structure includes a substrate 10, a source region 103, a drain region 102, a gate structure 101, and a first doped region 104.
The substrate 10 has a first conductivity type. The source region 103 and the drain region 102 each have a second conductivity type opposite to the first conductivity type, and are disposed in the substrate 10 at intervals. A gate structure 101 is disposed on the substrate between the source region 103 and the drain region 102. The first doped region 104 has a first conductivity type, is disposed in the substrate on a side of the drain region 102 away from the gate structure 101, and is spaced apart from the drain region 102, and the doping concentration of the first doped region 104 is greater than the doping concentration of the substrate 10. The source region 103 and the gate structure 101 are electrically connected together to a first potential terminal (Cathode terminal), the drain region 102 is electrically connected to a second potential terminal (Anode region), and the first doped region 104 is arranged to be floating.
The floating arrangement of the first doped region 104 may refer to: the first doped region 104 is not connected to any external circuitry. In this embodiment, the upper surface of the substrate of the first doped region 104 is covered with the SAB layer 108, so as to avoid forming a metal silicide on the upper surface of the substrate of the first doped region 104, and further avoid connecting the first doped region 104 with an external circuit, so as to realize floating arrangement of the first doped region 104. The first doped region 104 can reduce the avalanche breakdown voltage of the collector junction of the parasitic NPN transistor of the esd protection structure, thereby helping to reduce the trigger voltage of the esd protection structure.
In this embodiment, the esd protection structure may be a GGNMOS. In another embodiment, the esd protection structure may be GGPMOS.
In this embodiment, the first conductivity type is P-type, and the second conductivity type is N-type. In another embodiment, the first conductivity type is N-type and the second conductivity type is P-type. The electrostatic discharge protection structure is described below by taking the first conductive type as a P-type and the second conductive type as an N-type as an example.
In one embodiment, as shown in fig. 14, the esd protection structure includes a second doped region 105. The second doped region 105 is arranged floating and has the first conductivity type, and is arranged in the substrate between the gate structure 101 and the source region 103. The floating second doped region 105 is arranged between the gate structure 101 and the source region 103, so that the current path distribution of the electrostatic discharge protection structure can be improved, and a current aggregation effect is not formed near the surface of the channel region, so that a secondary breakdown point appears after the secondary breakdown point, and the ESD robustness of the electrostatic discharge protection structure is enhanced; furthermore, since the second doped region 105 is provided such that a current path when the electrostatic discharge protection structure is turned on is longer, a sustain voltage of the electrostatic discharge protection structure can be increased.
As shown in fig. 14, the SAB layer 108 may cover the upper surfaces of the substrates of the first and second doped regions 104 and 105 and the upper surfaces of the substrates of the source and drain regions 103 and 102. When a metal silicide layer (not shown) is formed on the substrate 10, due to the barrier of the SAB layer 108, metal silicide is formed on the exposed substrate surfaces of the source region 103 and the drain region 102, and metal silicide is not formed on the upper substrate surfaces of the first doped region 104 and the second doped region 105, so that the conductive structure above the substrate 10, such as metal silicide, can be avoided to make the first doped region 104 conductive to the adjacent drain region 102 and the second doped region 105 conductive to the adjacent source region 103, which helps to improve the performance of the esd protection structure. However, the SAB layer 108 may cover other areas of the substrate 10, and the exposed upper surface of the substrate 10, which is not covered by the SAB layer, may be formed with a metal silicide layer.
In another embodiment, as shown in fig. 15, the esd protection structure may include a first isolation structure 115, where the first isolation structure 115 is located in the substrate between the gate structure 101 and the source region 103. The first isolation structure 115 functions similarly to the second doped region 105, and may also improve the current path distribution of the ESD protection structure, and helps to avoid current collection effects near the channel region surface, enhance the ESD robustness of the ESD protection structure, and increase the sustain voltage of the ESD protection structure. The first isolation structure 115 may be a Shallow Trench Isolation (STI). But not limited thereto, the first isolation structure 115 may also be a junction isolation or a local oxidation of silicon isolation (LOCOS).
As shown in fig. 14 and 15, the esd protection structure may include a Deep well region 114 (deep_nwell) having a second conductive type, and the Deep well region 114 is formed in the substrate 10 (p_substrate). A first well region 109 (Pwell) having a first conductivity type is formed on top of the deep well region 114, and the source region 103, the drain region 102, and the first doped region 104 are formed on top of the first well region 109, and the doping concentration of the first doped region 104 is greater than that of the first well region 109. Forming the first well region 109 facilitates isolation protection of the esd protection structure. The collector junction of the parasitic NPN transistor Q is the PN junction between the drain region 102 and the first well region 109, i.e., the n+/Pwell PN junction.
It should be noted that, in other embodiments, for the device structure that does not require isolation protection, the source region 103 and the drain region 102 having the second conductivity type, and the first doped region 104 having the first conductivity type may be directly formed in the substrate 10 having the first conductivity type, which helps to simplify the process flow. The collector junction of the parasitic NPN transistor Q is the PN junction between the drain region 102 and the substrate 10, i.e., the PN junction of n+/p_substrate.
As shown in fig. 14 and 15, in the present embodiment, a first well region extraction region 106 having a first conductivity type is formed on the top in the first well region 109, the first well region extraction region 106 is located on a side of the source region 103 away from the gate structure 101, and the first well region extraction region 106 is electrically connected to the first potential terminal (captode).
The esd protection structure may further include a second well region 110 (Nwell) having a second conductivity type, the second well region 110 being located on top of the deep well region 114 and surrounding the first well region 109; a second well region lead-out region 111 having a second conductivity type is formed on top of the second well region 110, and the doping concentration of the second well region lead-out region 111 is greater than that of the second well region 110; the second well region extraction region 111 is electrically connected to a third potential terminal (ISO).
An isolation structure (i.e., a second isolation structure 107) is disposed between the first well region extraction region 106 and the source region 103; an isolation structure is disposed between the first well region extraction region 106 and the second well region extraction region 111. Referring to fig. 15, the depths of the second isolation structures 107, the first isolation structures 115, and the isolation structures between the first well region extraction region 106 and the second well region extraction region 111 may be the same, so that these isolation structures may be formed by the same process, which helps to save manufacturing costs.
As shown in fig. 14 and 15, the esd protection structure may further include a third well region 112 (Pwell) having the first conductivity type, the third well region 112 having a doping concentration greater than that of the substrate 10; a third well region lead-out region 113 is formed on top of the third well region 112, the third well region lead-out region 113 having a first conductivity type and a doping concentration greater than that of the third well region 112; the third well region extraction region 113 is electrically connected to a fourth potential terminal (Psub).
Referring to fig. 14 and 15, the depths of the first well region 109, the second well region 110, and the third well region 112 may be the same. But is not limited thereto, the depths of the first well region 109, the second well region 110, and the third well region 112 may be different.
It should be noted that, the interval K (as shown in fig. 15) between the first doped region 104 and the drain region 102 may be adjusted according to the magnitude of the trigger voltage required by the esd protection structure, and the K value may be different in different processes. When the space between the first doped region 104 and the drain region 102 is fixed without considering the saving of masks, the first doped region 104 may be formed by using a single mask doping, and by increasing the concentration of the first doped region 104, the triggering voltage of the esd protection structure is lower.
In order to save masks, the doping depths and doping concentrations of the first doped region 104 and the second doped region 105, the first well region extraction region 106, and the third well region extraction region 113 may be the same. Namely, the first doped region 104, the second doped region 105, the first well region leading-out region 106 and the third well region leading-out region 113 can be obtained by adopting the same mask doping, which is beneficial to saving the cost; however, compared to the solution where the first doped region 104 is fabricated by using a single mask, the adjustable range of the doping concentration of the first doped region 104 is narrower, and the distance between the first doped region 104 and the drain region 102 needs to be adjusted to obtain the target trigger voltage.
In this embodiment, the third potential end has a different potential from the first potential end, the second potential end, and the fourth potential end. The first potential end and the fourth potential end have the same or different potential. As an example, the first potential terminal is a Cathode terminal (Cathode), the second potential terminal is an Anode terminal (Anode), and the potential of the Anode terminal is different from the potential of the Cathode terminal.
As shown in fig. 14, in this embodiment, the esd protection structure may include at least two interdigital units 100, where each interdigital unit 100 includes one gate structure 101, one source region 103 and one drain region 102. The two adjacent interdigital units 100 are paired, the drain regions 102 of a pair of interdigital units 100 are close to each other and the source regions 103 are far away from each other, the first doped region 104 may be located between the two mutually close drain regions 102 and shared by the two interdigital units 100, and the pair of interdigital units 100 are axisymmetric with respect to the corresponding first doped region 104, so that the chip area occupied by the esd protection structure is reduced. But is not limited thereto, the drain region 102 of each of the inter-digital cells 100 may individually correspond to one of the first doped regions 104.
In the electrostatic discharge protection structure of the present invention, a first doped region 104 having a first conductivity type is disposed in a substrate on a side of a drain region 102 having a second conductivity type, which is far away from a gate structure 101, the first doped region 104 being disposed in a floating manner, is spaced apart from the drain region 102, and a doping concentration of the first doped region 104 is greater than a doping concentration of the substrate 10. The addition of the first doped region 104 can reduce the avalanche breakdown voltage of the collector junction (i.e., the PN junction formed between the drain region 102 and the substrate 10) of the parasitic NPN transistor in the ESD protection structure, so as to reduce the trigger voltage of the ESD protection structure, and compared with the conventional ESD protection structure (e.g., conventional GGNMOS), the ESD robustness of the ESD protection structure of the present invention is higher in the same chip area; in addition, the ESD protection structure of the present invention does not need to introduce the P-type ESD implant region 116 in the ggnmos_p+ device of fig. 10, and the addition of the first doped region 104 does not reduce the current capability of the ESD protection structure.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (13)

1. An electrostatic discharge protection structure, comprising:
a substrate having a first conductivity type;
a source region and a drain region, each having a second conductivity type opposite to the first conductivity type, disposed in the substrate at intervals;
a gate structure disposed on the substrate between the source region and the drain region;
a first doped region of a first conductivity type disposed in the substrate on a side of the drain region remote from the gate structure and spaced apart from the drain region, the first doped region having a doping concentration greater than that of the substrate;
the source electrode region and the gate electrode structure are electrically connected to a first potential end together, the drain electrode region is electrically connected to a second potential end, and the first doped region is arranged in a floating mode.
2. The esd-protection structure of claim 1, wherein a spacing between the first doped region and the drain region is set according to a magnitude of a trigger voltage required by the esd-protection structure.
3. The esd-protection structure of claim 1, comprising a second doped region of the first conductivity type disposed in the substrate between the gate structure and the source region, the second doped region being a floating arrangement.
4. The esd-protection structure of claim 3, comprising an SAB layer covering a top surface of the substrate of the first doped region and the second doped region.
5. The electrostatic discharge protection structure of claim 1 comprising a first isolation structure in a substrate between the gate structure and the source region.
6. The esd-protection structure of claim 1, comprising a deep well region of a second conductivity type formed in the substrate; a first well region with a first conductivity type is formed on top of the deep well region, the source region, the drain region and the first doped region are formed on top of the first well region, and the doping concentration of the first doped region is greater than that of the first well region.
7. The esd-protection structure of claim 6, wherein a top portion within the first well region is formed with a first well region extraction region having a first conductivity type, the first well region extraction region being located on a side of the source region remote from the gate structure, and the first well region extraction region being electrically connected to the first potential terminal.
8. The esd-protection structure of claim 7, comprising a second well region of a second conductivity type located on top of the deep well region and surrounding the first well region; a second well region leading-out region with a second conductivity type is formed at the top in the second well region, and the doping concentration of the second well region leading-out region is larger than that of the second well region; the second well region leading-out region is electrically connected to a third potential end;
an isolation structure is arranged between the first well region leading-out region and the source region; an isolation structure is arranged between the first well region leading-out region and the second well region leading-out region.
9. The esd-protection structure of claim 8, comprising a third well region of the first conductivity type having a doping concentration greater than the doping concentration of the substrate; a third well region leading-out region is formed at the top in the third well region, and the third well region leading-out region has a first conductivity type and has a doping concentration larger than that of the third well region; the third well region leading-out region is electrically connected to the fourth potential end.
10. The esd-protection structure of claim 9, wherein the third potential terminal has a different potential than the first, second and fourth potential terminals; and the first potential end and the fourth potential end are the same or different in potential.
11. The esd-protection structure of claim 1, wherein the first potential terminal is a cathode terminal, the second potential terminal is an anode terminal, and a potential of the anode terminal is different from a potential of the cathode terminal.
12. The esd-protection structure of claim 1, wherein the esd-protection structure is a GGNMOS.
13. The esd-protection structure of claim 1, comprising at least two inter-digital cells, each of the inter-digital cells comprising a gate structure, a source region and a drain region; every two adjacent interdigital units are in a pair, the drain electrode regions of one pair of interdigital units are close to each other, the first doped region is positioned between the two drain electrode regions close to each other, and the pair of interdigital units are axisymmetric relative to the corresponding first doped region.
CN202111443893.3A 2021-11-30 2021-11-30 Electrostatic discharge protection structure Pending CN116207090A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117790500A (en) * 2024-02-19 2024-03-29 成都芯翼科技有限公司 Electrostatic discharge protection structure for M-LVDS port

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US8299532B2 (en) * 2009-08-20 2012-10-30 United Microelectronics Corp. ESD protection device structure
CN107346786B (en) * 2016-05-05 2020-05-01 中芯国际集成电路制造(上海)有限公司 GGNMOS transistor, multi-finger GGNMOS device and circuit
KR20200074581A (en) * 2018-12-17 2020-06-25 에스케이하이닉스 주식회사 Electrostatic Discharge Protection Device
CN110265391B (en) * 2019-06-05 2021-03-16 南京邮电大学 LIGBT type ESD protective device with embedded floating N + region
CN214848631U (en) * 2021-07-08 2021-11-23 湖南静芯微电子技术有限公司 Low-voltage grid unidirectional silicon controlled electrostatic protection device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117790500A (en) * 2024-02-19 2024-03-29 成都芯翼科技有限公司 Electrostatic discharge protection structure for M-LVDS port
CN117790500B (en) * 2024-02-19 2024-05-10 成都芯翼科技有限公司 Electrostatic discharge protection structure for M-LVDS port

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