CN108807362B - Electrostatic discharge protection device and electrostatic discharge method - Google Patents

Electrostatic discharge protection device and electrostatic discharge method Download PDF

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CN108807362B
CN108807362B CN201710281602.2A CN201710281602A CN108807362B CN 108807362 B CN108807362 B CN 108807362B CN 201710281602 A CN201710281602 A CN 201710281602A CN 108807362 B CN108807362 B CN 108807362B
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doped region
region
transistor
doped
well
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CN108807362A (en
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吴明欣
陈信良
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Macronix International Co Ltd
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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Abstract

The invention provides an electrostatic discharge protection element and an electrostatic discharge method. The electrostatic discharge protection element comprises a first well region, a second well region, a fourth doped region, a sixth doped region and a fourth doped region. The first well region and the second well region are located in the substrate. The first well region has a first doped region to a third doped region to form a first transistor. The second well region is located at one side of the first well region. The fourth doped region to the sixth doped region are located in the second well region. The fourth doped region is in contact with the third doped region, and the conductivity type of the fourth doped region is the same as that of the third doped region. The fifth doped region, the second well region and the substrate form a second transistor. The conductivity type of the second transistor is complementary to the conductivity type of the first transistor. The fifth doped region is located between the fourth doped region and the sixth doped region.

Description

Electrostatic discharge protection device and electrostatic discharge method
Technical Field
The present invention relates to an electrostatic discharge protection device, and more particularly, to a silicon controlled rectifier.
Background
Esd protection devices are widely used in electronic devices to prevent the electronic devices from receiving abnormal high voltage and causing damage. A Silicon Controlled Rectifier (SCR) is a common esd protection device, and has the advantages of small area, high voltage resistance, etc.
However, the general scr has the disadvantages of a large trigger voltage (trigger voltage) and a small holding voltage (holding voltage). Therefore, although the abnormal high voltage does not exceed the trigger voltage of the scr, it may still cause damage to the electronic components. In addition, if the holding voltage of the scr is less than the operating voltage of the electronic device, latch-up may be induced when the scr is turned on. Specifically, the scr cannot return to a normal operating state after being triggered, and a large current is momentarily generated. Thus, damage to the electronic components is caused.
Disclosure of Invention
The invention provides an electrostatic discharge protection device and an electrostatic discharge method, which can avoid latch-up effect.
The electrostatic discharge protection element comprises a first well region, a second well region, a fourth doped region, a fifth doped region and a sixth doped region. The first well region is located in the substrate and has a first doped region, a second doped region and a third doped region to form a first transistor. The second well region is located in the substrate at one side of the first well region. The fourth doped region, the fifth doped region and the sixth doped region are located in the second well region. The fourth doped region is in contact with the third doped region, and the conductivity type of the fourth doped region is the same as that of the third doped region. The fifth doped region, the second well region and the substrate form a second transistor. The conductivity type of the second transistor is complementary to the conductivity type of the first transistor. The fifth doped region is located between the fourth doped region and the sixth doped region.
In an embodiment of the invention, the substrate, the first well region, the first doped region and the fifth doped region may have a first conductivity type. The second well region, the second doped region, the third doped region, the fourth doped region and the sixth doped region may have a second conductivity type.
In an embodiment of the invention, the second doped region may be located between the first doped region and the third doped region.
In an embodiment of the invention, a ratio of a width of the third doped region from a side opposite to the fourth doped region to another side contacting the fourth doped region to a width of the fourth doped region from a side contacting the third doped region to another side opposite to the third doped region may be in a range of 1 to 4.
In an embodiment of the invention, the esd protection device further includes a first stacked structure. The first stacked structure is located on the first well region between the second doped region and the third doped region. The first stacked structure includes a first insulating layer and a first conductive layer sequentially stacked on the substrate.
In an embodiment of the invention, the esd protection device further includes a first isolation structure and a second isolation structure. The first isolation structure is located between the first doped region and the second doped region. The first doped region is located between the first isolation structure and the second isolation structure.
In an embodiment of the invention, the first doped region, the second doped region and the first conductor layer may be electrically connected to the cathode. The third doped region, the fourth doped region, the fifth doped region and the sixth doped region can be electrically connected to the anode.
In an embodiment of the invention, the top view pattern of the first well region may surround the top view pattern of the second well region.
In an embodiment of the invention, the esd protection device further includes a seventh doped region, an eighth doped region and a ninth doped region. The first doped region, the second doped region and the third doped region are located on a first side of the second well region, and the seventh doped region, the eighth doped region and the ninth doped region are located on a second side of the second well region. The first side and the second side are opposite to each other. The seventh doped region, the eighth doped region and the ninth doped region form another transistor, and the conductivity type of the another transistor is the same as that of the first transistor.
In an embodiment of the invention, the ninth doped region may have the first conductivity type, and the seventh doped region and the eighth doped region may have the second conductivity type.
In an embodiment of the invention, a ratio of a width of the sixth doped region from a side opposite to the seventh doped region to the other side contacting the seventh doped region to a width of the seventh doped region from the side contacting the sixth doped region to the other side opposite to the sixth doped region may be in a range of 0.25 to 1.
In an embodiment of the invention, the esd protection device further includes a third isolation structure and a fourth isolation structure. The third isolation structure is located between the eighth doped region and the ninth doped region. The ninth doped region is located between the third isolation structure and the fourth isolation structure.
In an embodiment of the invention, the esd protection device further includes a second stacked structure. The second stacking structure is located on the first well region between the seventh doped region and the eighth doped region, and the second stacking structure includes a second insulating layer and a second conductor layer sequentially stacked on the substrate.
In an embodiment of the invention, the third doped region, the fourth doped region, the fifth doped region, the sixth doped region and the seventh doped region may be electrically connected to the anode. The first doped region, the second doped region, the first conductive layer, the eighth doped region, the second conductive layer and the ninth doped region can be electrically connected to the cathode.
The electrostatic discharge method of the present invention includes the following steps. An electrostatic discharge protection element as described above is provided. The third doped region, the fourth doped region, the fifth doped region and the sixth doped region are electrically coupled. The first doped region is electrically coupled to the second doped region. The third doped region, the fourth doped region, the fifth doped region and the sixth doped region receive an electrostatic voltage. The first doped region and the second doped region are connected to a ground electrode. The first transistor is turned on in a first time interval according to the electrostatic voltage. And according to the electrostatic voltage, the second transistor is conducted in a second time interval so that the first transistor and the second transistor can discharge electrostatic charges.
In an embodiment of the invention, a starting point of the first time interval and a starting point of the second time interval may be different.
In an embodiment of the invention, a starting point of the first time interval may be earlier than a starting point of the second time interval.
Based on the above, the third doped region and the fourth doped region, which are in contact with each other and have the same conductivity type, are disposed on two sides of the interface between the first well region and the second well region, so that the first transistor and the second transistor can be turned on at different time points. Therefore, the SCR of the ESD protection device has two-stage snapback characteristics (double snap-back rectifiers). Therefore, the silicon controlled rectifier has lower trigger voltage, so that the damage of the electronic element caused by abnormal high voltage can be reduced. In addition, the silicon controlled rectifier has higher holding voltage, so that the situation that the operating voltage of an electronic element electrically coupled with the electrostatic discharge protection element exceeds the holding voltage to trigger latch-up can be avoided.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A is a schematic cross-sectional view of an esd protection device according to an embodiment of the invention.
Fig. 1B is a schematic top view of fig. 1A.
FIG. 1C is a current-voltage diagram of a SCR of an ESD protection device according to an embodiment of the present invention.
FIG. 1D is a flow chart of an electrostatic discharge method according to an embodiment of the invention.
FIG. 2A is a schematic cross-sectional view of an ESD protection device according to another embodiment of the present invention.
Fig. 2B is a schematic top view of fig. 2A.
[ notation ] to show
100. 200: electrostatic discharge protection element
102: a first well region
104: second well region
104 a: the first part
104 b: the second part
106: first doped region
108: second doped region
110: a third doped region
112: first stacking structure
114: a first insulating layer
116: first conductor layer
118: a fourth doped region
120: a fifth doped region
122: a sixth doped region
124: first isolation structure
126: second isolation structure
128: contact window
230: a seventh doped region
232: the eighth doped region
234: a ninth doped region
236: second stack structure
238: a second insulating layer
240: second conductor layer
242: third isolation structure
244: fourth isolation structure
M1, M2: MOS transistor
S1: first side
S2: second side
S100, S102, S104, S106, S108, S110: step (ii) of
S110a, S110 b: substeps of
T1: a first transistor
T2: second transistor
T3: a third transistor
T4: a fourth transistor
TP 1: first turning point
TP 2: second turning point
W1-W4: width of
Detailed Description
Fig. 1A is a schematic cross-sectional view of an esd protection device according to an embodiment of the invention. Fig. 1B is a schematic top view of fig. 1A. FIG. 1C is a current-voltage diagram of a SCR of an ESD protection device according to an embodiment of the present invention.
The esd protection device 100 of the present embodiment includes a first well 102 and a second well 104. The first well region 102 and the second well region 104 are located in the substrate 10. In some embodiments, the substrate 10 includes a semiconductor substrate or a Silicon On Insulator (SOI) substrate, and the semiconductor substrate may have an epitaxial layer thereon. For example, the material of the semiconductor substrate and the epitaxial layer may include silicon, germanium, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, or the like. The first well region 102 may be doped to have a first conductivity type and the second well region 104 may be doped to have a second conductivity type. In some embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. In other embodiments, the first conductive type may also be N-type, and the second conductive type may be P-type. For example, the N-type dopant includes phosphorus or arsenic. In addition, the P-type dopant may include boron. In some embodiments, the first well region 102 may surround the second well region 104 from a top view (as shown in fig. 1B). In other words, the first well region 102 can be located on the first side S1 and the second side S2 of the second well region 104 as viewed in cross section (as shown in FIG. 1A). In other embodiments, the first well region 102 may be located at the first side S1 of the second well region 104.
The first well 102 has a first doped region 106, a second doped region 108, and a third doped region 110. The first doped region 106 may have a first conductivity type, and the second doped region 108 and the third doped region 110 may have a second conductivity type. The second doped region 108 may be located between the first doped region 106 and the third doped region 110. In addition, the second doped region 108, the first well region 102 and the third doped region 110 may form a first transistor T1. The first transistor T1 may be a Bipolar Junction Transistor (BJT). In particular, the second doped region 108, the first well 102 and the third doped region 110 can be used as an emitter, a base and a collector of the BJT, respectively.
The esd protection device 100 may further include a first stacked structure 112. The first stacked structure 112 may be located between the second doped region 108 and the third doped region 110. The first stacked structure 112 may include a first insulating layer 114 and a first conductive layer 116 sequentially stacked on the substrate 10. In some embodiments, the first stacked structure 112, the second doped region 108 and the third doped region 110 may form a MOS (Metal-Oxide-Semiconductor) transistor M1. In particular, the first conductive layer 116 and the first insulating layer 114 of the first stacked structure 112 can be used as a gate and a gate dielectric layer of the MOS transistor M1, respectively. The material of the first conductor layer 116 may include polysilicon or a metal material. For example, the metallic material may include tungsten or aluminum. The material of the first insulating layer 114 may include silicon oxide or other high dielectric constant material (e.g., dielectric constant greater than 4). For example, the high dielectric constant material may include hafnium silicate, zirconium silicate, hafnium dioxide, or zirconium dioxide. In addition, the second doped region 108 and the third doped region 110 may serve as a drain/source region of the MOS transistor M1.
The esd protection device 100 further comprises a fourth doped region 118, a fifth doped region 120 and a sixth doped region 122. The fifth doped region 120 has the first conductivity type, and the fourth doped region 118 and the sixth doped region 122 have the second conductivity type. The fourth doped region 118, the fifth doped region 120 and the sixth doped region 122 are located in the second well region 104. The fifth doped region 120 is located between the fourth doped region 118 and the sixth doped region 122. The fourth doped region 118 contacts the third doped region 110, and the conductivity type of the fourth doped region 118 is the same as the conductivity type of the third doped region 110. In some embodiments, the third doped region 110 and the fourth doped region 118 may be two portions of the same doped region that contact each other. Specifically, the third doped region 110 is a portion of the first well region 102, and the fourth doped region 118 is another portion of the second well region 104. In addition, a ratio (W1/W2) of a width W1 of the third doped region 110 from a side opposite to the fourth doped region 118 to the other side contacting the fourth doped region 118 to a width W2 of the fourth doped region 118 from the side contacting the third doped region 110 to the other side opposite to the third doped region 110 is in a range (e.g., in a range of 1 to 4). The above range may be determined according to the operating voltage and the process parameters of the esd protection device 100, and is not limited.
The second well region 104 may be divided into a first portion 104a facing the first stacked structure 112 and a second portion 104b opposite to the first stacked structure 112. The fifth doped region 120, the first portion 104a of the second well region 104 and the substrate 10 may form a second transistor T2. The second transistor T2 may also be a BJT, and the conductivity type of the first transistor T1 is complementary to the conductivity type of the second transistor T2. In particular, the fifth doped region 120, the first portion 104a of the second well 104 and the substrate 10 can be respectively used as an emitter, a base and a collector of the BJT. Similarly, the fifth doped region 120, the second portion 104b of the second well region 104 and the substrate 10 may form a third transistor T3. The third transistor T3 is also BJT, and the conductivity type of the third transistor T3 is the same as the conductivity type of the second transistor T2. In particular, the fifth doped region 120, the second portion 104b of the second well 104 and the substrate 10 can be used as an emitter, a base and a collector of the BJT. In some embodiments, the first transistor T1, the second transistor T2, and the third transistor T3 may constitute a Silicon Controlled Rectifier (SCR), and the third transistor T3 is connected in parallel with the second transistor T2. In other embodiments, the silicon controlled rectifier may include a first transistor T1 and a second transistor T2.
The esd protection device 100 may further include a first isolation structure 124 and a second isolation structure 126. The first isolation structure 124 is located between the first doped region 106 and the second doped region 108, and the first doped region 106 is located between the first isolation structure 124 and the second isolation structure 126. For simplicity, the first isolation structure 124 and the second isolation structure 126 are omitted from fig. 1B. In some embodiments, the first isolation structure 124 and the second isolation structure 126 may be field oxide layer (FOX) or local oxidation of silicon (LOCOS) structures, and may be disposed on the substrate 10. In other embodiments, the first isolation structure 124 and the second isolation structure 126 may be Shallow Trench Isolation (STI) structures and are disposed in the substrate 10.
In some embodiments, the first doped region 106, the second doped region 108, and the first conductive layer 116 may be electrically connected to the cathode through the contact window 128. The cathode may be a ground electrode. The third doped region 110, the fourth doped region 118, the fifth doped region 120, and the sixth doped region 122 may be electrically connected to the anode through the contact window 128. The anode may be adapted to receive an abnormally high voltage. The abnormal high voltage includes, for example, noise (noise) or electrostatic voltage. In addition, the esd protection device 100 may be electrically coupled to an electronic device. When the electronic device receives an abnormal high voltage during operation, the scr of the esd protection device 100 is turned on to discharge the charges.
In particular, the first transistor T1 and the second transistor T2 of the scr of the present embodiment can be turned on at different time points. In some embodiments, the first transistor T1 may be turned on first, followed by the second transistor T2. Thus, referring to fig. 1C, the scr of the present embodiment can have two-stage snapback characteristics (double snap-back characteristics). The first transition point TP1 and the second transition point TP2 of the current-voltage curve represent the turn-on of the first transistor T1 and the turn-on of the second transistor T2, respectively. In addition, the third transistor T3 connected in parallel with the second transistor T2 is turned on at the same time as the second transistor T2 is turned on. In other embodiments, the second transistor T2 and the third transistor T3 may be turned on first, and then the first transistor T1 may be turned on.
FIG. 1D is a flow chart of an electrostatic discharge method according to an embodiment of the invention. The electrostatic discharge method of the present embodiment includes the following steps.
Step S100 is performed to provide the electrostatic discharge protection device 100 shown in fig. 1A. Step S102 is performed to electrically couple the third doped region 110, the fourth doped region 118, the fifth doped region 120 and the sixth doped region 122. In particular, the third doped region 110, the fourth doped region 118, and the fifth doped region 120 may be electrically coupled to the anode through the contact 128.
Step S104 is performed while step S102 is performed to electrically couple the first doped region 106 and the second doped region 108. In step S104, the first conductive layer 116 of the first stacked structure 112 may be electrically coupled to the first doped region 106 and the second doped region 108. In addition, the first conductor layer 116, the first doped region 106, and the second doped region 108 may be electrically coupled to the cathode through the contact window 128.
Step S106 is performed to enable the third doped region 110, the fourth doped region 118, the fifth doped region 120 and the sixth doped region 122 to receive the electrostatic voltage. Step S108 is performed while step S106 is performed to connect the first doped region 106 and the second doped region 108 to the ground electrode. In step S108, the first conductive layer 116 of the first stacked structure 112 may be further connected to the ground electrode.
Step S110 is performed to turn on the first transistor T1 and the second transistor T2, respectively. The step S110 may include a sub-step S110a and a sub-step S110 b. The sub-step S110a is performed to turn on the first transistor T1 during the first time interval according to the electrostatic voltage. In the sub-step S110b, the second transistor T2 is turned on during the second time interval according to the electrostatic voltage. The electrostatic charge can be discharged by turning on the first transistor T1 and the second transistor T2. In addition, since the second transistor T2 is connected in parallel with the third transistor T3, the third transistor T3 is turned on at the same time as the second transistor T2 is turned on.
In some embodiments, the starting point of the first time interval is different from the starting point of the second time interval. Further, the first time interval may partially overlap the second time interval. In some embodiments, the starting point of the first time interval may be earlier than the starting point of the second time interval. In other embodiments, the starting point of the second time interval may be earlier than the starting point of the first time interval.
Based on the above, the first transistor T1 and the second transistor T2 can be turned on at different time points by disposing the third doped region 110 and the fourth doped region 118 contacting each other and having the same conductivity type at two sides of the interface between the first well region 102 and the second well region 104. Thus, the scr of the present embodiment has two-stage snapback characteristics. Therefore, the silicon controlled rectifier of the embodiment can have a lower trigger voltage, so that the damage of the electronic element caused by the abnormal high voltage can be reduced. In addition, the scr of the present embodiment also has a higher holding voltage, so that the operation voltage of the electronic device electrically coupled to the esd protection device 100 can be prevented from exceeding the holding voltage to trigger the latch-up effect.
In some embodiments, the silicon controlled rectifier including the first transistor T1 through the third transistor T3 and the MOS transistor M1 may be integrated in the same region of the substrate 10, so that an additional mask process is not required to form the esd protection device in other regions of the substrate 10. Therefore, the manufacturing cost of the ESD protection device can be reduced, and the area occupied by the ESD protection device can be reduced. Further, by controlling the MOS transistor M1 to be kept in an off (cut off) state, the leakage between the second doped region 108 and the third doped region 110 can be reduced. In addition, the third transistor T3 is connected in parallel with the second transistor T2, so that the current leakage of the scr can be increased. Therefore, the esd protection device 100 can complete the charge discharge more quickly.
FIG. 2A is a schematic cross-sectional view of an ESD protection device according to another embodiment of the present invention. Fig. 2B is a schematic top view of fig. 2A.
The esd protection device 200 of the present embodiment is similar to the esd protection device 100 shown in fig. 1A and 1B, and only the differences between the two will be described below, and the same or similar parts will not be described redundantly. In addition, in the esd protection element 100 and the esd protection element 200, the same reference numerals denote the same or similar components.
The esd protection device 200 further comprises a seventh doped region 230, an eighth doped region 232 and a ninth doped region 234. The ninth doped region 234 has the first conductivity type, and the seventh doped region 230 and the eighth doped region 232 have the second conductivity type. The first doped region 106, the second doped region 108 and the third doped region 110 are located at the first side S1 of the second well region 104, and the seventh doped region 230, the eighth doped region 232 and the ninth doped region 234 are located at the second side S2 of the second well region 104. The first side S1 and the second side S2 of the second well region 104 are opposite to each other. The eighth doped region 232 is located between the seventh doped region 230 and the ninth doped region 234.
The seventh doped region 230 is in contact with the sixth doped region 122, and the conductivity type of the seventh doped region 230 is the same as the conductivity type of the sixth doped region 122. In some embodiments, the sixth doped region 122 and the seventh doped region 230 may be two portions of the same doped region that contact each other. Specifically, the seventh doped region 230 is a portion of the first well 102, and the sixth doped region 122 is another portion of the second well 104. In addition, a ratio (W3/W4) of a width W3 of the sixth doped region 122 from the side opposite to the seventh doped region 230 to the other side contacting the seventh doped region 230 to a width W4 of the seventh doped region 230 from the side contacting the sixth doped region 122 to the other side opposite to the sixth doped region 122 is in a range (e.g., in a range of 0.25 to 1). The above range can be determined according to the operating voltage of the esd protection device and the process parameters, and is not limited. In addition, the seventh doped region 230, the eighth doped region 232, and the ninth doped region 234 constitute a fourth transistor T4. The third transistor T4 may also be a BJT, and the conductivity type of the third transistor T4 is the same as the conductivity type of the first transistor T1. In particular, the eighth doped region 232, the first well 102 on the second side S2 of the second well 104, and the seventh doped region 230 can be respectively used as the emitter, the base, and the collector of the BJT.
In some embodiments, the esd protection device 200 may further include a second stacked structure 236. The second stack structure 236 is located on the first well region 102 between the seventh doped region 230 and the eighth doped region 232. The second stacked structure 236 includes a second insulating layer 238 and a second conductive layer 240 sequentially stacked on the substrate 10. In some embodiments, the second stack structure 236, the seventh doped region 230, and the eighth doped region 232 may form a MOS transistor M2. In particular, the second conductive layer 240 and the second insulating layer 238 of the second stacked structure 236 may be used as a gate electrode and a gate dielectric layer of the MOS transistor M2, respectively. The material of the second conductor layer 240 may include polysilicon or a metal material. For example, the metal material may include tungsten or aluminum. The material of the second insulating layer 238 may include silicon oxide or other high dielectric constant material (e.g., dielectric constant greater than 4). For example, the high dielectric constant material may include hafnium silicate, zirconium silicate, hafnium dioxide, or zirconium dioxide. In addition, the seventh doped region 230 and the third doped region 232 may serve as drain/source regions of the MOS transistor M2.
In addition, the esd protection device 200 may further include a third isolation structure 242 and a fourth isolation structure 244. The third isolation structure 242 is located between the eighth doped region 232 and the ninth doped region 234, and the ninth doped region 234 is located between the third isolation structure 242 and the fourth isolation structure 244. In some embodiments, the third isolation structure 242 and the fourth isolation structure 244 may be field oxide layers or silicon partial oxidation structures, and may be disposed on the substrate 10. In other embodiments, the third and fourth isolation structures 242 and 244 may be shallow trench isolation structures and are disposed in the substrate 10.
In some embodiments, the first doped region 106, the second doped region 108, the first conductive layer 116, the eighth doped region 232, the second conductive layer 240, and the ninth doped region 234 may be electrically connected to the cathode through the contact window 128. The third doped region 110, the fourth doped region 118, the fifth doped region 120, the sixth doped region 122 and the seventh doped region 230 can be electrically connected to the anode through the contact window 128. In this way, the first transistor T1 and the fourth transistor T4 can be connected in parallel, and the second transistor T2 and the third transistor T3 can be connected in parallel. In the present embodiment, the scr of the esd protection device 200 may include a first transistor T1 through a fourth transistor T4.
When the electronic device electrically coupled to the esd protection device 200 receives an abnormal high voltage during operation, the scr of the esd protection device 200 is turned on to discharge the charges. In some embodiments, the first transistor T1 and the fourth transistor T4 may be turned on, followed by the second transistor T2 and the third transistor T3. In other embodiments, the second transistor T2 and the third transistor T3 may be turned on first, and then the first transistor T1 and the fourth transistor T4 may be turned on.
The electrostatic discharge method of the present embodiment is similar to the electrostatic discharge method shown in fig. 1C, and only the differences will be described below. In step S102, the seventh doped region 230 is further electrically coupled to the third doped region 110 to the sixth doped region 122. In step S104, the eighth doped region 232, the ninth doped region 234 and the second conductive layer 240 are electrically coupled to the first doped region 106, the second doped region 108 and the first conductive layer 116.
Next, in step S106, the third doped region 110 to the seventh doped region 230 are enabled to receive the electrostatic voltage. In addition, in step S108, the first doped region 106, the second doped region 108, the first conductor layer 116, the eighth doped region 232, the ninth doped region 234 and the second conductor layer 240 are connected to the ground electrode.
Then, step S110 is performed to turn on the first transistor T1 and the second transistor T2, respectively. Specifically, the fourth transistor T4 is turned on while performing the sub-step S110 a. In addition, the third transistor T3 is turned on while performing the sub-step S110 b. As a result, the electrostatic charges can be commonly discharged from the first to fourth transistors T1 to T4.
Similar to the third doped region 110 and the fourth doped region 118 shown in fig. 1A and fig. 1B, the sixth doped region 122 and the seventh doped region 230 of the present embodiment can also turn on the scr segment of the esd protection device 200. In addition, by controlling the MOS transistor M2 to be kept in the off state, the leakage between the seventh doped region 230 and the eighth doped region 232 can be reduced. Furthermore, since the fourth transistor T4 is connected in parallel with the first transistor T1, the current leakage of the scr can be further increased, so as to further accelerate the charge leakage.
In summary, the third doped region and the fourth doped region with the same conductive type are connected to each other and cross over the first well region and the second well region with complementary conductive types. Therefore, the electrostatic discharge protection device can turn on a plurality of transistors in a segmented manner after receiving the abnormal high voltage so as to conduct the charge discharge. Accordingly, the SCR of the ESD protection device has two-stage snapback characteristics. In other words, the silicon controlled rectifier has a lower trigger voltage, so that the damage of the electronic element electrically coupled to the electrostatic discharge protection element caused by the abnormal high voltage can be reduced. In addition, the silicon controlled rectifier has higher holding voltage, so that the latch-up effect triggered by the fact that the operating voltage of the electronic element is higher than the holding voltage can be avoided.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, but rather, may be modified and practiced in various ways without departing from the spirit and scope of the invention.

Claims (10)

1. An electrostatic discharge protection element comprising:
the first well region is positioned in the substrate and is provided with a first doping region, a second doping region and a third doping region, wherein the second doping region, the first well region and the third doping region form a first transistor;
the second well region is positioned in the substrate on one side of the first well region;
a fourth doped region located in the second well region, the fourth doped region contacting the third doped region and having a same conductivity type as the third doped region;
a fifth doped region located in the second well region, wherein the fifth doped region, the second well region and the substrate form a second transistor, and a conductive type of the second transistor is complementary to a conductive type of the first transistor; and
a sixth doped region located in the second well region, wherein the fifth doped region is located between the fourth doped region and the sixth doped region.
2. The esd-protection device according to claim 1, wherein the substrate, the first well region, the first doped region, and the fifth doped region have a first conductivity type, and the second well region, the second doped region, the third doped region, the fourth doped region, and the sixth doped region have a second conductivity type.
3. The electrostatic discharge protection element of claim 1, wherein the second doped region is located between the first doped region and the third doped region.
4. The electrostatic discharge protection element according to claim 1, wherein a ratio of a width of the third doped region from a side opposite to the fourth doped region to the other side contacting the fourth doped region to a width of the fourth doped region from a side contacting the third doped region to the other side opposite to the third doped region is in a range of 1 to 4.
5. The ESD protection device of claim 1, further comprising a first stacked structure on the first well region between the second doped region and the third doped region, and comprising a first insulating layer and a first conductive layer sequentially stacked on the substrate.
6. The esd-protection device according to claim 1, wherein a top view pattern of the first well region surrounds a top view pattern of the second well region.
7. The ESD protection device of claim 6, further comprising a seventh doped region, an eighth doped region and a ninth doped region, wherein the first doped region, the second doped region and the third doped region are located on a first side of the second well region, the seventh doped region, the eighth doped region and the ninth doped region are located on a second side of the second well region, the first side and the second side are opposite to each other, and the seventh doped region, the eighth doped region and the ninth doped region form another transistor having a conductive type same as that of the first transistor.
8. The esd-protection element according to claim 7, wherein a ratio of a width of the sixth doped region from a side opposite to the seventh doped region to the other side contacting the seventh doped region to a width of the seventh doped region from the side contacting the sixth doped region to the other side opposite to the sixth doped region is in a range of 0.25 to 1.
9. An electrostatic discharge method comprising:
providing an electrostatic discharge protection element according to claim 1;
electrically coupling the third doped region, the fourth doped region, the fifth doped region, and the sixth doped region;
electrically coupling the first doped region and the second doped region;
causing the third, fourth, fifth, and sixth doped regions to receive an electrostatic voltage;
connecting the first doped region and the second doped region to a ground electrode;
turning on the first transistor in a first time interval according to the electrostatic voltage; and
and conducting the second transistor in a second time interval according to the electrostatic voltage so as to enable the first transistor and the second transistor to discharge electrostatic charges.
10. The electrostatic discharge method of claim 9, wherein a starting point of the first time interval is different from a starting point of the second time interval.
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