CN104299966A - Electrostatic discharge protection structure - Google Patents
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- CN104299966A CN104299966A CN201310295934.8A CN201310295934A CN104299966A CN 104299966 A CN104299966 A CN 104299966A CN 201310295934 A CN201310295934 A CN 201310295934A CN 104299966 A CN104299966 A CN 104299966A
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Abstract
The invention discloses an electrostatic discharge protection structure. The protection structure comprises a substrate, a contact region, a first metal oxide semiconductor element, a second metal oxide semiconductor element, a first doping region and a second doping region, wherein the contact region is located in the substrate, the first metal oxide semiconductor element comprises a first drain region with a first conducting type and is located in the substrate, the second metal oxide semiconductor element comprises a second drain region with the first conducting type and is located in the substrate; the first drain region is closer to the contact region in comparison with the second drain region; the first doping region and the second doping region are respectively provided with a second conducting type, and respectively located below the corresponding first drain region and the corresponding second drain region; the area and/or doping concentration of the first doping region is greater than the area and/or doping concentration of the second doping area. Through the change of the area/doping concentration of the doping regions, the difference caused by different distances between the doping regions and the contact region can be modified, breakdown voltages of parasitic bipolar transistors (BJT) in different region can be approximately same, so that the breakover time of each BJT is nearly consistent.
Description
Technical field
The present invention relates to a kind of semiconductor element, and in particular to ESD-protection structure.
Background technology
Static discharge (electrostatic discharge, ESD) is after electric charge is accumulated on non-conductor or unearthed conductor, via discharge path, and the phenomenon of fast moving (electric discharge) at short notice.Static discharge can damage the circuit be made up of the element of integrated circuit.For example, the machine of human body, encapsulated integrated circuit or the instrument of testing integrated circuits are all common electrified bodies, when aforementioned electrified body contacts with chip, namely likely to chip discharge.The instantaneous power of static discharge may cause the integrated circuit in chip damage or lost efficacy.
The static discharge tolerance level of usual commercial integrated circuit must pass through the test of human-body model (HumanBody Model, HBM) 2kV and machine discharge mode (Machine Model, MM) 200V.In order to bear high-tension electrostatic discharge testing like this, the protecting component for electrostatic discharge on integrated circuit often has the design of large component size.In order to save chip area as far as possible, in layout (layout), this large-sized element realizes in the mode of finger-like (multi-finger) usually.Although the protective element of finger-like can save chip area, this layout type often causes the problem of the uneven conducting of element (non-uniform turn-on).
Summary of the invention
The invention provides a kind of ESD-protection structure, the viability (robustness) of ESD-protection structure can be promoted.
The invention provides a kind of ESD-protection structure, the opening time of each parasitic BJT can be made roughly consistent.
The present invention proposes a kind of ESD-protection structure, comprises substrate, contact (pick up) district, the first metal oxide semiconductor device, the second metal oxide semiconductor device, the first doped region and the first doped region.Contact areas, is arranged in above-mentioned substrate.First metal oxide semiconductor device, is positioned in above-mentioned substrate, comprises first drain region with the first conductivity type.Second metal oxide semiconductor device, is positioned in above-mentioned substrate, comprises second drain region with the first conductivity type.More above-mentioned second drain region, above-mentioned first drain region is close to above-mentioned contact areas.First doped region, has the second conductivity type, is positioned at below above-mentioned first drain region.Second doped region, has the second conductivity type, is positioned at below above-mentioned second drain region, wherein the area of above-mentioned first doped region, doping content or both be greater than the area of above-mentioned second doped region, doping content or both.
According to one embodiment of the invention, above-mentioned first conductivity type is N-type, and above-mentioned second conductivity type is P type.
According to one embodiment of the invention, above-mentioned first conductivity type is P type, and above-mentioned second conductivity type is N-type.
According to one embodiment of the invention, above-mentioned first metal-oxide semiconductor (MOS) (MOS) element and above-mentioned second metal oxide semiconductor device are for becoming finger-shaped metal oxide semiconductor device side by side.
According to one embodiment of the invention, above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide semiconductor device are chess trellis (Waffle) metal oxide semiconductor device.
According to one embodiment of the invention, above-mentioned contact areas is ring-type, and above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide semiconductor device are positioned within the region of enclosing above-mentioned contact areas.
The present invention also proposes a kind of ESD-protection structure, comprising: substrate, contact areas, multiple metal oxide semiconductor device, multiple doped region.Contact areas, is arranged in above-mentioned substrate.Multiple metal oxide semiconductor device, is positioned in above-mentioned substrate, has the drain region of the first conductivity type respectively.Multiple doped region, has the second conductivity type and below the above-mentioned drain region laying respectively at each metal oxide semiconductor device.From away from above-mentioned contact areas above-mentioned doped region to close to the area of the above-mentioned doped region of above-mentioned contact areas, doping content or both increase progressively gradually.
According to one embodiment of the invention, above-mentioned first conductivity type is N-type, and above-mentioned second conductivity type is P type.
According to one embodiment of the invention, above-mentioned first conductivity type is P type, and above-mentioned second conductivity type is N-type.
According to one embodiment of the invention, above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide semiconductor device are for becoming finger-shaped metal oxide semiconductor device side by side.
According to one embodiment of the invention, above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide semiconductor device are chess trellis metal oxide semiconductor device.
According to one embodiment of the invention, above-mentioned contact areas is ring-type, and above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide semiconductor device are positioned within the region of enclosing above-mentioned contact areas.
Based on above-mentioned; the invention provides a kind of ESD-protection structure; the viability that the doped region different with its conductivity type can promote ESD-protection structure is set below drain region; and by changing the area/doping content of the doped region be positioned at below drain region; doped region can be revised from contact areas apart from different caused difference; make the breakdown voltage of each parasitic BJT roughly the same, the ON time of each BJT just can be made almost consistent.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the partial top view of the ESD-protection structure of one embodiment of the invention.
Fig. 2 is the partial cutaway schematic of the ESD-protection structure of one embodiment of the invention.
Fig. 3 is the partial top view of the ESD-protection structure of another embodiment of the present invention.
Fig. 4 is the partial cutaway schematic of the ESD-protection structure of another embodiment of the present invention.
Fig. 5 is overlooking of the ESD-protection structure of another embodiment of the present invention.
[symbol description]
10: substrate
20: the first metal oxide semiconductor devices
22: first grid structure
24: the first source areas
24a, 26a, 34a, 36a, 50a, 74a: contact hole
26: the first drain regions
30: the second metal oxide semiconductor devices
32: second grid structure
34: the second source areas
36: the second drain regions
40: the first doped regions
50: contact (pick up) district
52: isolation structure
60: the second doped regions
70: the three metal oxide semiconductor devices
74: the three source areas
80: the four metal oxide semiconductor devices
100a, 100b: ESD-protection structure
110,210: metal oxide semiconductor device
220,230: grid structure
212: source area
114,114a, 114b, 214,214a, 214b: drain region
140,140a, 140b, 240,240a, 240b: doped region
A
1, A
2: area
P
w1, P
w2: width
P
l1, P
l2: length
Embodiment
A kind of ESD-protection structure of the embodiment of the present invention, it comprises multiple metal oxide semiconductor device.Below the drain region of each metal oxide semiconductor device, the doped region different with drain region conductivity type is set, to promote the viability of ESD-protection structure.Moreover, area/the doping content of the doped region below the drain region close to contact (pickup) district is greater than the area/doping content of the doped region below away from the drain region of contact areas, to make the breakdown voltage of each parasitic BJT roughly the same, and then make each parasitic BJT ON time almost consistent.
Fig. 1 is the partial top view of the ESD-protection structure of embodiments of the invention.Fig. 2 is the partial cutaway schematic of the ESD-protection structure of embodiments of the invention.
Please also refer to Fig. 1 and 2, the ESD-protection structure 100a of one embodiment of the invention comprises substrate 10, first metal oxide semiconductor device 20, second metal oxide semiconductor device 30, doped region, contact (pick up) district 50, first 40 and the second doped region 60.First metal oxide semiconductor device 20 and the second metal oxide semiconductor device 30 have the first conductivity type passage.Doped region, contact areas 50, first 40 and the second doped region 60 have the second conductivity type and adulterate.In one embodiment, the first conductivity type is N-type, and the second conductivity type is P type.In another embodiment, the first conductivity type is P type, and the second conductivity type is N-type.The doping of P type doped region is such as boron or boron trifluoride (BF
3).The doping of N-type doped region is such as phosphorus or arsenic.In order to clear description the present embodiment, with the conduction type in each region of word indicating in Fig. 1 and 2, "+" number represents the region that doping content is higher.But the present invention is not limited with the conduction type indicated in Fig. 1 and 2.
First metal oxide semiconductor device 20 comprises first grid structure 22, first source area 24 and the first drain region 26.In the substrate 10 of first grid structure 22 between the first source area 24 and the first drain region 26.First grid structure 22 comprises first grid conductor layer and first grid dielectric layer.The material of first grid conductor layer can be conductor, such as metal or doped polycrystalline silicon.The material of first grid dielectric layer can be insulator, the high dielectric constant material that such as silica or dielectric constant are greater than 4.First grid structure 22 also can comprise clearance wall, and its material can be insulator, such as silica or silicon nitride.First source area 24 and the first drain region 26 have the first conductivity type, and be positioned among substrate 10, it has the first conductivity type passage each other, is positioned at below first grid structure 22.
Second metal oxide semiconductor device 30 comprises second grid structure 32, second source area 34 and the second drain region 36.In the substrate 10 of second grid structure 32 between the second source area 34 and the second drain region 36.Second grid structure 32 comprises second grid conductor layer and second grid dielectric layer.The material of second grid conductor layer can be conductor, such as metal or doped polycrystalline silicon.The material of second grid dielectric layer can be insulator, the high dielectric constant material that such as silica or dielectric constant are greater than 4.Second grid structure 32 also can comprise clearance wall, and its material can be insulator, such as silica or silicon nitride.Second source area 34 and the second drain region 36 have the first conductivity type, and be positioned among substrate 10, it has the first conductivity type passage each other, is positioned at below second grid structure 32.
In one embodiment, ESD-protection structure 100a also comprises the 3rd metal oxide semiconductor device 70 and the 4th metal oxide semiconductor device 80 between the first metal oxide semiconductor device 20 and the second metal oxide semiconductor device 30.3rd metal oxide semiconductor device 70 and the first metal oxide semiconductor device 20 share the first drain region 26.4th metal oxide semiconductor device 80 and the second metal oxide semiconductor device 30 share the second drain region 36, and share the 3rd source area 74 with the 3rd metal-oxide semiconductor (MOS).In one embodiment, the first metal oxide semiconductor device 20, second metal oxide semiconductor device 30, the 3rd metal oxide semiconductor device 70 can be become finger-shaped metal oxide semiconductor device side by side with the 4th metal oxide semiconductor device 80.
Contact areas 50 has the second conductivity type and is arranged in substrate 10.In one embodiment, contact areas 50 is ring-type, and the first metal oxide semiconductor device 20, second metal oxide semiconductor device 30, the 3rd metal oxide semiconductor device 70 and the 4th metal oxide semiconductor device 80 are positioned within the region of enclosing contact areas 50.Contact areas 50 and the first metal oxide semiconductor device 20 are separated with isolation structure 52.Isolation structure 52 can contain insulating material, such as silica.Isolation structure 52 can be regional area oxide layer (FOX) or shallow slot isolation structure (STI).Compared to the second metal oxide semiconductor device 30, first metal oxide semiconductor device 20 comparatively close to contact (pick up) district 50.That is, compared to the first drain region 26 of the second drain region 36, first metal oxide semiconductor device 20 of the second metal oxide semiconductor device 30 comparatively close to contact areas 50.
First doped region 40 has the second conductivity type, is positioned at the below of the first drain region 26 of the first metal oxide semiconductor device 20.Second doped region 60 has the second conductivity type, is positioned at the below of the second drain region 36 of the second metal oxide semiconductor device 30.In one embodiment, the first doped region 40 and the first drain region 26 are close to, and the second doped region 60 and the second drain region 36 are close to, as shown in Figure 2.In another embodiment, the distance between the end face of the first doped region 40 and the bottom surface of the first drain region 26 is such as about 0.05 μm to 0.2 μm; Distance between the end face of the second doped region 60 and the bottom surface of the second drain region 36 is such as about 0.05 μm to 0.2 μm.By the setting of the first doped region 40 and the second doped region 60, the viability (robustness) of ESD-protection structure can be promoted.The width of the first doped region 40 is P
w1, length is P
l1, area A
1=P
w1× P
l1.The width of the second doped region 60 is P
w2, length is P
l2, area A
2=P
w2× P
l2.The size of the area of the first doped region 40 and the second doped region 60 or the height of doping content can with the breakdown voltages affecting side direction diode.In one embodiment, the first drain region, drain region 26 to the second 36 is close to the area A of doped region 40, contact areas 50, first
1comparatively be greater than the area A of the second doped region 60
2.In another embodiment, the first drain region, drain region 26 to the second 36 is comparatively greater than the second doped region 60 close to the doping content of doped region 40, contact areas 50, first.In another embodiment, the first drain region, drain region 26 to the second 36 is close to the area A of doped region 40, contact areas 50, first
1the area A of the second doped region 60 is all comparatively greater than with doping content
2with doping content.
Generally speaking, the conducting of parasitic BJT is by substrate 10 leakage current Ioff.The value of leakage current is almost fixed substantially in the substrate.Determine that the conducting speed of parasitic BJT is decided by the size (Vbe=Ioff × Rsub) of base stage to emitter voltage (Vbe).First doped region 40 is comparatively near apart from contact areas 50, and the resistance of its substrate 10 is less, therefore Vbe voltage is just less, and parasitic BJT just can slower conducting.Otherwise, and the second doped region 60 is comparatively far away apart from contact areas 50, the resistance of its substrate 10 is comparatively large, therefore voltage Vbe is just comparatively large, and BJT just can comparatively fast conducting.Therefore, the inconsistent problem of each BJT ON time is just had.
As mentioned above, make the key of parasitic BJT conducting be voltage Vbe, and the voltage of voltage Vbe is equivalent to Ioff × Rsub.According to the present embodiment, the Ioff here discussed can be directly proportional again (that is, Ioff ≒ k × A, k are proportionality constant) haply to the area A of doped region.Therefore, if will allow each parasitic BJT can simultaneously conducting, that is the voltage Vbe of each parasitic BJT to be allowed identical haply, following relational expression can be derived:
Vbe≒Ioff×Rsub≒k×A×Rsub
Therefore, suppose that at the second doped region 60 area away from contact areas 50 be A
2, be A close to the area of the first doped region 40 of contact areas 50
1, then due to comparatively large at the Rsub away from contact areas 50, therefore the second doped region 60 can be obtained need little area, on the contrary less at the Rsub close to contact areas 50, therefore the first doped region 40 can be obtained need large area.So, just can be almost equal away from contact areas 50 and the voltage Vbe close to each parasitic BJT of contact areas 50, the object of conducting while of making each parasitic BJT almost can also just be reached.
In sum, in the present embodiment, by the area A of the first doped region 40
1, doping content or both change into the area A being comparatively greater than the second doped region 60
2, doping content or both, the first doped region 40 and the second doped region 60 can be revised from contact areas 50 apart from different caused difference, make the breakdown voltage of side direction parasitic diode roughly the same, the ON time of each BJT just can be made almost consistent.
Drain region 36, source area 34, second, drain region 26, second, source area 24, first, contact areas 50, first and the 3rd source area 74 are provided with multiple contact hole 50a, 24a, 26a, 34a, 36a and 74a.The material of contact hole 50a, 24a, 26a, 34a, 36a and 74a can be conductor.In addition, the structure of contact hole 50a, 24a, 26a, 34a, 36a and 74a can comprise barrier layer and leading electric layer.Barrier layer is such as the composite bed of Ti and TiN, the composite bed of Ta and TaN or its combination in any; Leading electric layer is such as tungsten layer, layers of copper or aluminium lamination.Between contact hole 50a, 24a, 26a, 34a, 36a and 74a and drain region 36, source area 34, second, drain region 26, second, source area 24, first, the contact areas below it 50, first and the 3rd source area 74, alternative is provided with metal silicide layer to guarantee low contact resistance and ohmic contact.
In other examples, please refer to Fig. 3 and 4, ESD-protection structure 100b comprises multiple metal oxide semiconductor device 110.Below the drain region 114 of each metal oxide semiconductor device 110, there is doped region 140, the conductivity type of doped region 140 and the conductivity type of drain region 114 different, and to increase progressively gradually from away from the area/doping content of doped region 140 to the doped region 140 close to contact areas 150 of contact areas 150.
In one embodiment; please refer to Fig. 1 and 2, first metal oxide semiconductor device 20, second metal oxide semiconductor device 30 of above-mentioned ESD-protection structure 100a, the 3rd metal oxide semiconductor device 70 and the 4th metal oxide semiconductor device 80 can be finger-shaped MOS arranged side by side.It is peripheral that contact areas 50 is looped around the first metal oxide semiconductor device 20, second metal oxide semiconductor device 30, the 3rd metal oxide semiconductor device 70 and the 4th metal oxide semiconductor device 80.Similarly, please refer to Fig. 3 and 4, multiple metal oxide semiconductor devices 110 of above-mentioned ESD-protection structure 100b can be finger-shaped MOS arranged side by side.It is peripheral that contact areas 150 is looped around metal oxide semiconductor device 110.
In another embodiment, please refer to Fig. 5, above-mentioned ESD-protection structure 100c comprises multiple metal oxide semiconductor device 210, and these metal oxide semiconductor devices are arranged in chess trellis (WaffLe).More particularly, multiple metal oxide semiconductor devices 210 of ESD-protection structure 100c comprise multiple grid structure 220 along first direction arrangement and multiple grid structure 230 arranged along second direction.In one embodiment, first direction and second direction orthogonal.Multiple grid structure 220 forms multiple chess lattice with multiple grid structure 230.Source area 212 and drain region 214 are then alternately configured among chess lattice, make arbitrary source area 212 surrounding by four drain regions 214 around, arbitrary drain region 214 by four source areas 212 around.Contact areas 250 is surrounded on the periphery of the metal oxide semiconductor device 210 of chess trellis.
Metal oxide semiconductor device is arranged in the metal oxide semiconductor device 210b distance contact areas 250 of chess trellis in chess trellis center farthest, and nearest in the metal oxide semiconductor device 210a distance contact areas 250 of chess trellis edge, the inconsistent problem of its parasitic BJT ON time is even more serious.Therefore, according to the mode of above-described embodiment, can arrange doped region 240 below drain region 214, the conductivity type of doped region 240 is different from the conductivity type of source area 212 and drain region 214.Area/the doping content of the doped region 240a nearer in distance contact areas 250 is designed to the area/doping content being greater than distance contact areas 250 doped region 240b far away.Or, be designed to increase progressively gradually to the area/doping content close to the doped region 240a below the drain region 214a of contact areas 250 from away from the doped region 240b below the drain region 214b of contact areas 250, use and revise doped region 240 from contact areas 250 apart from different caused difference, make the breakdown voltage of each parasitic BJT roughly the same, become and the ON time of each BJT can be made almost consistent.
In above embodiment, contact areas is surrounded on the periphery of the metal oxide semiconductor device of chess trellis.But the present invention is not limited to this.Contact areas also can be arranged between two adjacent metal oxide semiconductor devices or the metal oxide semiconductor device of adjacent two groups.
Comprehensive the above, the doped region that the embodiment of the present invention is arranged below drain region and its conductivity type is different can promote the viability of ESD-protection structure.In addition, by changing the area/doping content of the doped region be positioned at below drain region, doped region can be revised from contact areas apart from different caused difference, make the breakdown voltage of each parasitic BJT of zones of different roughly the same, the ON time of each BJT just can be made almost consistent.
Although the present invention with embodiment openly as above; so itself and be not used to limit the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on appended claims confining spectrum.
Claims (12)
1. an ESD-protection structure, is characterized in that comprising:
Substrate;
Contact areas, is arranged in described substrate;
First metal oxide semiconductor device, is positioned in described substrate, comprises first drain region with the first conductivity type;
Second metal oxide semiconductor device, is positioned in described substrate, comprises one second drain region with described first conductivity type, and more described second drain region, wherein said first drain region is close to described contact areas;
First doped region, has the second conductivity type, is positioned at below described first drain region; And
Second doped region, has described second conductivity type, is positioned at below described second drain region, the area of wherein said first doped region, doping content or both be greater than the area of described second doped region, doping content or both.
2. ESD-protection structure as claimed in claim 1, wherein said first conductivity type is N-type, and described second conductivity type is P type.
3. ESD-protection structure as claimed in claim 1, wherein said first conductivity type is P type, and described second conductivity type is N-type.
4. ESD-protection structure as claimed in claim 1, wherein said first metal oxide semiconductor device and described second metal oxide semiconductor device are for becoming finger-shaped metal oxide semiconductor device side by side.
5. ESD-protection structure as claimed in claim 1, wherein said first metal oxide semiconductor device and described second metal oxide semiconductor device are chess trellis metal oxide semiconductor device.
6. ESD-protection structure as claimed in claim 1, wherein said contact areas is ring-type, and described first metal oxide semiconductor device and described second metal oxide semiconductor device are positioned within the region of enclosing described contact areas.
7. an ESD-protection structure, is characterized in that comprising:
Substrate;
Contact areas, is arranged in described substrate;
Multiple metal oxide semiconductor device, is positioned in described substrate, has the drain region of the first conductivity type respectively;
Multiple doped region, has the second conductivity type and below the described drain region laying respectively at each metal oxide semiconductor device,
Wherein from away from described contact areas described doped region to close to the area of the described doped region of described contact areas, doping content or both increase progressively gradually.
8. ESD-protection structure as claimed in claim 7, wherein said first conductivity type is N-type, and described second conductivity type is P type.
9. ESD-protection structure as claimed in claim 7, wherein said first conductivity type is P type, and described second conductivity type is N-type.
10. ESD-protection structure as claimed in claim 7, wherein these metal oxide semiconductor devices are become finger-shaped metal oxide semiconductor device side by side.
11. ESD-protection structures as claimed in claim 7, wherein these metal oxide semiconductor devices are chess trellis metal oxide semiconductor device.
12. ESD-protection structures as claimed in claim 7, wherein said contact areas is ring-type, and these metal oxide semiconductor devices are positioned within the region of enclosing described contact areas.
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| Publication number | Publication date |
|---|---|
| CN104299966B (en) | 2019-07-19 |
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