CN104299966B - ESD-protection structure - Google Patents
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- CN104299966B CN104299966B CN201310295934.8A CN201310295934A CN104299966B CN 104299966 B CN104299966 B CN 104299966B CN 201310295934 A CN201310295934 A CN 201310295934A CN 104299966 B CN104299966 B CN 104299966B
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Abstract
ESD-protection structure, including substrate, contact areas, the first metal oxide semiconductor device, the second metal oxide semiconductor device, the first doped region and the second doped region.Contact areas is located in substrate.First metal oxide semiconductor device includes first drain region with the first conductive type, is located in substrate.Second metal oxide semiconductor device includes second drain region with the first conductive type, is located in substrate.First drain region is compared with the second drain region close to contact areas.First and second doped regions all have the second conductive type, are located at below corresponding first and second drain region.The area and/or doping concentration of first doped region are greater than the area and/or doping concentration of the second doped region.By changing area/doping concentration of doped region, doped region and the contact areas difference caused by different can be corrected, keeps the breakdown voltage of each parasitic bipolar transistor of different zones (BJT) roughly the same, each BJT turn-on time can be made almost consistent.
Description
Technical field
The present invention relates to a kind of semiconductor elements, and in particular to ESD-protection structure.
Background technique
Static discharge (electrostatic discharge, ESD) is that charge tires out on non-conductor or unearthed conductor
After product, via discharge path, the phenomenon that fast moving (electric discharge) in a short time.Static discharge can damage the member by integrated circuit
The circuit that part is constituted.For example, the instrument of human body, the machine of encapsulation integrated circuit or test integrated circuit is all common band
Electric body, when aforementioned electrical body is contacted with chip, i.e., it is possible that chip discharge.The instantaneous power of static discharge may cause core
Integrated circuit damage or failure in piece.
Usually commercialization integrated circuit static discharge tolerance level must pass through human-body model (HumanBody Model,
HBM) the test of 2kV and machine discharge mode (Machine Model, MM) 200V.In order to bear the quiet of such high voltage
Discharge of electricity is tested, and the protecting component for electrostatic discharge on integrated circuit is often with the design for having big component size.In order to save as far as possible
Chip area, on layout (layout), this large-sized element comes real usually in a manner of finger-like (multi-finger)
It is existing.Although the protective element of finger-like can save chip area, this layout type often results in element and (non-is unevenly connected
Uniform turn-on) the problem of.
Summary of the invention
The present invention provides a kind of ESD-protection structure, can promote the viability of ESD-protection structure
(robustness).
The present invention provides a kind of ESD-protection structure, and the opening time of each parasitism BJT can be made substantially uniform.
The present invention proposes a kind of ESD-protection structure, including substrate, the area contact (pick up), the oxidation of the first metal
Object semiconductor element, the second metal oxide semiconductor device, the first doped region and the first doped region.Contact areas is located at upper
It states in substrate.First metal oxide semiconductor device is located in above-mentioned substrate, including the first drain electrode with the first conductive type
Area.Second metal oxide semiconductor device is located in above-mentioned substrate, including the second drain region with the first conductive type.On
More above-mentioned second drain region in the first drain region is stated close to above-mentioned contact areas.First doped region has the second conductive type, is located at above-mentioned
Below first drain region.Second doped region has the second conductive type, is located at below above-mentioned second drain region, wherein above-mentioned first
The area of doped region, doping concentration or both are greater than the area of above-mentioned second doped region, doping concentration or both.
According to one embodiment of the invention, above-mentioned the first conductive type is N-type, and above-mentioned the second conductive type is p-type.
According to one embodiment of the invention, above-mentioned the first conductive type is p-type, and above-mentioned the second conductive type is N-type.
According to one embodiment of the invention, above-mentioned first metal-oxide semiconductor (MOS) (MOS) element and above-mentioned second metal oxygen
Compound semiconductor element is side by side at finger-shaped metal oxide semiconductor device.
According to one embodiment of the invention, above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide half
Conductor element is grid shape (Waffle) metal oxide semiconductor device.
According to one embodiment of the invention, above-mentioned contact areas be ring-type, above-mentioned first metal oxide semiconductor device with it is upper
The second metal oxide semiconductor device is stated to be located within the region that above-mentioned contact areas is enclosed.
The present invention also proposes a kind of ESD-protection structure, comprising: substrate, contact areas, multiple metal oxides are partly led
Volume elements part, multiple doped regions.Contact areas is located in above-mentioned substrate.Multiple metal oxide semiconductor devices are located at above-mentioned substrate
On, it is respectively provided with the drain region of the first conductive type.Multiple doped regions have the second conductive type and are located at each metal oxidation
Below the above-mentioned drain region of object semiconductor element.From the above-mentioned doped region far from above-mentioned contact areas to close to the upper of above-mentioned contact areas
Area, the doping concentration or both for stating doped region are gradually incremented by.
According to one embodiment of the invention, above-mentioned the first conductive type is N-type, and above-mentioned the second conductive type is p-type.
According to one embodiment of the invention, above-mentioned the first conductive type is p-type, and above-mentioned the second conductive type is N-type.
According to one embodiment of the invention, above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide half
Conductor element is side by side at finger-shaped metal oxide semiconductor device.
According to one embodiment of the invention, above-mentioned first metal oxide semiconductor device and above-mentioned second metal oxide half
Conductor element is grid shape metal oxide semiconductor device.
According to one embodiment of the invention, above-mentioned contact areas be ring-type, above-mentioned first metal oxide semiconductor device with it is upper
The second metal oxide semiconductor device is stated to be located within the region that above-mentioned contact areas is enclosed.
Based on above-mentioned, the present invention provides a kind of ESD-protection structure, setting and its conductivity type phase below drain region
Different doped region can promote the viability of ESD-protection structure, and by changing the doped region being located at below drain region
Area/doping concentration, can correct doped region and contact areas distance it is different caused by difference so that each parasitism BJT's collapses
Voltage of bursting is roughly the same, can be so that the turn-on time of each BJT is almost consistent.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the partial top view of the ESD-protection structure of one embodiment of the invention.
Fig. 2 is the partial cutaway schematic of the ESD-protection structure of one embodiment of the invention.
Fig. 3 is the partial top view of the ESD-protection structure of another embodiment of the present invention.
Fig. 4 is the partial cutaway schematic of the ESD-protection structure of another embodiment of the present invention.
Fig. 5 is the vertical view of the ESD-protection structure of another embodiment of the present invention.
[symbol description]
10: substrate
20: the first metal oxide semiconductor devices
22: first grid structure
24: the first source areas
24a, 26a, 34a, 36a, 50a, 74a: contact hole
26: the first drain regions
30: the second metal oxide semiconductor devices
32: second grid structure
34: the second source areas
36: the second drain regions
40: the first doped regions
50: the area contact (pick up)
52: isolation structure
60: the second doped regions
70: third metal oxide semiconductor device
74: third source area
80: the four metal oxide semiconductor devices
100a, 100b: ESD-protection structure
110,210: metal oxide semiconductor device
220,230: gate structure
212: source area
114,114a, 114b, 214,214a, 214b: drain region
140,140a, 140b, 240,240a, 240b: doped region
A1、A2: area
PW1、PW2: width
PL1、PL2: length
Specific embodiment
A kind of ESD-protection structure of the embodiment of the present invention comprising multiple metal oxide semiconductor devices.?
Below the drain region of each metal oxide semiconductor device, the doped region different with drain region conductivity type is set, to be promoted
The viability of ESD-protection structure.Furthermore the area of the doped region below the drain region close to the area contact (pickup)/
Doping concentration is greater than area/doping concentration of the doped region below the drain region far from contact areas, so that each parasitism BJT's collapses
Voltage of bursting is roughly the same, and then keeps each parasitism BJT turn-on time almost consistent.
Fig. 1 is the partial top view of the ESD-protection structure of the embodiment of the present invention.Fig. 2 is the embodiment of the present invention
ESD-protection structure partial cutaway schematic.
Please also refer to Fig. 1 and 2, the ESD-protection structure 100a of one embodiment of the invention includes substrate 10, the first gold medal
Belong to oxide-semiconductor devices 20, the second metal oxide semiconductor device 30, the area 50 contact (pick up), the first doped region
40 and second doped region 60.First metal oxide semiconductor device 20 and the second metal oxide semiconductor device 30 have the
One conductivity type channel.Contact areas 50, the first doped region 40 and the second doped region 60 are adulterated with the second conductive type.In an embodiment
In, the first conductive type is N-type, and the second conductive type is p-type.In another embodiment, the first conductive type is p-type, the second conductive type
For N-type.The doping of P-doped zone is, for example, boron or boron trifluoride (BF3).The doping of N-doped zone is, for example, phosphorus or arsenic.In order to
Clearly describe the present embodiment, with the conduction type in each region of word indicating in Fig. 1 and 2, "+" number indicates the higher area of doping concentration
Domain.However, the present invention is not limited with the conduction type indicated in Fig. 1 and 2.
First metal oxide semiconductor device 20 includes first grid structure 22, the first source area 24 and the first drain region
26.First grid structure 22 is in the substrate 10 between the first source area 24 and the first drain region 26.First grid structure 22
Including first grid conductor layer and first grid dielectric layer.The material of first grid conductor layer can be conductor, for example, metal or
DOPOS doped polycrystalline silicon.The material of first grid dielectric layer can be insulator, such as silica or dielectric constant are greater than 4 high dielectric
Constant material.First grid structure 22 may also include clearance wall, and material can be insulator, such as silicon oxide or silicon nitride.
First source area 24 and the first drain region 26 have the first conductive type, are located among substrate 10, have first to lead each other
Electric type channel is located at 22 lower section of first grid structure.
Second metal oxide semiconductor device 30 includes second grid structure 32, the second source area 34 and the second drain region
36.Second grid structure 32 is in the substrate 10 between the second source area 34 and the second drain region 36.Second grid structure 32
Including second grid conductor layer and second grid dielectric layer.The material of second grid conductor layer can be conductor, for example, metal or
DOPOS doped polycrystalline silicon.The material of second grid dielectric layer can be insulator, such as silica or dielectric constant are greater than 4 high dielectric
Constant material.Second grid structure 32 may also include clearance wall, and material can be insulator, such as silicon oxide or silicon nitride.
Second source area 34 and the second drain region 36 have the first conductive type, are located among substrate 10, have first to lead each other
Electric type channel is located at 32 lower section of second grid structure.
In one embodiment, ESD-protection structure 100a further includes being located at the first metal oxide semiconductor device 20
Third metal oxide semiconductor device 70 and the 4th metal oxide half between the second metal oxide semiconductor device 30
Conductor element 80.Third metal oxide semiconductor device 70 and the first metal oxide semiconductor device 20 share the first drain electrode
Area 26.4th metal oxide semiconductor device 80 and the second metal oxide semiconductor device 30 share the second drain region 36,
And third source area 74 is shared with third metal-oxide semiconductor (MOS).In one embodiment, the first metal-oxide semiconductor (MOS) member
Part 20, the second metal oxide semiconductor device 30, third metal oxide semiconductor device 70 and the 4th metal oxide half
Conductor element 80 can be for side by side at finger-shaped metal oxide semiconductor device.
Contact areas 50 has the second conductive type and is located in substrate 10.In one embodiment, contact areas 50 is cyclic annular, first
Metal oxide semiconductor device 20, the second metal oxide semiconductor device 30, third metal oxide semiconductor device 70
It is located within the region that contact areas 50 is enclosed with the 4th metal oxide semiconductor device 80.Contact areas 50 and the first metal aoxidize
Object semiconductor element 20 is with the separation of isolation structure 52.Isolation structure 52 can contain insulating materials, such as silica.Isolation structure
52 can be regional area oxide layer (FOX) or shallow slot isolation structure (STI).Compared to the second metal-oxide semiconductor (MOS) member
Part 30, the first metal oxide semiconductor device 20 are closer to the area 50 contact (pick up).That is, being aoxidized compared to the second metal
First drain region 26 of the second drain region 36 of object semiconductor element 30, the first metal oxide semiconductor device 20 is closer to connect
Point area 50.
First doped region 40 has the second conductive type, positioned at the first drain region of the first metal oxide semiconductor device 20
26 lower section.Second doped region 60 has the second conductive type, positioned at the second drain electrode of the second metal oxide semiconductor device 30
The lower section in area 36.In one embodiment, the first doped region 40 and the first drain region 26 are close to the second doped region 60 and second drains
Area 36 is close to as shown in Figure 2.In another embodiment, between the top surface of the first doped region 40 and the bottom surface of the first drain region 26
Distance be, for example, about 0.05 μm to 0.2 μm；The distance between the bottom surface of the top surface of second doped region 60 and the second drain region 36
E.g. about 0.05 μm to 0.2 μm.By the setting of the first doped region 40 and the second doped region 60, static discharge guarantor can be promoted
The viability (robustness) of protection structure.The width of first doped region 40 is PW1, length PL1, area A1=PW1×PL1.The
The width of two doped regions 60 is PW2, length PL2, area A2=PW2×PL2.The area of first doped region 40 and the second doped region 60
Size or the height of doping concentration can be with the breakdown voltage that influences lateral diode.In one embodiment, the first drain region 26
Than the second drain region 36 close to contact areas 50, the area A of the first doped region 401The relatively larger than area A of the second doped region 602.Another
In one embodiment, for 26 to the second drain region 36 of the first drain region close to contact areas 50, the doping concentration of the first doped region 40 is larger
In the second doped region 60.In another embodiment, 26 to the second drain region 36 of the first drain region is adulterated close to contact areas 50, first
The area A in area 401The area A of the second doped region 60 is relatively larger than with doping concentration2With doping concentration.
In general, the conducting of parasitism BJT is by 10 leakage current Ioff of substrate.The value of leakage current is substantially several in the substrate
It is fixed.The conducting speed for determining parasitism BJT is determined by the size (Vbe=Ioff × Rsub) of base stage to emitter voltage (Vbe)
It is fixed.First doped region 40 is relatively close apart from contact areas 50, and the resistance value of substrate 10 is smaller, therefore Vbe voltage is just smaller, and parasitic BJT is just
It can relatively slow conducting.Conversely, and the second doped region 60 apart from contact areas 50 farther out, the resistance value of substrate 10 is larger, therefore voltage Vbe is just
Larger, BJT will comparatively fast be connected.Therefore, the problem that will have each BJT turn-on time inconsistent.
As described above, the key of parasitic BJT conducting is made to be voltage Vbe, and the voltage of voltage Vbe be equivalent to Ioff ×
Rsub.According to the present embodiment, the Ioff here discussed again can it is generally directly proportional to the area A of doped region (that is, Ioff ≒ k ×
A, k are proportionality constant).Therefore, if to allow each parasitism BJT that can simultaneously turn on, that is, the voltage Vbe of each parasitism BJT is allowed
It is substantially the same, can derive following relationship:
Vbe≒Ioff×Rsub≒k×A×Rsub
Therefore, it is assumed that 60 area of the second doped region in separate contact areas 50 is A2, close to the first doped region of contact areas 50
40 area is A1, then due to larger in the Rsub far from contact areas 50, therefore available second doped region 60 needs small face
Product, on the contrary it is smaller in the Rsub close to contact areas 50, therefore available first doped region 40 needs big area.In this way, remote
Voltage Vbe from contact areas 50 and each parasitism BJT close to contact areas 50 can be almost equal, and can also reach makes respectively to post
The purpose that raw BJT is almost simultaneously turned on.
In conclusion in the present embodiment, by the area A of the first doped region 401, doping concentration or both change into it is larger
In the area A of the second doped region 602, doping concentration or both, the first doped region 40 and the second doped region 60 can be corrected and connect
Point area 50 is apart from difference caused by difference, so that the breakdown voltage of lateral parasitic diode is roughly the same, it can be so that each BJT
Turn-on time it is almost consistent.
In contact areas 50, the first source area 24, the first drain region 26, the second source area 34, the second drain region 36 and
Multiple contact hole 50a, 24a, 26a, 34a, 36a and 74a are provided on three source areas 74.Contact hole 50a, 24a, 26a, 34a,
The material of 36a and 74a can be conductor.In addition, the structure of contact hole 50a, 24a, 26a, 34a, 36a and 74a can wrap
Include barrier layer and leading electric layer.Barrier layer is, for example, the composite layer of Ti and TiN, the composite layer of Ta and TaN or any combination thereof；It is main
Conductive layer is, for example, tungsten layer, layers of copper or aluminium layer.In contact hole 50a, 24a, 26a, 34a, 36a and 74a and contact below
Between area 50, the first source area 24, the first drain region 26, the second source area 34, the second drain region 36 and third source area 74
Alternative is equipped with metal silicide layer to ensure low contact resistance and Ohmic contact.
In other examples, referring to figure 3. with 4, ESD-protection structure 100b includes multiple metal oxides
Semiconductor element 110.There is doped region 140, doping below the drain region 114 of each metal oxide semiconductor device 110
The conductivity type in area 140 is different with the conductivity type of drain region 114, and from the doped region 140 far from contact areas 150 to close to contact areas
Area/doping concentration of 150 doped region 140 is gradually incremented by.
In one embodiment, Fig. 1 and 2, the first metal oxide of above-mentioned ESD-protection structure 100a are please referred to
Semiconductor element 20, the second metal oxide semiconductor device 30, third metal oxide semiconductor device 70 and the 4th metal
Oxide-semiconductor devices 80 can be finger-shaped MOS arranged side by side.Contact areas 50 is looped around the first metal-oxide semiconductor (MOS) member
Part 20, the second metal oxide semiconductor device 30, third metal oxide semiconductor device 70 and the 4th metal oxide half
80 periphery of conductor element.Similarly, referring to figure 3. with 4, multiple metal oxides of above-mentioned ESD-protection structure 100b
Semiconductor element 110 can be finger-shaped MOS arranged side by side.Contact areas 150 is looped around outside metal oxide semiconductor device 110
It encloses.
In another embodiment, referring to figure 5., above-mentioned ESD-protection structure 100c includes multiple metal oxides
Semiconductor element 210, and these metal oxide semiconductor devices are arranged in grid shape (WaffLe).More specifically, electrostatic
Multiple metal oxide semiconductor devices 210 of discharge prevention structure 100c include multiple grid knots arranged along a first direction
Structure 220 and multiple gate structures 230 arranged along second direction.In one embodiment, first direction and second direction are mutual
Vertically.Multiple gate structures 220 constitute multiple grids with multiple gate structures 230.And source area 212 is then handed over drain region 214
For being configured among grid, so that 212 surrounding of any source area is surrounded by four drain regions 214, any drain region 214 is by four
Source area 212 surrounds.Contact areas 250 is surrounded on the periphery of the metal oxide semiconductor device 210 of grid shape.
Metal oxide semiconductor device is arranged in metal oxide semiconductor device of the grid shape at grid shape center
210b is farthest apart from contact areas 250, and in the metal oxide semiconductor device 210a of grid shape edge apart from contact areas 250
Recently, the inconsistent problem of parasitism BJT turn-on time is even more serious.Therefore, it can leaked according to the mode of above-described embodiment
The conductivity type of doped region 240, the conductivity type of doped region 240 and source area 212 and drain region 214 is set below polar region 214 not
Together.It is designed to be greater than apart from contact areas 250 farther out in area/doping concentration apart from the closer doped region 240a in contact areas 250
Doped region 240b area/doping concentration.Alternatively, from the doped region 240b below the drain region 214b far from contact areas 250
It is designed to gradually be incremented by area/doping concentration close to the doped region 240a below the drain region 214a of contact areas 250, use
Doped region 240 and contact areas 250 are corrected apart from difference caused by difference, so that the breakdown voltage of each parasitism BJT is roughly the same,
Change can make the turn-on time of each BJT almost consistent.
In the above embodiment, contact areas is surrounded on the periphery of the metal oxide semiconductor device of grid shape.However,
The present invention is not limited thereto.Contact areas also can be set in two adjacent metal oxide semiconductor devices or adjacent two
Between the metal oxide semiconductor device of group.
In summary, the doped region different with its conductivity type, which is arranged, in the embodiment of the present invention below drain region to mention
Rise the viability of ESD-protection structure.In addition, dense by the area/doping for changing the doped region being located at below drain region
Degree, can correct doped region and contact areas distance it is different caused by difference so that the collapse of each parasitism BJT of different zones is electric
Press it is roughly the same, can be so that the turn-on time of each BJT be almost consistent.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, those skilled in the art,
It does not depart from the spirit and scope of the present invention, when can make some changes and embellishment, therefore protection scope of the present invention is appended by the view
Subject to claims confining spectrum.
Claims (13)
1. a kind of ESD-protection structure, characterized by comprising:
Substrate；
Contact areas is located in the substrate；
First metal oxide semiconductor device is located in the substrate, including the first drain region with the first conductive type；
Second metal oxide semiconductor device is located in the substrate, including one second leakage with the first conductive type
Polar region, wherein first drain region, second drain region is close to the contact areas；
First doped region has the second conductive type, is located at below first drain region；And
Second doped region has the second conductive type, is located at below second drain region, wherein first doped region
Area is greater than the area of second doped region.
2. ESD-protection structure as described in claim 1, wherein the first conductive type is N-type, described second is conductive
Type is p-type.
3. ESD-protection structure as described in claim 1, wherein the first conductive type is p-type, described second is conductive
Type is N-type.
4. ESD-protection structure as described in claim 1, wherein first metal oxide semiconductor device and institute
Stating the second metal oxide semiconductor device is side by side at finger-shaped metal oxide semiconductor device.
5. ESD-protection structure as described in claim 1, wherein first metal oxide semiconductor device and institute
Stating the second metal oxide semiconductor device is grid shape metal oxide semiconductor device.
6. ESD-protection structure as described in claim 1, wherein the contact areas is ring-type, the first metal oxidation
Object semiconductor element and second metal oxide semiconductor device are located within the region that the contact areas is enclosed.
7. a kind of ESD-protection structure, characterized by comprising:
Substrate；
Contact areas is located in the substrate；
Multiple metal oxide semiconductor devices are located in the substrate, are respectively provided with the drain region of the first conductive type；
Multiple doped regions have the second conductive type and are located under the drain region of each metal oxide semiconductor device
Side,
Wherein gradually passed from the area of the doped region to the doped region close to the contact areas far from the contact areas
Increase.
8. ESD-protection structure as claimed in claim 7, wherein the first conductive type is N-type, described second is conductive
Type is p-type.
9. ESD-protection structure as claimed in claim 7, wherein the first conductive type is p-type, described second is conductive
Type is N-type.
10. ESD-protection structure as claimed in claim 7, wherein these metal oxide semiconductor devices be side by side at
Finger-shaped metal oxide semiconductor device.
11. ESD-protection structure as claimed in claim 7, wherein these metal oxide semiconductor devices are grid shape
Metal oxide semiconductor device.
12. ESD-protection structure as claimed in claim 7, wherein the contact areas is ring-type, these metal oxides
Semiconductor element is located within the region that the contact areas is enclosed.
13. a kind of ESD-protection structure, characterized by comprising:
Substrate；
Contact areas is located in the substrate；
First metal oxide semiconductor device is located in the substrate, including the first drain region with the first conductive type；
Second metal oxide semiconductor device is located in the substrate, including one second leakage with the first conductive type
Polar region, wherein first drain region, second drain region is close to the contact areas；
First doped region has the second conductive type, is located at below first drain region；And
Second doped region has the second conductive type, is located at below second drain region, wherein first doped region
Area, doping concentration or both are greater than the area of second doped region, doping concentration or both,
Wherein first doped region and second doped region are configured in the substrate, and the doping of first doped region
Concentration and the doping concentration of second doped region are different from around the described of first doped region and second doped region
The doping concentration of substrate.
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| CN106328648A (en) * | 2015-07-03 | 2017-01-11 | 台湾类比科技股份有限公司 | Integrated circuit and self-protection output buffer |
| CN107623000B (en) * | 2016-07-15 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection circuit and manufacturing method thereof |
| CN108807362B (en) * | 2017-04-26 | 2021-02-23 | 旺宏电子股份有限公司 | Electrostatic discharge protection device and electrostatic discharge method |
| US11430951B2 (en) * | 2020-04-24 | 2022-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistive memory cell with switching layer comprising one or more dopants |
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