CN101645447A - Static discharge protection circuit element - Google Patents
Static discharge protection circuit element Download PDFInfo
- Publication number
- CN101645447A CN101645447A CN200810146107A CN200810146107A CN101645447A CN 101645447 A CN101645447 A CN 101645447A CN 200810146107 A CN200810146107 A CN 200810146107A CN 200810146107 A CN200810146107 A CN 200810146107A CN 101645447 A CN101645447 A CN 101645447A
- Authority
- CN
- China
- Prior art keywords
- type
- protection circuit
- region
- area
- static discharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a static discharge protection circuit element, which comprises an N-type laterally diffused metal oxide semiconductor (LDNMOS) element comprising a P-type substrate and an N-type deep well region. The P-type substrate comprises a first region and a second region. The N-type deep well region is positioned in the first region and the second region of the P-type substrate. TheLDNMOS element further comprises a gate positioned on the P-type substrate between the first region and the second region, a P-type injection region positioned in the first region, an N-type stage region positioned in the N-type deep well region in the first region, an N-type first doped region positioned in the N-type stage region, a P-type substrate region positioned in the second region, an N-type second doped region positioned in the P-type substrate region, and a P-type doped region positioned in the P-type substrate region and adjacent to the N-type second doped region.
Description
Technical field
The present invention relates to a kind of semiconductor element, relate more specifically to a kind of Laterally Diffused Metal Oxide Semiconductor (lateral double diffused metal oxidesemiconductor that is used for ESD protection circuit; LDMOS) element.
Background technology
Static discharge (Electrostatic Discharge; ESD) be to cause most electronic component or electronic system to be subjected to excessively electrically stress (Electrical Overstress; EOS) principal element of Po Huaiing.This destruction can cause semiconductor element and the nonvolatil breaking-up of computer system, thereby influences integrated circuit (Integrated Circuits; ICs) circuit function makes that electronic product work is undesired.
In deep-sub-micrometer semiconductor technology, since the component size micro, the static discharge of element (Electrostatic Discharge; ESD) the relative variation of tolerance level, therefore, the electrostatic discharge protective design must be considered when IC designs.Usually the static discharge tolerance level of commercial IC is essential by human body discharge mode (Human Body Model; HBM) 2kV and machine discharge mode (MachineModel; MM) test of 200V.
In order to bear high-tension electrostatic discharge testing like this, the protecting component for electrostatic discharge on the IC often has the design of big component size.In order to save die area as far as possible, on layout (layout), this large-sized element is realized in the mode of finger-like (multi-finger) usually.
Yet; for the LDMOS element that is widely used in power management at present; the LDMOS element of finger-like at present still can't be by the test of human body discharge mode (HBM) 2kV and machine discharge mode (MM) 200V; therefore, need the element that a kind of LDMOS element with enough static discharge tolerance levels is used as ESD protection circuit badly.
Summary of the invention
The invention provides a kind of LDMOS element that is used for ESD protection circuit, it has higher static discharge tolerance level.
The present invention proposes a kind of static discharge protection circuit element, and it comprises at least one Laterally Diffused Metal Oxide Semiconductor (LDMOS) element.This LDMOS element comprises the substrate with first conductivity type, the deep-well district with second conductivity type.Substrate comprises first area and second area.The deep-well district is positioned within the first area and second area of substrate.This LDMOS element also comprises grid, have the injection region of first conductivity type, have second conductivity type the rank district, have second conductivity type first doped region, have first conductivity type matrix area, have second doped region of second conductivity type and doped region with first conductivity type.Grid is in the substrate between first area district and the second area.The injection region is positioned at the first area of substrate.The rank district is arranged in the deep-well district of first area.First doped region is arranged in the rank district.Matrix area is arranged in the deep-well district of second area.Second doped region is arranged in matrix area.Doped region is arranged in matrix area, and adjacent with second doped region.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned injection region is between first doped region and rank district.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned injection region is positioned at first doped region below.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned injection region is positioned among the district of rank.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned injection region is between rank district and deep-well district.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned injection region is positioned among the deep-well district.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned first conductivity type is the P type, above-mentioned second conductivity type is the N type.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned first conductivity type is the N type, above-mentioned second conductivity type is the P type.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for also comprises the second conductivity type light doping section, in the matrix area between the grid and second doped region.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for also comprises: have the wellblock of first conductivity type, be positioned at the periphery in deep-well district; And protective ring, be arranged in the wellblock.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for also comprises isolation structure, between the protective ring and second doped region.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, above-mentioned isolation structure comprises field oxide structure or fleet plough groove isolation structure.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for comprises a plurality of above-mentioned LDMOS elements.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, a plurality of grids of above-mentioned those LDMOS elements are connected to each other.
Described according to embodiments of the invention, the above-mentioned static discharge protection circuit element that is used for, a plurality of grids of above-mentioned those LDMOS elements connect and are many finger-like.
The LDMOS element that is used for ESD protection circuit of the present invention, its doped region below as drain electrode forms the injection region and can reach the purpose that promotes tolerance level really.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperation institute accompanying drawing are described in detail below.
Description of drawings
Fig. 1 is the generalized section according to the LDNMOS element that is used for ESD protection circuit that embodiments of the invention illustrated.
Figure 1A is the vertical view according to the LDNMOS element that is used for ESD protection circuit that embodiments of the invention illustrated.
Fig. 2 is the generalized section according to the LDNMOS element that is used for ESD protection circuit that another embodiment of the present invention illustrated.
Fig. 3 is the generalized section according to the LDNMOS element that is used for ESD protection circuit that another embodiment of the present invention illustrated.
Fig. 4 is the generalized section of the LDNMOS element that is used for ESD protection circuit that illustrated according to an embodiment more of the present invention.
Fig. 5 is respectively the measured electrical graph of a relation before encapsulating according to the formed LDNMOS of experimental example of the present invention.
Description of reference numerals
10,20:LDNMOS element
The substrate of 100:P type
101a, 101b: isolation structure
The 102:N type deep well area
104a, 104b:P mold base district
106,108a, 108b:N type doped region
110a, 110b: grid
116a, 116b:P type wellblock
134a, 134b:P type doped region
118a, 118b: protective ring
130:N type rank district
132:P type injection region
136a, 136b:N type light doping section
140: the first area
150a, 150b: second area
Embodiment
The LDMOS element that is used for ESD protection circuit of the present invention can be LDNMOS element or LDPMOS element.Below be to illustrate, wherein represent first conductivity type, and represent second conductivity type, but the present invention be not as limit with the N type with the P type with the LDNMOS element.Persons skilled in the art should be appreciated that the present invention can also be replaced as the N type with first conductivity type, and second conductivity type is replaced as the P type to form the LDPMOS element.
Below, the static discharge protection circuit element that will be constituted with two LDNMOS elements is that example elaborates, but is not that the present invention does not do special restriction to the quantity of LDMOS element in order to qualification the present invention.
Fig. 1 is the generalized section according to the LDNMOS element that is used for ESD protection circuit that embodiments of the invention illustrated.
Please refer to Fig. 1, static discharge protection circuit element comprises LDNMOS element 10,20, and it comprises P type substrate 100 and N type deep well area 102.P type substrate 100 is divided into first area 140, second area 150a and second area 150b.First area 140 is between second area 150a and second area 150b.N type deep well area 102 is positioned among first area 140, second area 150a and the second area 150b of substrate 100.In an embodiment, the energy of formation N type deep well area 102 for example is 1600～2000KeV; Dosage for example is 10
11～3 * 10
12/ cm
2
The LDNMOS element 10 that is used for ESD protection circuit also comprises grid 110a, N type first doped region 106, N type rank district (grade region) 130, two the N type second doped region 108a, P type doped region 134a and P mold base district 104a.LDNMOS element 20 also comprises grid 110b, N type first doped region 106, N type rank district 130, two the N type second doped region 108b, P type doped region 134b and P mold base district 104b.
N type rank district 130, it is arranged in the deep-well district 102 of first area 140.In an embodiment, the energy in formation N type rank district 130 for example is 50～150KeV; Dosage for example is 10
11～5 * 10
12/ cm
2
N type first doped region 106 for example is the N+ doped region, and it is arranged in the rank district 130 with conductivity type, as the common drain district of the LDNMOS element 10,20 that is used for ESD protection circuit, electrically connects by contact hole and weld pad.In an embodiment, the energy of formation N type first doped region 106 for example is 60～100KeV; Dosage for example is 10
14～2 * 10
15/ cm
2
P mold base district 104a, 104b lay respectively in the interior N type deep well area 102 of second area 150a, 150b.In an embodiment, the energy of formation P mold base district 104a, 104b for example is 160～200KeV; Dosage for example is 10
12～4 * 10
13/ cm
2
The N type second doped region 108a, 108b are the N+ doped region for example, lay respectively among matrix area 104a, the 104b, as the source area of the LDNMOS element 10,20 that is used for ESD protection circuit.In an embodiment, the energy of the formation N type second doped region 108a, 108b for example is 60～100KeV; Dosage for example is 10
14～2 * 10
15/ cm
2
P type doped region 134a, 134b for example are the P+ doped region, and it lays respectively among P mold base district 104a, the 104b, and are sandwiched between two N types, the second doped region 108a and two the N type second doped region 108b.In an embodiment, the energy of formation P type doped region 134a, 134b for example is 35～75KeV; Dosage for example is 10
14～3 * 10
15/ cm
2P type doped region 134a, 134b see through contact hole with the N type second doped region 108a, 108b respectively and source electrode electrically connects.
Grid 110a and extends to 130 tops, N type rank district in the first area 140 in the deep-well district 102 between first area 140 and the second area 150a, and extends to the P mold base district 104a top of the part in the second area 150a.Grid 110b and extends to 130 tops, N type rank district in the first area 140 in the deep-well district 102 between first area 140 and the second area 150b, and extends to the P mold base district 104b top of the part in the second area 150b.Grid 110a, 110b are made of grid conducting layer and gate dielectric layer, and the sidewall of grid conducting layer and gate dielectric layer can also form clearance wall.In an embodiment, grid 110a, 110b are electrically connected to each other, and are two finger-like.Certainly, static discharge protection circuit element can be to be made of a plurality of LDNMOS elements, and the grid of each LDNMOS element can be connected to each other, and is many finger-like, shown in Figure 1A.
In an embodiment, the LDNMOS element 10,20 that is used for ESD protection circuit also comprises N type light doping section 136a, 136b respectively.N type light doping section 136a is between grid 110a and the N type second doped region 108a; N type light doping section 136b is between grid 110b and the N type second doped region 108b.
The LDNMOS element 10,20 that is used for ESD protection circuit of the present invention can also comprise p type wells district 116a and 116b and protective ring 118a and 118b.P type wells district 116a, 116b lay respectively at the periphery of N type deep well area 102.Protective ring 118a, 118b lay respectively among N type wellblock 116a, the 116b.In an embodiment, protective ring 118a, 118b are isolated with isolation structure 101a, 101b and the N type second doped region 108a, 108b respectively.Isolation structure 101a, 101b can be that shallow trench isolation is from (STI) structure or field oxide (FOX) structure.
It should be noted that in the present invention the LDMOS element 10,20 that is used for ESD protection circuit also comprises P type injection region 132, it is positioned at the first area 140 of substrate 100.Admixture in the P type injection region 132 for example is a boron.The area of P type injection region 132 is greater than the area of N type first doped region 106, and less than the area in N type rank district 130.P type injection region 132 can with existing C DMOS process integration, only need can form by the formation of injecting mask and the execution of ion implantation technology.The formation opportunity of P type injection region 132 is also without particular limitation.The degree of depth of the injection of P type injection region 132 is relevant with the energy of its injection, and the energy of its injection is about 10～250KeV.In an embodiment, the dosage of P type injection region 132 is 0.5～1.5 times of dosage in N type rank district 130.In another embodiment, the dosage of P type injection region 132 is 0.7～1.3 times of dosage in N type rank district 130.In another embodiment, the dosage of P type injection region 132 is 0.9～1.1 times of dosage in N type rank district 130.
Please refer to Fig. 1, in an embodiment, P type injection region 132 is between N type first doped region 106 and N type rank district 130.The energy that forms P type injection region 132 for example is 10～15KeV; Dosage for example is 2 * 10
13～8 * 10
13/ cm
2
In another embodiment, please refer to Fig. 2, P type injection region 132 is positioned among the N type rank district 130.The energy that forms P type injection region 132 for example is 15～25KeV; Dosage for example is 2 * 10
13～8 * 10
13/ cm
2
In another embodiment, please refer to Fig. 3, P type injection region 132 is between N type rank district 130 and N type deep well area 102.The energy that forms P type injection region 132 for example is 25～35KeV; Dosage for example is 2 * 10
13～8 * 10
13/ cm
2
In another embodiment, please refer to Fig. 4, P type injection region 132 is positioned among the N type deep well area 102.The energy that forms P type injection region 132 for example is 100～200KeV; Dosage for example is 2 * 10
13～8 * 10
13/ cm
2
With the LDNMOS element 10 that is used for ESD protection circuit of the present invention shown in Figure 4; when the ESD magnitude of voltage that is applied during greater than the breakdown voltage of the face that connects of the N type deep well area 102 of LDNMOS element 10 and P mold base district 104a, P type injection region 132; see through avalanche breakdown mechanism (avalanche breakdown mechanism), will produce electron stream and hole stream.Hole stream will be flowed through P mold base district 104a and be arrived the P type doped region 134a that is connected with source electrode line, make the voltage quasi position of P mold base district 104a, P type injection region 132 increase.Know clearly it, when cross-pressure in the cut-in voltage (cut-in voltage) of the ohmically pressure drop of P mold base district 104a greater than side direction npn BJT, the side direction npn BJT that is made of N type deep well area 102, P mold base district 104a and the N type second doped region 108a will be triggered.After being unlocked of side direction npn BJT, hole stream will inject via P type injection region 132 and be injected in P type doped region 134a, to increase the voltage quasi position of P type injection region 132.Then, when institute's injected holes flows greater than critical value, the Vertical n pn BJT that is made of N type first doped region 106, P type injection region 132 and N type deep well area 102 will be unlocked.In case side direction npn BJT and Vertical n pn BJT are unlocked simultaneously, form low impedance path at N type first doped region 106, P type injection region 132, N type deep well area 102 and P type doped region 134a, with effective release ESD electric current.
Similarly; the LDNMOS element 10 that is used for ESD protection circuit for Fig. 1～3; formed P type injection region 132 between N type first doped region 106 and N type rank district 130; or among N type rank district 130 formed P type injection region 132; or be formed P type injection region 132 between N type rank district 130 and N type deep well area 102; all can with N type first doped region 106; N type deep well area 102 constitutes Vertical n pn BJT; and with N type deep well area 102; P mold base district 104a; the side direction npn BJT that the N type second doped region 108a forms forms low impedance path, with effective release ESD electric current.
In above embodiment, all be to illustrate with P type injection region 132 single and that be positioned under N type first doped region 106.Yet the present invention is as limit, and P type injection region 132 can be that the zonule by a plurality of separation is constituted.For example be that P type injection region 132 is made of a plurality of zonules parallel with substrate surface.Or be, constituted by a plurality of zonule of vertical arrangement, for example, P type injection region 132 can be optionally simultaneously the position Fig. 1 to any two, three zones shown in Figure 4 or simultaneously the position among these four zones.
P type injection region 132 also is not limited under N type first doped region 106, its can depart from slightly N type first doped region 106 under and near grid 110a or 110b.In addition, the concentration of P type injection region 132 is not limited to even distribution, also can become Gradient distribution.
Experimental example is to be used as being used for the ESD static discharge protection circuit element with LDNMOS element of the present invention 18 volts.The formed LDNMOS element of experimental example is before encapsulating, and the electrical graph of a relation after measuring as shown in Figure 5.Formed LDNMOS element of experimental example and traditional LDNMOS element are after encapsulating, and the result after human body discharge mode (HBM) and machine discharge mode (MM) are measured is respectively shown in table 1 and table 2.
Table 1
Table 2
Result by Fig. 5 shows: electric current and its trigger voltage that the LDNMOS element of experimental example can tolerate more than 8 amperes can maintain about 23 volts.
Shown by table 1,2 result: the result of human body discharge mode (HBM) test of experimental example is greater than 8.0kV; The result of machine discharge mode (MM) test is greater than 800V.
Comprehensive the above; the injection region that the LDMOS element that is used for ESD protection circuit of the present invention can increase different conductivity types below as the doped region of drain electrode can reach the usefulness that promotes the esd protection element that is used for high voltage device really, makes it can be by the essential test by human body discharge mode (HBM) 2kV and machine discharge mode (MM) 200V of static discharge tolerance level of commercial IC.
In addition, the LDMOS element that is used for ESD protection circuit of the present invention can be applied in the semiconductor element (power management IC) of all power managements, technology simple and can with existing C DMOS process integration, and cost is low, has competitiveness.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those of ordinary skill under any in the technical field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, thus protection scope of the present invention with claim the person of being defined be as the criterion.
Claims (15)
1. static discharge protection circuit element, it comprises at least one laterally diffused metal oxide semiconductor element, this laterally diffused metal oxide semiconductor element comprises:
Substrate with first conductivity type, this substrate comprises first area and second area;
Deep-well district with second conductivity type is positioned within this first area and this second area of this substrate;
Grid is in this substrate between this first area and this second area;
Injection region with first conductivity type is positioned at this first area of this substrate;
Rank district with second conductivity type is arranged in this deep-well district of this first area;
First doped region with this second conductivity type is arranged in this rank district;
Matrix area with this first conductivity type is arranged in this deep-well district of this second area;
Have second doped region of this second conductivity type, be arranged in this matrix area; And
Doped region with this first conductivity type is arranged in this matrix area, and is adjacent with this second doped region.
2. static discharge protection circuit element as claimed in claim 1, wherein this injection region is between this first doped region and this rank district.
3. static discharge protection circuit element as claimed in claim 1, wherein this injection region is positioned at this first doped region below.
4. static discharge protection circuit element as claimed in claim 1, wherein this injection region is positioned among this rank district.
5. static discharge protection circuit element as claimed in claim 1, wherein this injection region is between this rank district and this deep-well district.
6. static discharge protection circuit element as claimed in claim 1, wherein this injection region is positioned among this deep-well district.
7. static discharge protection circuit element as claimed in claim 1, wherein this first conductivity type is the P type, this second conductivity type is the N type.
8. static discharge protection circuit element as claimed in claim 1, wherein this first conductivity type is the N type, this second conductivity type is the P type.
9. static discharge protection circuit element as claimed in claim 1 also comprises the second conductivity type light doping section, in this matrix area between this grid and this second doped region.
10. static discharge protection circuit element as claimed in claim 1 also comprises:
Wellblock with this first conductivity type is positioned at the periphery in this deep-well district; And
Protective ring is arranged in this wellblock.
11. static discharge protection circuit element as claimed in claim 10 also comprises isolation structure, between this protective ring and this second doped region.
12. static discharge protection circuit element as claimed in claim 11, wherein this isolation structure comprises field oxide structure or fleet plough groove isolation structure.
13. static discharge protection circuit element as claimed in claim 1, it comprises a plurality of these laterally diffused metal oxide semiconductor elements.
14. static discharge protection circuit element as claimed in claim 13, wherein a plurality of grids of these a plurality of laterally diffused metal oxide semiconductor elements are connected to each other.
15. static discharge protection circuit element as claimed in claim 14, wherein a plurality of grids of these a plurality of laterally diffused metal oxide semiconductor elements connect and are many finger-like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101461071A CN101645447B (en) | 2008-08-06 | 2008-08-06 | Static discharge protection circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101461071A CN101645447B (en) | 2008-08-06 | 2008-08-06 | Static discharge protection circuit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101645447A true CN101645447A (en) | 2010-02-10 |
| CN101645447B CN101645447B (en) | 2011-05-04 |
Family
ID=41657244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101461071A Active CN101645447B (en) | 2008-08-06 | 2008-08-06 | Static discharge protection circuit element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101645447B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569384A (en) * | 2010-12-17 | 2012-07-11 | 无锡华润上华半导体有限公司 | Groove MOSFET (metal-oxide-semiconductor field-effect transistor) device and manufacturing method thereof |
| CN104299966A (en) * | 2013-07-15 | 2015-01-21 | 联华电子股份有限公司 | Electrostatic discharge protection structure |
| CN105226094A (en) * | 2014-06-19 | 2016-01-06 | 旺宏电子股份有限公司 | Semiconductor structure |
| CN105489594A (en) * | 2014-09-16 | 2016-04-13 | 旺宏电子股份有限公司 | Semiconductor structure |
| CN104183596B (en) * | 2013-05-22 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | ESD-protection structure |
| CN107887375A (en) * | 2016-09-29 | 2018-04-06 | 联华电子股份有限公司 | Semiconductor electrostatic discharge prevention element |
| CN111415930A (en) * | 2019-01-07 | 2020-07-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure and electrostatic discharge protection circuit |
| CN111415929A (en) * | 2019-01-07 | 2020-07-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure and electrostatic discharge protection circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002237591A (en) * | 2000-12-31 | 2002-08-23 | Texas Instruments Inc | Dmos transistor source structure and method for manufacturing the same |
| JP2006108208A (en) * | 2004-10-01 | 2006-04-20 | Nec Electronics Corp | Semiconductor device containing ldmos transistor |
-
2008
- 2008-08-06 CN CN2008101461071A patent/CN101645447B/en active Active
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569384A (en) * | 2010-12-17 | 2012-07-11 | 无锡华润上华半导体有限公司 | Groove MOSFET (metal-oxide-semiconductor field-effect transistor) device and manufacturing method thereof |
| US8772864B2 (en) | 2010-12-17 | 2014-07-08 | Csmc Technologies Fab1 Co., Ltd. | Trench MOSFET device and method for fabricating the same |
| CN102569384B (en) * | 2010-12-17 | 2015-07-01 | 无锡华润上华半导体有限公司 | Groove MOSFET (metal-oxide-semiconductor field-effect transistor) device and manufacturing method thereof |
| CN104183596B (en) * | 2013-05-22 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | ESD-protection structure |
| CN104299966A (en) * | 2013-07-15 | 2015-01-21 | 联华电子股份有限公司 | Electrostatic discharge protection structure |
| CN104299966B (en) * | 2013-07-15 | 2019-07-19 | 联华电子股份有限公司 | ESD-protection structure |
| CN105226094A (en) * | 2014-06-19 | 2016-01-06 | 旺宏电子股份有限公司 | Semiconductor structure |
| CN105226094B (en) * | 2014-06-19 | 2018-10-02 | 旺宏电子股份有限公司 | Semiconductor structure |
| CN105489594A (en) * | 2014-09-16 | 2016-04-13 | 旺宏电子股份有限公司 | Semiconductor structure |
| CN107887375A (en) * | 2016-09-29 | 2018-04-06 | 联华电子股份有限公司 | Semiconductor electrostatic discharge prevention element |
| CN111415930A (en) * | 2019-01-07 | 2020-07-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure and electrostatic discharge protection circuit |
| CN111415929A (en) * | 2019-01-07 | 2020-07-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure and electrostatic discharge protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101645447B (en) | 2011-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7655980B1 (en) | Device for ESD protection circuit | |
| CN101645447B (en) | Static discharge protection circuit element | |
| US7906810B2 (en) | LDMOS device for ESD protection circuit | |
| CN100452433C (en) | Semiconductor device and high voltage p-type metal oxide semiconductor (HVPMOS) device | |
| US8044457B2 (en) | Transient over-voltage clamp | |
| CN100394596C (en) | ESD protection device and semiconductor chip | |
| US9431389B2 (en) | ESD transistor for high voltage and ESD protection circuit thereof | |
| US7709896B2 (en) | ESD protection device and method | |
| US8530969B2 (en) | Semiconductor device | |
| CN104037171B (en) | Semiconductor element and manufacture method thereof and operational approach | |
| JP2004047959A (en) | Electrostatic discharge protection element | |
| CN105206609A (en) | Compact guard ring structure for cmos integrated circuits | |
| KR101051684B1 (en) | Electrostatic discharge protection device and manufacturing method | |
| US20150129977A1 (en) | Semiconductor electrostatic discharge protection apparatus | |
| US7190030B1 (en) | Electrostatic discharge protection structure | |
| Chen et al. | Circuit and layout co-design for ESD protection in bipolar-CMOS-DMOS (BCD) high-voltage process | |
| CN107346786B (en) | GGNMOS transistor, multi-finger GGNMOS device and circuit | |
| US10269898B2 (en) | Surrounded emitter bipolar device | |
| US9153570B2 (en) | ESD tolerant I/O pad circuit including a surrounding well | |
| TW201334183A (en) | Semiconductor device | |
| Marreiro et al. | Substrate Isolation Options Effect on HV Latch-up | |
| US9659923B2 (en) | Electrostatic discharge (ESD) protection circuits, integrated circuits, systems, and methods for forming the ESD protection circuits | |
| JP2002094001A (en) | Esd protection structure of semiconductor integrated circuit | |
| Zhan et al. | High-voltage asymmetrical bi-directional device for system-level ESD protection of automotive applications on a BiCMOS technology | |
| US20110095368A1 (en) | Electrostatic discharge protection device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |