JP2002094001A - Esd protection structure of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ESD(electrostatic discharge) protective structure which is capable of securing satisfactory parasitic SCR operation, even in a semiconductor integrated circuit of a process of 0.25 μm or smaller in which STI(shallow trench isolation) for isolation is adopted, and further is capable of preventing damages to a gate oxide film of 10 nm or thinner, even if a surge due to ESD is applied to the gate oxide film. SOLUTION: By arranging a P- diffused region 4 under a P+ diffused region 8 to include the P+ diffused region 8, a parasitic PNP bipolar transistor 13 is constituted by the combination of a P-well region 2, an N-well region 3, and P- diffused region 4. The boundary between the P- diffused region 4 and the N-well region 3 is arranged deeper than the bottom face of the isolation 9 of the STI structure. With such a constitution, the parasitic PNP bipolar transistor 13 can have a short base width, and the bipolar operation is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to integrated circuits,
More specifically, the present invention relates to an ESD protection structure for a semiconductor integrated circuit that protects an integrated circuit from electrostatic discharge (ESD).

[0002]

2. Description of the Related Art Integrated circuit chips are subjected to ESD from the chip package assembling process to the mounting on a set board.
May damage the semiconductor element. ESD refers to static electricity from a non-conductive surface entering an input / output pad of an integrated circuit and escaping to ground.

[0003] For example, static electricity charged to the human body has a considerable amount of electric charge of several thousands V or less under high humidity and 10,000 V or more under low humidity. Upon touching the integrated circuit, electrostatic charges flow from the human body into the integrated circuit, producing ESD with energy levels of up to millions of joules and short discharge times of only nanoseconds or microseconds. As a result, the instantaneous power levels of ESD can be as high as hundreds of kilowatts, with currents up to tens of amps, causing severe damage to integrated circuits. An ESD protection element is provided in the integrated circuit so that the static electricity flows to the ground without destroying the semiconductor element in the integrated circuit.

FIG. 6 shows an ESD protection structure of a conventional semiconductor integrated circuit. P-type silicon substrate 1, P-type well region 2, N-type well region 3, P ⁺ -type diffusion region 5, N ⁺ -type diffusion region 6, N ⁺ -type diffusion region 7, P ⁺ -type diffusion region 8, isolation 9, gate 10 and side walls 11. The MOS transistor is constituted by the gate 10, the N ⁺ type diffusion region 6 and the N ⁺ type diffusion region 7.

[0005] P-type well region 2, N-type well region 3,
^The parasitic PNP bipolar transistor 24 is formed by combining the ⁺ type diffusion regions 8 while the N ⁺ type diffusion regions 6 and P
Parasitic NPN bipolar transistor 23 is formed by combining type well region 2 and N type well region 3. The collector of the parasitic PNP bipolar transistor 24 is electrically connected to the base of the parasitic NPN bipolar transistor 23, and similarly, the collector of the parasitic NPN bipolar transistor 23 is electrically connected to the base of the parasitic PNP bipolar transistor 24. . A parasitic SCR is thus configured. N-type well region 3 is connected to an input / output pad via P ⁺ -type diffusion region 8, and P-type well region 2 is connected to ground potential Vs via P ⁺ -type diffusion region 5.
Connected to s.

FIG. 7 shows an ESD protection circuit of a semiconductor integrated circuit. This is because the above-mentioned SCR
The protection device 25 is connected. 26 is PMO
SFET, 27 is an NMOSFET. The ESD protection structure as shown in FIG.
(IEEE Electron Devices Letters, Vol. 12, 199121-
22). According to this LO to separation
SCR fabricated by 0.8 μm CMOS process using COS,
It operates with a trigger voltage of 10 V or less and a trigger current of 10 mA or less.

[0007]

In the case of a fine process after the 0.25 μm process, STI (Shallow Trench I
solation) is used. The STI can be formed deeply in the silicon substrate, and the depletion layer is hardly spread, and has extremely excellent element isolation characteristics as compared with the LOCOS. As a result, there arises a problem that the parasitic PNP bipolar transistor 24 in FIG. 6 does not function as a bipolar transistor.

Further, the gate oxide film thickness has reached 10 nm or less due to miniaturization, and measures for preventing the gate oxide film from being broken have become more important.

A sample of the ESD protection structure shown in FIG. 6 is manufactured by a 0.18 μm CMOS process using STI for separation, and S
The result of confirming the CR operation is shown in FIG. Voltage application condition,
FIG. 5A shows the voltage and current measurement points.

The distance Wd from the boundary between the P-type well region 2 and the N-type well region 3 to the boundary between the N ⁺ -type diffusion region 7 and the isolation 9 is
It was 1.0 μm. This is a result of considering the misalignment of the implantation mask during processing and the inflow region of carriers moving from the N well region 3 to the N ⁺ type diffusion region 7. Also, N ⁺
Width Wsti of isolation 9 between p-type diffusion region 7 and P ⁺ -type diffusion region 8
Was set to 0.6 μm. This is a result in consideration of misalignment of the implantation mask during processing. From the above, the base width W of the parasitic PNP bipolar transistor 24 is 1.6 μm.

FIG. 5B shows Iio when Vio is plotted on the horizontal axis.
Characteristic 101, Iio characteristic 102 when Vd is plotted on the horizontal axis, Vio
The Iio characteristic 103 when the difference potential between io and Vd is plotted on the horizontal axis is shown. The parasitic NPN bipolar transistor 23 has a trigger voltage of 6
It turns out that it is operating at V. On the other hand, judging from the Iio characteristic 103 when the difference potential between Vio and Vd is plotted on the horizontal axis,
Parasitic PNP bipolar transistor 24 does not operate in bipolar mode. Up to 15 V, the resistance value increases as the voltage increases. This is because the depletion layer expands as the voltage increases, and at the same time, the resistance value increases. When the voltage exceeds 15 V, the current caused by the avalanche breakdown generated between the P-type well region 2 and the N-type well region 3 becomes dominant,
It is considered that the current also increases as shown in the figure as the voltage increases. When the voltage reaches 18V, the depletion layer in the N-type well region 3, to reach the P ⁺ -type diffusion region 8, causing a punch-through between the P-type well region 2 and P ⁺ -type diffusion region 8, the current It is thought to increase sharply. Note that Wsti is 0.3 μm, and the base width of the parasitic PNP bipolar transistor 24 is
A sample with a W of 1.3 μm was prepared and evaluated in the same way.
The parasitic PNP bipolar transistor 24 did not operate.

An object of the present invention is to use STI for separation, to ensure good SCR operation even in a 0.25 μm process or later process having good separation characteristics, and to apply a surge due to ESD to a gate oxide film of 10 nm or less. An object of the present invention is to provide an ESD protection structure for a semiconductor integrated circuit which can prevent the gate oxide film from being destroyed even if it is used.

[0013]

According to a first aspect of the present invention, there is provided an ESD protection structure for a semiconductor integrated circuit for protecting a circuit to which an operating voltage is applied, comprising: a substrate; First and second well regions formed adjacently in a substrate; first and second diffusion regions formed in the first well region; first and second well regions; A third diffusion region formed over the second diffusion region, a fourth diffusion region formed in the second well region, a fifth diffusion region formed in the fourth diffusion region,
A gate formed to cover the first well region between the second diffusion region and the third diffusion region; and a MOS transistor is constituted by the gate, the second diffusion region, and the third diffusion region. , The first well region, the second well region, and the fourth diffusion region constitute a parasitic bipolar transistor.

According to the ESD protection structure of the semiconductor integrated circuit of the first aspect, the base width of the parasitic bipolar transistor can be reduced by the fourth diffusion region, and the operation of the parasitic bipolar transistor can be performed even when STI is used for isolation. It becomes possible.

According to another aspect of the present invention, the substrate is a silicon substrate and is a P-type.

According to the ESD protection structure for a semiconductor integrated circuit of the second aspect, the same effect as that of the first aspect can be obtained.

According to a third aspect of the present invention, there is provided an ESD protection structure for a semiconductor integrated circuit, wherein the first well region is P
And the second well region is N-type.

According to the ESD protection structure for a semiconductor integrated circuit according to the third aspect, the same effect as that of the second aspect can be obtained.

According to a fourth aspect of the present invention, there is provided an ESD protection structure for a semiconductor integrated circuit according to the third aspect, wherein the first diffusion region, the fourth diffusion region, and the fifth diffusion region are P-type, and the second diffusion region is provided. And the third diffusion region is N-type.

According to the ESD protection structure for a semiconductor integrated circuit of the fourth aspect, the same effect as that of the third aspect can be obtained.

According to a fifth aspect of the present invention, there is provided an ESD protection structure for a semiconductor integrated circuit according to the first aspect, wherein the third diffusion region and the fifth diffusion region are separated by STI.

According to the ESD protection structure for a semiconductor integrated circuit according to the fifth aspect, the same effect as that of the first aspect is obtained.

According to a sixth aspect of the present invention, in the ESD protection structure of the fifth aspect, the depth of the fourth diffusion region is larger than the STI.

According to the ESD protection structure for a semiconductor integrated circuit according to the sixth aspect, the same effect as that of the fifth aspect can be obtained.

According to a seventh aspect of the present invention, there is provided an ESD protection structure for a semiconductor integrated circuit according to the sixth aspect, wherein the gate of the MOS transistor has a sidewall.

According to the ESD protection structure for a semiconductor integrated circuit according to the seventh aspect, the same effect as that of the sixth aspect is obtained.

According to an eighth aspect of the present invention, there is provided an ESD protection structure for a semiconductor integrated circuit according to the seventh aspect, wherein a boundary on the silicon substrate surface between the third diffusion region and the first well region is located below the sidewall. It is.

According to the ESD protection structure for a semiconductor integrated circuit according to the eighth aspect, in addition to the same effect as the seventh aspect, it is necessary to reduce the trigger voltage of the SCR as the thickness of the gate oxide film decreases. However, the design can be performed without considering the gate oxide film destruction of the ESD protection circuit to which the surge voltage applied from the input / output pad is applied first. This allows
When a surge is applied, the gate oxide film of the ESD protection circuit which is most likely to be damaged in the integrated circuit is not damaged, and a highly reliable ESD protection circuit can be manufactured.

According to a ninth aspect of the present invention, in the ESD protection structure of the first aspect, the substrate is a silicon substrate and is an N-type.

According to the ESD protection structure for a semiconductor integrated circuit of the ninth aspect, the same effect as that of the first aspect can be obtained.

The ESD of the semiconductor integrated circuit according to claim 10
The protection structure according to claim 9, wherein the first well region is N-type.
The type and the second well region are P-type.

The ESD of a semiconductor integrated circuit according to claim 10.
According to the protection structure, the same effect as the ninth aspect is obtained.

The ESD of a semiconductor integrated circuit according to claim 11
The protection structure according to claim 3, wherein the first diffusion region, the fourth diffusion region,
11. The ESD protection structure according to claim 10, wherein the first diffusion region and the fifth diffusion region are N-type, and the second diffusion region and the third diffusion region are P-type.

The ESD of a semiconductor integrated circuit according to claim 11
According to the protection structure, the same effect as that of the tenth aspect is obtained.

The ESD of a semiconductor integrated circuit according to claim 12.
The protection structure is an ESD protection structure for a semiconductor integrated circuit for protecting a circuit to which an operating voltage is applied, and includes a substrate,
A third well region formed in the substrate, first and second diffusion regions formed in the third well region, a sixth diffusion region formed in the third well region, Third
A third diffusion region formed over the well region and the sixth diffusion region, and a fifth diffusion region formed in the sixth diffusion region.
And a gate formed to cover the third well region between the second diffusion region and the third diffusion region. The gate, the second diffusion region, and the third diffusion region A MOS transistor is formed, and a vertical parasitic bipolar transistor is formed by the third well region, the sixth diffusion region, and the fifth diffusion region.

The ESD of a semiconductor integrated circuit according to claim 12.
According to the protection structure, since the vertical parasitic bipolar transistor operates in the vertical direction, the same effect as that of the first aspect is obtained.

The ESD of a semiconductor integrated circuit according to claim 13.
In the protective structure according to claim 12, the third diffusion region and the fifth diffusion region are separated by STI.

The ESD of a semiconductor integrated circuit according to claim 13.
According to the protection structure, the same effect as the twelfth aspect is obtained.

The ESD of a semiconductor integrated circuit according to claim 14.
In the protective structure according to the thirteenth aspect, the sixth diffusion region has a depth greater than STI.

14. The ESD of a semiconductor integrated circuit according to claim 14.
According to the protection structure, the same effects as those of the thirteenth aspect are obtained.

The ESD of a semiconductor integrated circuit according to claim 15
The protective structure according to claim 14 has a seventh diffusion region of the same conductivity type as the third well region in the third well region below the sixth diffusion region.

An ESD of a semiconductor integrated circuit according to claim 15.
According to the protection structure, in addition to the same effects as those of the fourteenth aspect, the seventh diffusion region enhances the current driving capability, so that the ESD is improved.
The protection circuit can be designed with a small area. The ESD protection circuit is usually connected to the input / output pads, and as a result, is arranged in a band around the integrated circuit chip. Therefore, if the area occupied by the ESD protection circuit is reduced, the area of the integrated circuit chip is reduced. Of course, the number of integrated circuit chips that can be obtained from one wafer increases, which leads to cost reduction.

[0043]

Embodiments of the present invention will be described below in detail.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 9 is a schematic cross-sectional view illustrating an ESD protection structure of the semiconductor integrated circuit according to the embodiment.

The outline of the SCR, P to include a P ⁺ -type diffusion region 8 under the P ⁺ -type diffusion region 8 ^- the same as that as described with respect to FIG. 6, except in that a diffusion region 4 .

Parasitic PNP bipolar transistor 13
Are P-type well region 2, N-type well region 3,^-Mold diffusion
It is composed of a combination of regions 4. On the other hand, the parasitic NPN
The bipolar transistor 12 has N⁺Mold diffusion
Combination of region 6, P-type well region 2, and N-type well region 3
It is composed of Parasitic PNP bipolar transistor
13 and the parasitic NPN bipolar transistor 12
The SCR is configured. P ^-Diffusion region 4 and N-type well region
The boundary of region 3 is set deeper than the bottom of isolation 9 of STI structure
I do.

With the above configuration, the base width of the parasitic PNP bipolar transistor 13 is reduced, and bipolar operation is enabled.

(Second Embodiment) FIG. 2 is a schematic sectional view illustrating an ESD protection structure of a semiconductor integrated circuit according to a second embodiment of the present invention.

P-type silicon substrate 1, P-type well region 1
4, a P ⁺ type diffusion region 5, an N ⁺ type diffusion region 6, an N ⁺ type diffusion region 7, a P ⁺ type diffusion region 8, an N ⁻ type diffusion region 15, an isolation 9, a gate 10, and a sidewall 11 . The P-type well region 14, the N ⁻ -type diffusion region 15, and the P ⁺ -type diffusion region 8 are combined to form the vertical parasitic PNP bipolar transistor 17, while the N ⁺ -type diffusion region 6, P
Parasitic NPN bipolar transistor 16 is formed by combining type well region 14 and N ⁻ type diffusion region 15. The collector of the vertical parasitic PNP bipolar transistor 17 is electrically connected to the base of the parasitic NPN bipolar transistor 16, and similarly, the collector of the parasitic NPN bipolar transistor 16 is electrically connected to the base of the vertical parasitic PNP bipolar transistor 17. ing. A parasitic SCR is thus configured. N ⁻ type diffusion region 15 is connected to an input / output pad via P ⁺ type diffusion region 8, and P type well region 14 is connected to ground potential Vss via P ⁺ type diffusion region 5. N ^- type diffusion region 1
The boundary between the STI structure 5 and the P-type well region 14 is
Set deeper than the bottom of.

With the above configuration, the vertical parasitic PNP
Since the bipolar transistor 17 operates in the vertical direction, N
⁺ -Type diffusion region 7 under the P-type well region and the N ^- -type the boundary line and the N ⁺ -type diffusion region 7 of the diffusion region 15 in contact with the separation 9 and P ⁺
The bipolar operation becomes possible regardless of the distance between the boundary lines of the mold diffusion region 8.

(Third Embodiment) FIG. 3 is a schematic sectional view illustrating an ESD protection structure of a semiconductor integrated circuit according to a third embodiment of the present invention.

The outline of the SCR is the same as that described with reference to FIG. 2 except that a P-type diffusion region 18 is provided below the N ⁻ type diffusion region 15.

With the above configuration, the vertical parasitic PNP
The parasitic resistance (not shown) between the collector of the bipolar transistor 20 and the base of the parasitic NPN bipolar transistor 19 becomes low, and the current driving capability of the SCR increases. In FIG. 3, the lateral spread of the P-type diffusion region 18 is the same as that of the N ⁻ -type diffusion region 15, but may extend over the entire ESD protection element.

(Fourth Embodiment) FIG. 4 is a schematic sectional view illustrating an ESD protection structure of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

The outline of the SCR is the same as that described with reference to FIG. 1 except that the boundary 22 between the N ⁺ type diffusion region 7 and the P type well region 2 is set below the side wall 11.

With the above configuration, the surge applied from the input / output pad is not directly applied to the thin gate oxide film, and the breakdown of the gate oxide film of 10 nm or less can be prevented. N ⁺ type diffusion region 6, P type well region 2, N ⁺
The NMOSFET composed of the combination of the mold diffusion region 7, the gate 10, and the sidewall 11 has an offset structure, but does not have any problem because it does not need to operate as a MOSFET.

The present invention relates to the case where the silicon substrate is N-type, the case where the first well region is N-type, the case where the second well region is P-type, and the case where the first diffusion region and the fourth diffusion region It is also possible that the region and the fifth diffusion region are N-type, and the second and third diffusion regions are P-type.

[0058]

The ESD of the semiconductor integrated circuit according to claim 1
According to the protection structure, the base width of the parasitic bipolar transistor can be reduced by the fourth diffusion region, and the operation of the parasitic bipolar transistor becomes possible even when STI is used for isolation.

According to the ESD protection structure for a semiconductor integrated circuit of the second aspect, the same effect as that of the first aspect can be obtained.

According to the third aspect of the ESD protection structure for a semiconductor integrated circuit, the same effects as those of the second aspect can be obtained.

According to the ESD protection structure for a semiconductor integrated circuit of the fourth aspect, the same effect as that of the third aspect can be obtained.

According to the ESD protection structure for a semiconductor integrated circuit according to the fifth aspect, the same effect as that of the first aspect can be obtained.

According to the ESD protection structure for a semiconductor integrated circuit of the sixth aspect, the same effect as that of the fifth aspect can be obtained.

According to the ESD protection structure for a semiconductor integrated circuit according to the seventh aspect, the same effect as that of the sixth aspect can be obtained.

According to the ESD protection structure for a semiconductor integrated circuit according to the eighth aspect, in addition to the same effect as the seventh aspect, it is necessary to reduce the trigger voltage of the SCR as the thickness of the gate oxide film becomes thinner. However, the design can be performed without considering the gate oxide film destruction of the ESD protection circuit to which the surge voltage applied from the input / output pad is applied first. This allows
When a surge is applied, the gate oxide film of the ESD protection circuit which is most likely to be damaged in the integrated circuit is not damaged, and a highly reliable ESD protection circuit can be manufactured.

According to the ESD protection structure for a semiconductor integrated circuit of the ninth aspect, the same effect as that of the first aspect can be obtained.

The ESD of a semiconductor integrated circuit according to claim 10
According to the protection structure, the same effect as the ninth aspect is obtained.

The ESD of a semiconductor integrated circuit according to claim 11
According to the protection structure, the same effect as that of the tenth aspect is obtained.

The ESD of the semiconductor integrated circuit according to claim 12
According to the protection structure, since the vertical parasitic bipolar transistor operates in the vertical direction, the same effect as that of the first aspect is obtained.

The ESD of a semiconductor integrated circuit according to claim 13.
According to the protection structure, the same effect as the twelfth aspect is obtained.

The ESD of the semiconductor integrated circuit according to claim 14
According to the protection structure, the same effects as those of the thirteenth aspect are obtained.

The ESD of the semiconductor integrated circuit according to claim 15
According to the protection structure, in addition to the same effects as those of the fourteenth aspect, the seventh diffusion region enhances the current driving capability, so that the ESD is improved.
The protection circuit can be designed with a small area. The ESD protection circuit is usually connected to the input / output pads, and as a result, is arranged in a band around the integrated circuit chip. Therefore, if the area occupied by the ESD protection circuit is reduced, the area of the integrated circuit chip is reduced. Of course, the number of integrated circuit chips that can be obtained from one wafer increases, which leads to cost reduction.

[Brief description of the drawings]

FIG. 1 shows an ESD of a semiconductor integrated circuit having a parasitic PNP bipolar transistor according to a first embodiment of the present invention.
It is a schematic sectional drawing explaining a protection structure.

FIG. 2 shows a vertical parasitic PN according to a second embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view illustrating an ESD protection structure including a P bipolar transistor.

FIG. 3 shows a vertical parasitic PN according to a third embodiment of the present invention.
E with P bipolar transistor and low resistance parasitic resistance
It is a schematic sectional drawing explaining an SD protection structure.

FIG. 4 is a schematic sectional view illustrating an ESD protection structure having a structure for preventing a gate oxide film from being damaged from a surge voltage according to the present invention.

FIG. 5 is a view showing a result of producing a conventional ESD protection structure by an STI process and measuring IV characteristics;
(A) is a schematic sectional view showing a bias condition, and (b) is a graph in which a current with respect to each measured voltage is plotted.

FIG. 6 is a schematic cross-sectional view illustrating a conventional ESD protection structure.

FIG. 7 is a schematic diagram of an ESD protection circuit.

[Explanation of symbols]

Reference Signs List 1 P-type silicon substrate 2 P-type well region 3 N-type well region 4 P ⁻ -type diffusion region 5 P ⁺ -type diffusion region 6 N ⁺ -type diffusion region 7 N ⁺ -type diffusion region 8 P ⁺ -type diffusion region 9 Isolation 10 Gate 11 Sidewall 12 Parasitic NPN bipolar transistor 13 Parasitic PNP bipolar transistor 14 P-type well region 15 N ^- type diffusion region 16 Parasitic NPN bipolar transistor 17 Vertical parasitic PNP bipolar transistor 18 P-type diffusion region 19 Parasitic NPN bipolar transistor 20 Vertical parasitic PNP bipolar transistor 21 N ⁺ -type diffusion region and the P-type boundary 23 parasitic boundary 22 N ⁺ -type diffusion region of the well region and the P-type well region NPN bipolar transistor 24 the parasitic PNP bipolar transistor 25 SCR protection device 26 PMOSFET 27 NMOSFE Iio characteristics when the potential difference between Iio characteristics 103 Vio and Vd when the Iio characteristics 102 Vd when took 101 Vio horizontal axis taken on the horizontal axis taken on the horizontal axis

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 29/74 F term (Reference) 5F005 AH01 CA02 5F038 AV06 BH06 BH13 EZ20 5F048 AA02 AC03 BA01 BC03 BE02 BE03 BE05 BG14 CC08 CC10 CC13 CC15 CC16 CC18 CC19 DA25 5F082 AA33 BA47 BC01 BC09 EA03 EA09 FA16

Claims (15)

[Claims] An ESD protection structure for a semiconductor integrated circuit for protecting a circuit to which an operating voltage is applied, comprising: a substrate; first and second well regions formed adjacent to the substrate; A first diffusion region formed in the first well region; a third diffusion region formed over the first well region and the second well region; A fourth diffusion region formed in the second well region; a fifth diffusion region formed in the fourth diffusion region; and a fourth diffusion region formed between the second diffusion region and the third diffusion region. A gate formed so as to cover the first well region, wherein the gate, the second diffusion region and the third diffusion region constitute a MOS transistor, and wherein the first well region and the second 2 well region and the fourth diffusion region ESD protection structure of a semiconductor integrated circuit, characterized in that it constitutes a parasitic bipolar transistor I. 2. The ESD protection structure for a semiconductor integrated circuit according to claim 1, wherein the substrate is a P-type silicon substrate. 3. The ES of a semiconductor integrated circuit according to claim 2, wherein the first well region is P-type and the second well region is N-type.
D protection structure. 4. The semiconductor according to claim 3, wherein the first diffusion region, the fourth diffusion region, and the fifth diffusion region are P-type, and the second diffusion region and the third diffusion region are N-type. ESD protection structure for integrated circuits. 5. The ESD protection structure according to claim 1, wherein the third diffusion region and the fifth diffusion region are separated by STI. 6. The ESD protection structure for a semiconductor integrated circuit according to claim 5, wherein the depth of the fourth diffusion region is larger than STI. 7. The ES of a semiconductor integrated circuit according to claim 6, wherein the gate of the MOS transistor has a sidewall.
D protection structure. 8. The ESD protection structure for a semiconductor integrated circuit according to claim 7, wherein a boundary on the surface of the silicon substrate between the third diffusion region and the first well region is located below the sidewall. 9. The ESD protection structure for a semiconductor integrated circuit according to claim 1, wherein the substrate is a silicon substrate and is N-type. 10. The semiconductor integrated circuit according to claim 9, wherein the first well region is N-type and the second well region is P-type.
SD protection structure. 11. The semiconductor integrated circuit according to claim 10, wherein the first diffusion region, the fourth diffusion region and the fifth diffusion region are N-type, and the second diffusion region and the third diffusion region are P-type. ESD protection structure. 12. An ESD protection structure for a semiconductor integrated circuit for protecting a circuit to which an operating voltage is applied, comprising: a substrate; a third well region formed on the substrate; and the third well region. A first diffusion region formed in the third well region, a sixth diffusion region formed in the third well region, and a structure extending over the third well region and the sixth diffusion region. A third diffusion region, a fifth diffusion region formed in the sixth diffusion region, and the third well region between the second diffusion region and the third diffusion region. A MOS transistor is formed by the gate, the second diffusion region, and the third diffusion region, and the third well region, the sixth diffusion region, and the Vertical parasitic bi-poor due to fifth diffusion region ESD of the semiconductor integrated circuit characterized in that it constitutes a la transistor
Protection structure. 13. The ESD protection structure for a semiconductor integrated circuit according to claim 12, wherein a third diffusion region and said fifth diffusion region are separated by STI. 14. The ESD protection structure according to claim 13, wherein the depth of the sixth diffusion region is deeper than the STI. 15. The ESD of a semiconductor integrated circuit according to claim 14, further comprising a seventh diffusion region of the same conductivity type as said third well region in a third well region below said sixth diffusion region.
Protection structure.