WO2012063378A1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
WO2012063378A1
WO2012063378A1 PCT/JP2011/002683 JP2011002683W WO2012063378A1 WO 2012063378 A1 WO2012063378 A1 WO 2012063378A1 JP 2011002683 W JP2011002683 W JP 2011002683W WO 2012063378 A1 WO2012063378 A1 WO 2012063378A1
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Prior art keywords
input
output
output terminal
type well
semiconductor integrated
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PCT/JP2011/002683
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French (fr)
Japanese (ja)
Inventor
荒井勝也
甲上歳浩
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パナソニック株式会社
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Publication of WO2012063378A1 publication Critical patent/WO2012063378A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7436—Lateral thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0817—Thyristors only

Definitions

  • the present disclosure relates to a semiconductor integrated circuit, in particular, a semiconductor integrated circuit including an electrostatic discharge (ESD) protection element.
  • ESD electrostatic discharge
  • the resistance to surge of the semiconductor integrated circuit is the breakdown voltage of the weakest combination when a surge is applied between all terminals. Therefore, when it is difficult to predict the surge discharge path of the semiconductor integrated circuit, it is necessary to apply a surge to all terminal combinations of the semiconductor integrated circuit and test the resistance to the surge.
  • This test method is generally called a pin-to-pin test or a pin combination test (hereinafter referred to as “pin combination test”).
  • the distance between adjacent terminals is reduced due to process miniaturization or narrow pad (PAD) pitch (multiple pins). For this reason, the tolerance with respect to the surge of the parasitic element which exists between adjacent terminals is falling. As a result, the resistance to surge of the semiconductor integrated circuit tends to be determined by the resistance to surge between adjacent terminals.
  • PAD narrow pad
  • the conventional semiconductor integrated circuit includes an input / output cell 100 and an input / output cell 101, and a power line 110 and a ground line 111 are arranged so as to straddle the input / output cells 100 and 101. ing.
  • the input / output cell 100 includes an input / output terminal 102, an NMOS transistor 103, a PMOS transistor 104, and an input / output circuit 105.
  • the input / output cell 101 includes an input / output terminal 106, an NMOS transistor 107, a PMOS transistor 108, and an input / output circuit 109.
  • sources 122 and 124 made of a P + diffusion layer and a drain 123 made of a P + diffusion layer constituting the PMOS transistor 104 are provided in an N-type well 150 provided on a semiconductor substrate (not shown). Is provided. Further, the gate 131 constituting the PMOS transistor 104 is provided on the N-type well 150 so that the source 122 and the drain 123 are located on the lower side, and the PMOS transistor so that the drain 123 and the source 124 are located on the lower side. 104 is provided on the N-type well 150.
  • sources 127 and 129 made of a P + diffusion layer and a drain 128 made of a P + diffusion layer constituting the PMOS transistor 108 are provided. Further, the gate 133 constituting the PMOS transistor 108 is provided on the N-type well 150 so that the source 127 and the drain 128 are located on the lower side, and the PMOS transistor so that the drain 128 and the source 129 are located on the lower side. A gate 134 constituting 108 is provided on the N-type well 150.
  • substrate contacts 121, 125, 126 and 130 made of N + diffusion layers are provided in the N-type well 150, and the power supply line 110 includes substrate contacts 121, 125, 126 and 130, gates 131 to 134, Also connected to the drains 122, 124, 127 and 129.
  • the drain 123 is connected to the input / output terminal 102, and the drain 128 is connected to the input / output circuit 105.
  • the parasitic element PNP bipolar is connected between the input / output terminal 102 and the input / output circuit 105 and the base is connected to the power supply line 110 as equivalently shown in the N-type well 150 in FIG. Transistor 112 is present.
  • sources 136 and 138 made of an N + diffusion layer constituting the NMOS transistor 103 and a drain made of a P + diffusion layer. 137 is provided in a P-type well 151 provided on a semiconductor substrate (not shown). Further, the gate 145 constituting the NMOS transistor 103 is provided on the N-type well 151 so that the source 136 and the drain 137 are located on the lower side, and the NMOS transistor is arranged so that the drain 137 and the source 138 are located on the lower side. 103 is provided on the P-type well 151.
  • sources 141 and 143 made of an N + diffusion layer and a drain 142 made of an N + diffusion layer constituting the NMOS transistor 107 are provided in a P-type well 151 provided on a semiconductor substrate (not shown). Further, the gate 147 constituting the NMOS transistor 107 is provided on the P-type well 151 so that the source 141 and the drain 142 are located on the lower side, and the NMOS transistor is arranged such that the drain 142 and the drain 143 are located on the lower side. A gate 148 constituting 107 is provided on the P-type well 151.
  • substrate contacts 135, 139, 140 and 144 made of P + diffusion layers are provided in the P-type well 151.
  • the power supply line 111 includes substrate contacts 135, 139, 140 and 144, gates 145 to 148, And connected to drains 136, 138, 141 and 144.
  • the drain 137 is connected to the input / output terminal 102, and the drain 142 is connected to the input / output circuit 105.
  • a parasitic element NPN bipolar device connected between the input / output terminal 102 and the input / output circuit 105 and having the base connected to the ground line 111 as equivalently shown in the P-type well 151 in FIG. A transistor 113 is present.
  • the parasitic element exists between adjacent input / output cells, which may cause the following problems. That is, when the input / output terminal 102 of one input / output cell 100 is grounded and a surge is applied to the input / output terminal 106 of the other input / output cell 101, a parasitic element (parasitic) existing between adjacent input / output cells is detected. Since a surge current flows through the element PNP transistor 112 and the parasitic element NPN transistor 113), these parasitic elements may be destroyed.
  • an object of the present invention is to provide a semiconductor integrated circuit having a configuration excellent in surge resistance without increasing the area of an ESD protection element of an input / output cell.
  • a semiconductor integrated circuit includes a power source line and a ground line, a first input / output terminal, and a drain connected to the first input / output terminal.
  • a first NMOS transistor connected to the ground line, a drain connected to the first input / output terminal, a source and gate connected to the power supply line, a first PMOS transistor, and a first input / output terminal;
  • a first input / output cell having a first input / output circuit connected to the drain of the first NMOS transistor and the drain of the first PMOS transistor; a second input / output terminal;
  • a second NMOS transistor connected to a terminal, a source and a gate connected to a ground line, and a drain connected to a second input / output terminal;
  • a second PMOS transistor having a source and a gate connected to the power supply line, and a second input / output terminal connected to the second input / output terminal, the drain of the second NMOS transistor, and the drain of the second
  • a second input / output cell having a circuit wherein the first PMOS transistor in the first input / output cell and the second NMOS transistor in the second input / output cell are arranged adjacent to each other,
  • the first input / output cell and the second input / output cell are arranged so that the first NMOS transistor in the first input / output cell and the second PMOS transistor in the second input / output cell are adjacent to each other.
  • Input / output cells are arranged adjacent to each other.
  • the anode is connected to the first input / output terminal and the cathode is the second input / output between the first input / output cell and the second input / output cell.
  • a first thyristor connected to the terminal is configured, and a second thyristor is configured with the cathode connected to the first input / output terminal and the anode connected to the second input / output terminal. It is preferable.
  • a semiconductor integrated circuit includes a power line and a ground line, a first input / output terminal, a cathode connected to the first input / output terminal, and an anode connected to the ground line.
  • the input / output cell, the second input / output terminal, the cathode is connected to the second input / output terminal, and the anode is connected to the ground line.
  • Second P-type diffusion layer-N-type well diode connected to input / output terminal and cathode connected to power supply line, and second input / output terminal, second N-type diffusion layer-P-type well
  • a second input / output cell having a second input / output circuit connected to the cathode of the diode and the anode of the second P-type diffusion layer-N-type well diode.
  • 1 P-type diffusion layer-N-type well diode and the second N-type diffusion layer-P-type well diode in the second input / output cell are arranged adjacent to each other, and in the first input / output cell
  • the first input / output is so arranged that the first N-type diffusion layer-P-type well diode and the second P-type diffusion layer-N-type well diode in the second input / output cell are arranged adjacent to each other.
  • the cell and the second input / output cell It is located adjacent to.
  • the anode is connected to the first input / output terminal and the cathode is the second input / output between the first input / output cell and the second input / output cell.
  • a first thyristor connected to the terminal is configured, and a second thyristor is configured with the cathode connected to the first input / output terminal and the anode connected to the second input / output terminal. It is preferable.
  • the semiconductor integrated circuit according to the embodiment of the present invention has a configuration in which a thyristor exists between adjacent first and second input / output cells, the semiconductor integrated circuit is excellent against surge without increasing the area of the ESD protection element. Tolerance is realized.
  • FIG. 1 is a plan view showing the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. Specifically, it shows a cross-sectional configuration along the line II-II in FIG. 1 and is an equivalent thyristor. , A connection relationship with a power line, a ground line, and an input / output terminal is schematically shown.
  • FIG. 3 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. Specifically, the cross-sectional configuration along the line III-III in FIG. , A connection relationship with a power line, a ground line, and an input / output terminal is schematically shown.
  • FIG. 4 is a plan view showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. Specifically, the cross-sectional configuration of the VV line in FIG. The connection relation with a line, a ground line, and an input / output terminal is shown typically.
  • FIG. 6 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. Specifically, it shows the cross-sectional configuration of the VI-VI line of FIG. 4 and is an equivalent thyristor. , A connection relationship with a power line, a ground line, and an input / output terminal is schematically shown.
  • FIG. 5 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. Specifically, the cross-sectional configuration of the VV line in FIG. The connection relation with a line, a ground line, and an input
  • FIG. 7 is a plan view showing a configuration of a conventional semiconductor integrated circuit.
  • FIG. 8 is a cross-sectional view showing a configuration of a conventional semiconductor integrated circuit. Specifically, it shows a cross-sectional configuration of line VIII-VIII in FIG. 7, and an equivalent transistor, power supply line, input / output terminal, And a connection relationship with the input / output circuit.
  • FIG. 9 is a cross-sectional view showing the configuration of a conventional semiconductor integrated circuit. Specifically, the cross-sectional configuration of the IX-IX line in FIG. 7 is shown, and an equivalent transistor, ground line, input / output terminal, And a connection relationship with the input / output circuit.
  • a semiconductor integrated circuit includes an input / output cell 1 and an input / output cell 2 arranged adjacent to each other so as to straddle the input / output cells 1 and 2.
  • the power supply line 11 and the ground line 12 are arranged.
  • the input / output cell 1 includes an input / output terminal 3, an NMOS transistor 4, a PMOS transistor 5, and an input / output circuit 6.
  • the input / output cell 2 includes an input / output terminal 7, an NMOS transistor 8, a PMOS transistor 9, and an input / output circuit 10.
  • sources 22 and 24 made of a P + diffusion layer and a drain 23 made of a P + diffusion layer constituting the PMOS transistor 5 are provided. Is provided. Further, the gate 31 constituting the PMOS transistor 5 is provided on the N-type well 63 so that the source 22 and the drain 23 are located on the lower side, and the PMOS transistor so that the drain 23 and the source 24 are located on the lower side. 5 is provided on the N-type well 63. Further, substrate contacts 21 and 25 made of N + diffusion layers are provided in the N-type well 63, and the power supply line 11 is connected to the substrate contacts 21 and 25, gates 31 and 32, and sources 22 and 24. ing. The drain 23 is connected to the input / output terminal 3. As described above, the PMOS transistor 5 having the gates 31 and 32 connected to the power supply line 11, the sources 22 and 24 connected to the power supply line 11, and the drain 23 connected to the input / output terminal 3 is provided.
  • a P-type well 64 provided on a semiconductor substrate (not shown) and adjacent to the N-type well 63, sources 27 and 29 made of an N + diffusion layer and a drain 28 made of an N + diffusion layer constituting the NMOS transistor 9 are provided. It has been. Further, the gate 33 constituting the NMOS transistor 9 is provided on the P-type well 64 so that the source 27 and the drain 28 are located below the side, and the NMOS transistor 9 is located so that the drain 28 and the source 29 are located below the side. 9 is provided on the P-type well 64.
  • substrate contacts 26 and 30 made of a P + diffusion layer are provided in the P-type well 64, and the ground line 12 is connected to the substrate contacts 26 and 30, gates 33 and 34, and sources 27 and 29. ing.
  • the drain 28 is connected to the input / output terminal 7.
  • the NMOS transistor 9 having the gates 33 and 34 connected to the ground line 12, the sources 27 and 29 connected to the ground line 12, and the drain 28 connected to the input / output terminal 7 is provided.
  • the input / output cell 1 and the input / output cell 1 are arranged so that the PMOS transistor 5 in the input / output cell 1 and the NMOS transistor 9 in the input / output cell 2 are arranged adjacent to each other.
  • the cells 2 are arranged adjacent to each other.
  • the anode is connected between the input / output cells 1 and 2 as equivalently shown in FIG. 3 and a thyristor (also referred to as a silicon controlled rectifier (SCR)) 13 having a cathode connected to the input / output terminal 7 is present.
  • a thyristor also referred to as a silicon controlled rectifier (SCR)
  • sources 36 and 38 made of N + diffusion layers constituting the NMOS transistor 4 and a drain made of N + diffusion layers. 37 is provided.
  • the gate 45 constituting the NMOS transistor 4 is provided on the P-type well 65 so that the source 36 and the drain 37 are located below the side, and the NMOS transistor 4 is located such that the drain 37 and the source 38 are located below the side. 4 is provided on the P-type well 65.
  • substrate contacts 35 and 39 made of a P + diffusion layer are provided in the P-type well 65, and the ground line 12 is connected to the substrate contacts 35 and 39, the gates 45 and 46, and the sources 36 and 38. ing.
  • the drain 37 is connected to the input / output terminal 3.
  • the NMOS transistor 4 having the gates 45 and 46 connected to the ground line 12, the sources 36 and 38 connected to the ground line 12, and the drain 37 connected to the input / output terminal 3 is provided.
  • an N-type well 66 provided on a semiconductor substrate (not shown) and adjacent to the P-type well 65, sources 41 and 43 made of a P + diffusion layer and a drain 42 made of a P + diffusion layer constituting the PMOS transistor 8 are provided. It has been. Further, the gate 47 constituting the PMOS transistor 8 is provided on the N-type well 66 so that the source 41 and the drain 42 are located on the lower side, and the PMOS transistor so that the drain 42 and the source 43 are located on the lower side. 8 is provided on the N-type well 66.
  • substrate contacts 40 and 44 made of N + diffusion layers are provided in the N-type well 66, and the power supply line 11 is connected to the substrate contacts 40 and 44, gates 47 and 48, and sources 41 and 43. ing.
  • the drain 42 is connected to the input / output terminal 7.
  • the PMOS transistor 8 is provided in which the gates 47 and 48 are connected to the power supply line 11, the sources 41 and 43 are connected to the power supply line 11, and the drain 42 is connected to the input / output terminal 7.
  • the input / output cell 1 and the input / output cell 1 are arranged so that the NMOS transistor 4 in the input / output cell 1 and the PMOS transistor 8 in the input / output cell 2 are arranged adjacent to each other.
  • the cells 2 are arranged adjacent to each other.
  • the cathode is connected between the input / output cells 1 and 2 as equivalently shown in FIG. 3 and a thyristor 14 having an anode connected to the input / output terminal 7 is present.
  • the input / output circuit 6 is connected to the input / output terminal 3, the drain 37 of the NMOS transistor 4, and the drain 23 of the PMOS transistor 5.
  • the input / output circuit 10 is connected to the input / output terminal 7, the drain 42 of the PMOS transistor 8, and the drain 28 of the NMOS transistor 9.
  • HBM human body model
  • MM machine model
  • the junction between the P-type well 65 and the N-type well 66 breaks down, and the thyristors 13 and 14 are in a positive feedback state. Thus, a latch-up operation is induced.
  • the discharge capability against surge of the thyristors 13 and 14 existing between the adjacent input / output cells 1 and 2 in the semiconductor integrated circuit according to the present embodiment is the same as that of the adjacent input / output cell in the semiconductor integrated circuit according to the related art.
  • the parasitic element bipolar transistors 112 and 113 existing between 100 and 101 are about 5 to 10 times higher.
  • the semiconductor integrated circuit according to the present embodiment it is possible to improve the resistance against the surge between the adjacent input / output cells 1 and 2 without increasing the area of the ESD protection circuit. Therefore, in recent semiconductor integrated circuit process miniaturization (such as shallow junction of diffusion layer) or narrow pad pitch (protection element area reduction), the adjacent input / output cells in the conventional semiconductor integrated circuit described above Compared with the parasitic element bipolar transistors 112 and 113 existing in the semiconductor integrated circuit, the semiconductor integrated circuit according to the present embodiment is very useful.
  • a semiconductor integrated circuit includes an input / output cell 1a and an input / output cell 2a arranged adjacent to each other, and straddles the input / output cells 1a and 2a.
  • the power supply line 11 and the ground line 12 are arranged.
  • the input / output cell 1a includes an input / output terminal 3, an N type diffusion layer-P type well diode 51 (hereinafter referred to as "N + PW diode 51”), a P type diffusion layer-N type well diode 52 (hereinafter referred to as “P + NW diode 52"). And an input / output circuit 6.
  • the input / output cell 2 includes an input / output terminal 7, a P-type diffusion layer-N-type well diode 53 (hereinafter referred to as "P + NW diode 53”), an N-type diffusion layer-P-type well diode 54 (hereinafter referred to as "N + PW diode”). 54 ”) and the input / output circuit 10.
  • a cathode 55 made of an N + diffusion layer and an anode 56 made of a P + diffusion layer constituting the P + NW diode 52 are provided in an N-type well 63 provided on a semiconductor substrate (not shown). ing. Further, substrate contacts 21 and 25 made of N + diffusion layers are provided in the N-type well 63, and the power supply line 11 is connected to the substrate contacts 21 and 25 and the cathode 55. The anode 56 is connected to the input / output terminal 3. As described above, the P + NW diode 52 having the cathode 55 connected to the power supply line 11 and the anode 56 connected to the input / output terminal 3 is provided.
  • a cathode 57 made of an N + diffusion layer and an anode 58 made of a P + diffusion layer constituting an N + PW diode 54 are provided in a P-type well 64 provided on a semiconductor substrate (not shown) and adjacent to the N-type well 63. Yes. Further, substrate contacts 26 and 30 made of P + diffusion layers are provided in the P-type well 64, and the ground line 12 is connected to the substrate contacts 26 and 30 and the anode 58. The cathode 57 is connected to the input / output terminal 7.
  • the N + PW diode 54 having the anode 58 connected to the ground line 12 and the cathode 57 connected to the input / output terminal 7 is provided.
  • the input / output cell 1a and the input / output cell 1a are arranged so that the P + NW diode 52 in the input / output cell 1a and the N + PW diode 54 in the input / output cell 2a are arranged adjacent to each other.
  • the cells 2a are arranged adjacent to each other.
  • the cathode is connected between the input / output cells 1a and 2a as equivalently shown in FIG. 3 and a thyristor 13a having an anode connected to the input / output terminal 7 is present.
  • an anode 59 composed of a P + diffusion layer and a cathode 60 composed of an N + diffusion layer constituting the N + PW diode 51 are provided. Is provided. Further, substrate contacts 35 and 39 made of P + diffusion layers are provided in the P-type well 65, and the ground line 12 is connected to the substrate contacts 35 and 39 and the anode 59. The cathode 60 is connected to the input / output terminal 3. Thus, the N + PW diode 51 having the anode 59 connected to the ground line 12 and the cathode 60 connected to the input / output terminal 3 is provided.
  • an anode 61 made of a P + diffusion layer and a cathode 62 made of an N + diffusion layer constituting the P + NW diode 53 are provided in an N type well 66 adjacent to the P type well 65 provided on a semiconductor substrate (not shown). Yes. Further, substrate contacts 40 and 44 made of an N + diffusion layer are provided in the N-type well 66, and the power supply line 11 is connected to the substrate contacts 40 and 44 and the cathode 62. The anode 61 is connected to the input / output terminal 7. As described above, the P + NW diode 53 having the cathode 62 connected to the power supply line 11 and the anode 61 connected to the input / output terminal 7 is provided.
  • the input / output cell 1a and the input / output cell 1a are arranged so that the N + PW diode 51 in the input / output cell 1a and the P + NW diode 53 in the input / output cell 2a are arranged adjacent to each other.
  • the cells 2a are arranged adjacent to each other.
  • the cathode is connected between the input / output cells 1a and 2a as equivalently shown in FIG. 3 and a thyristor 14a having an anode connected to the input / output terminal 7 is present.
  • the input / output circuit 6 is connected to the input / output terminal 3, the anode 56 of the P + NW diode 52, and the cathode 60 of the N + PW diode 51.
  • the input / output circuit 10 is connected to the input / output terminal 7, the anode 61 of the P + NW diode 53, and the cathode 57 of the N + PW diode 54.
  • the junction between the P-type well 65 and the N-type well 66 breaks down, and the thyristors 13a and 14a are in a positive feedback state.
  • a latch-up operation is induced.
  • the discharge capability against the surge of the thyristors 13a and 14a existing between the adjacent input / output cells 1a and 2a in the semiconductor integrated circuit according to the present embodiment is equal to the adjacent input / output cell in the semiconductor integrated circuit according to the related art.
  • the parasitic element bipolar transistors 112 and 113 existing between 100 and 101 are about 5 to 10 times higher.
  • the configuration of the semiconductor integrated circuit according to the present embodiment it is possible to improve the resistance against a surge between the adjacent input / output cells 1a and 2a without increasing the area of the ESD protection circuit. Therefore, in recent semiconductor integrated circuit process miniaturization (such as shallow junction of diffusion layer) or narrow pad pitch (protection element area reduction), the adjacent input / output cells in the conventional semiconductor integrated circuit described above
  • the semiconductor integrated circuit according to the present embodiment is very useful as compared with the parasitic element bipolar transistors 112 and 113 existing in FIG.
  • the diode type protection circuit is used in the input / output cell 1a and the input / output cell 2a, the input / output terminal 3 and the input / output terminal 3 and 7 capacity can be reduced. Therefore, the input / output cell 1a and the input / output cell 2a in this embodiment can be used as an input / output cell for a high-speed interface such as a high-resolution multimedia interface (HDMI) or a universal serial bus (USB). is there.
  • HDMI high-resolution multimedia interface
  • USB universal serial bus
  • the semiconductor integrated circuit according to various embodiments of the present invention can realize a semiconductor integrated circuit excellent in surge resistance without increasing the area of the ESD protection circuit. Therefore, it is particularly useful for a semiconductor integrated circuit provided with an ESD protection circuit.

Abstract

Provided is a semiconductor integrated circuit which has achieved excellent resistance against surge without increasing the area of an ESD protection circuit. The semiconductor integrated circuit has a configuration wherein a thyristor (13), in which an anode is connected to an input/output terminal (3) and a cathode is connected to an input/output terminal (7), and a thyristor (14), in which a cathode is connected to the input/output terminal (3) and an anode is connected to the input/output terminal (7), are arranged between an input/output cell (1) and an input/output cell (2) that are disposed adjacent to each other.

Description

半導体集積回路Semiconductor integrated circuit
　本開示は、半導体集積回路、特に、静電放電（ＥＳＤ）保護素子を備えた半導体集積回路に関する。 The present disclosure relates to a semiconductor integrated circuit, in particular, a semiconductor integrated circuit including an electrostatic discharge (ESD) protection element.
　近年、半導体集積回路は、素子の微細化及び高密度化と並行して高集積化が進んでいることにより、静電放電（以下、「サージ」という）によってもたらされるダメージに対して弱くなっている。例えば、外部接続用パッド（外部パッド）から侵入するサージにより、入力回路、出力回路、入出力回路及び内部回路などの素子が破壊され、素子の性能が低下する可能性が高くなっている。このため、半導体集積回路には、外部接続用パッドと、入力回路、出力回路、入出力回路又は内部回路との間に、サージから保護するための静電放電保護素子が設けられている（例えば特許文献１を参照）。 In recent years, semiconductor integrated circuits have become weak against damage caused by electrostatic discharge (hereinafter referred to as “surge”) due to progress in high integration in parallel with miniaturization and high density of elements. Yes. For example, a surge entering from an external connection pad (external pad) destroys elements such as an input circuit, an output circuit, an input / output circuit, and an internal circuit, and there is a high possibility that the performance of the element is deteriorated. For this reason, the semiconductor integrated circuit is provided with an electrostatic discharge protection element for protecting from a surge between the external connection pad and the input circuit, output circuit, input / output circuit or internal circuit (for example, (See Patent Document 1).
　また、半導体集積回路のサージに対する耐性は、全ての端子間にサージを印加した場合の最も弱い組合せの破壊電圧である。従って、半導体集積回路のサージ放電経路が予測し難い場合、半導体集積回路の全ての端子の組合せに対してサージを印加し、サージに対する耐性を試験する必要がある。この試験方法は、一般的に、Pin-to-Pin試験又はピン・コンビネーション試験と呼ばれている（以下、「ピン・コンビネーション試験」という）。 Also, the resistance to surge of the semiconductor integrated circuit is the breakdown voltage of the weakest combination when a surge is applied between all terminals. Therefore, when it is difficult to predict the surge discharge path of the semiconductor integrated circuit, it is necessary to apply a surge to all terminal combinations of the semiconductor integrated circuit and test the resistance to the surge. This test method is generally called a pin-to-pin test or a pin combination test (hereinafter referred to as “pin combination test”).
　ピン・コンビネーション試験では、非電源端子を接地基準としてその他の端子にサージを印加し、さらに、接地基準端子を順次変えながらサージ試験を実施する。このようにして、半導体集積回路の端子間に存在する寄生素子を介したサージ放電経路のサージに対する耐性を試験している。 In the pin combination test, surge is applied to the other terminals with the non-power supply terminal as the ground reference, and the ground reference terminal is changed sequentially. In this way, the resistance to surge of the surge discharge path through the parasitic element existing between the terminals of the semiconductor integrated circuit is tested.
　さらに、近年の半導体集積回路では、プロセスの微細化又は狭パッド（ＰＡＤ）ピッチ化（多ピン化）により、隣接する端子間の距離が縮小している。このため、隣接する端子間に存在する寄生素子のサージに対する耐性が低下している。その結果、半導体集積回路のサージに対する耐性は、この隣接する端子間のサージに対する耐性で決定される傾向にある。 Furthermore, in recent semiconductor integrated circuits, the distance between adjacent terminals is reduced due to process miniaturization or narrow pad (PAD) pitch (multiple pins). For this reason, the tolerance with respect to the surge of the parasitic element which exists between adjacent terminals is falling. As a result, the resistance to surge of the semiconductor integrated circuit tends to be determined by the resistance to surge between adjacent terminals.
　以下に、図７～図９を参照しながら、従来の半導体集積回路について説明する。 Hereinafter, a conventional semiconductor integrated circuit will be described with reference to FIGS.
　図７に示すように、従来の半導体集積回路は、入出力セル１００と入出力セル１０１とを含んでおり、入出力セル１００及び１０１を跨ぐようにして電源ライン１１０及びグランドライン１１１が配置されている。入出力セル１００は、入出力端子１０２、ＮＭＯＳトランジスタ１０３、ＰＭＯＳトランジスタ１０４及び入出力回路１０５によって構成されている。また、入出力セル１０１は、入出力端子１０６、ＮＭＯＳトランジスタ１０７、ＰＭＯＳトランジスタ１０８及び入出力回路１０９によって構成されている。 As shown in FIG. 7, the conventional semiconductor integrated circuit includes an input / output cell 100 and an input / output cell 101, and a power line 110 and a ground line 111 are arranged so as to straddle the input / output cells 100 and 101. ing. The input / output cell 100 includes an input / output terminal 102, an NMOS transistor 103, a PMOS transistor 104, and an input / output circuit 105. The input / output cell 101 includes an input / output terminal 106, an NMOS transistor 107, a PMOS transistor 108, and an input / output circuit 109.
　図７及び図８に示すように、図示しない半導体基板に設けられたＮ型ウェル１５０内には、ＰＭＯＳトランジスタ１０４を構成するＰ＋拡散層からなるソース１２２及び１２４とＰ＋拡散層からなるドレイン１２３が設けられている。また、側方下にソース１２２及びドレイン１２３が位置するようにＰＭＯＳトランジスタ１０４を構成するゲート１３１がＮ型ウェル１５０上に設けられ、側方下にドレイン１２３及びソース１２４が位置するようにＰＭＯＳトランジスタ１０４を構成するゲート１３２がＮ型ウェル１５０上に設けられている。 As shown in FIGS. 7 and 8, in an N-type well 150 provided on a semiconductor substrate (not shown), sources 122 and 124 made of a P + diffusion layer and a drain 123 made of a P + diffusion layer constituting the PMOS transistor 104 are provided. Is provided. Further, the gate 131 constituting the PMOS transistor 104 is provided on the N-type well 150 so that the source 122 and the drain 123 are located on the lower side, and the PMOS transistor so that the drain 123 and the source 124 are located on the lower side. 104 is provided on the N-type well 150.
　同様に、図示しない半導体基板に設けられたＮ型ウェル１５０内には、ＰＭＯＳトランジスタ１０８を構成するＰ＋拡散層からなるソース１２７及び１２９とＰ＋拡散層からなるドレイン１２８が設けられている。また、側方下にソース１２７及びドレイン１２８が位置するようにＰＭＯＳトランジスタ１０８を構成するゲート１３３がＮ型ウェル１５０上に設けられ、側方下にドレイン１２８及びソース１２９が位置するようにＰＭＯＳトランジスタ１０８を構成するゲート１３４がＮ型ウェル１５０上に設けられている。 Similarly, in an N-type well 150 provided on a semiconductor substrate (not shown), sources 127 and 129 made of a P + diffusion layer and a drain 128 made of a P + diffusion layer constituting the PMOS transistor 108 are provided. Further, the gate 133 constituting the PMOS transistor 108 is provided on the N-type well 150 so that the source 127 and the drain 128 are located on the lower side, and the PMOS transistor so that the drain 128 and the source 129 are located on the lower side. A gate 134 constituting 108 is provided on the N-type well 150.
　さらに、Ｎ型ウェル１５０内には、Ｎ＋拡散層からなる基板コンタクト１２１、１２５、１２６及び１３０が設けられており、電源ライン１１０は、基板コンタクト１２１、１２５、１２６及び１３０、ゲート１３１～１３４、並びにドレイン１２２、１２４、１２７及び１２９に接続されている。また、ドレイン１２３は入出力端子１０２に接続されており、ドレイン１２８は入出力回路１０５に接続されている。 Further, substrate contacts 121, 125, 126 and 130 made of N + diffusion layers are provided in the N-type well 150, and the power supply line 110 includes substrate contacts 121, 125, 126 and 130, gates 131 to 134, Also connected to the drains 122, 124, 127 and 129. The drain 123 is connected to the input / output terminal 102, and the drain 128 is connected to the input / output circuit 105.
　以上の構成により、図８におけるＮ型ウェル１５０内に等価的に示すように、入出力端子１０２と入出力回路１０５との間に接続され、ベースが電源ライン１１０に接続された寄生素子ＰＮＰバイポーラトランジスタ１１２が存在している。 With the above configuration, the parasitic element PNP bipolar is connected between the input / output terminal 102 and the input / output circuit 105 and the base is connected to the power supply line 110 as equivalently shown in the N-type well 150 in FIG. Transistor 112 is present.
　また、図７及び図９に示すように、図示しない半導体基板に設けられたＰ型ウェル１５１内には、ＮＭＯＳトランジスタ１０３を構成するＮ＋拡散層からなるソース１３６及び１３８とＰ＋拡散層からなるドレイン１３７が設けられている。また、側方下にソース１３６及びドレイン１３７が位置するようにＮＭＯＳトランジスタ１０３を構成するゲート１４５がＮ型ウェル１５１上に設けられ、側方下にドレイン１３７及びソース１３８が位置するようにＮＭＯＳトランジスタ１０３を構成するゲート１４６がＰ型ウェル１５１上に設けられている。 Further, as shown in FIGS. 7 and 9, in a P-type well 151 provided on a semiconductor substrate (not shown), sources 136 and 138 made of an N + diffusion layer constituting the NMOS transistor 103 and a drain made of a P + diffusion layer. 137 is provided. Further, the gate 145 constituting the NMOS transistor 103 is provided on the N-type well 151 so that the source 136 and the drain 137 are located on the lower side, and the NMOS transistor is arranged so that the drain 137 and the source 138 are located on the lower side. 103 is provided on the P-type well 151.
　同様に、図示しない半導体基板に設けられたＰ型ウェル１５１内には、ＮＭＯＳトランジスタ１０７を構成するＮ＋拡散層からなるソース１４１及び１４３とＮ＋拡散層からなるドレイン１４２が設けられている。また、側方下にソース１４１及びドレイン１４２が位置するようにＮＭＯＳトランジスタ１０７を構成するゲート１４７がＰ型ウェル１５１上に設けられ、側方下にドレイン１４２及びドレイン１４３が位置するようにＮＭＯＳトランジスタ１０７を構成するゲート１４８がＰ型ウェル１５１上に設けられている。 Similarly, in a P-type well 151 provided on a semiconductor substrate (not shown), sources 141 and 143 made of an N + diffusion layer and a drain 142 made of an N + diffusion layer constituting the NMOS transistor 107 are provided. Further, the gate 147 constituting the NMOS transistor 107 is provided on the P-type well 151 so that the source 141 and the drain 142 are located on the lower side, and the NMOS transistor is arranged such that the drain 142 and the drain 143 are located on the lower side. A gate 148 constituting 107 is provided on the P-type well 151.
　さらに、Ｐ型ウェル１５１内には、Ｐ＋拡散層からなる基板コンタクト１３５、１３９、１４０及び１４４が設けられており、電源ライン１１１は、基板コンタクト１３５、１３９、１４０及び１４４、ゲート１４５～１４８、並びにドレイン１３６、１３８、１４１及び１４４に接続されている。また、ドレイン１３７は入出力端子１０２に接続されており、ドレイン１４２は入出力回路１０５に接続されている。 Further, substrate contacts 135, 139, 140 and 144 made of P + diffusion layers are provided in the P-type well 151. The power supply line 111 includes substrate contacts 135, 139, 140 and 144, gates 145 to 148, And connected to drains 136, 138, 141 and 144. The drain 137 is connected to the input / output terminal 102, and the drain 142 is connected to the input / output circuit 105.
　以上の構成により、図９におけるＰ型ウェル１５１内に等価的に示すように、入出力端子１０２と入出力回路１０５との間に接続され、ベースがグランドライン１１１に接続された寄生素子ＮＰＮバイポーラトランジスタ１１３が存在している。 With the above configuration, a parasitic element NPN bipolar device connected between the input / output terminal 102 and the input / output circuit 105 and having the base connected to the ground line 111 as equivalently shown in the P-type well 151 in FIG. A transistor 113 is present.
特開２００７－１９４１３号公報JP 2007-19413 A
　しかしながら、上記従来の半導体集積回路においては、隣接する入出力セル間に寄生素子が存在しているために、以下の問題を生じる可能性がある。すなわち、一方の入出力セル１００の入出力端子１０２を接地して他方の入出力セル１０１の入出力端子１０６にサージを印加した場合、隣接する入出力セル間に存在している寄生素子（寄生素子ＰＮＰトランジスタ１１２及び寄生素子ＮＰＮトランジスタ１１３）を介してサージ電流が流れるため、これらの寄生素子が破壊されるおそれがある。 However, in the above-described conventional semiconductor integrated circuit, the parasitic element exists between adjacent input / output cells, which may cause the following problems. That is, when the input / output terminal 102 of one input / output cell 100 is grounded and a surge is applied to the input / output terminal 106 of the other input / output cell 101, a parasitic element (parasitic) existing between adjacent input / output cells is detected. Since a surge current flows through the element PNP transistor 112 and the parasitic element NPN transistor 113), these parasitic elements may be destroyed.
　また、近年、半導体集積回路は、プロセスの微細化（拡散層の浅接合化など）又は狭ＰＡＤピッチ化（保護素子の小面積化）により、寄生素子のサージに対する耐性が弱くなっている。その結果、半導体集積回路のサージに対する耐性が低くなってきている。このような問題に対して、入出力セル間の距離を広げて寄生素子のＯＮ電圧とＯＮ抵抗とを上昇させること、又は入出力セル内の保護素子のサイズを大きくして寄生素子のサイズを増大させることなどの対策も考えられるが、入出力セルの面積の増大、ひいては半導体集積回路の面積の増大を招いてしまう。 In recent years, semiconductor integrated circuits have become less resistant to parasitic element surges due to process miniaturization (such as shallow junction of diffusion layers) or narrow PAD pitch (protection element area reduction). As a result, the semiconductor integrated circuit is less resistant to surges. To solve this problem, increase the ON voltage and ON resistance of the parasitic element by increasing the distance between the input / output cells, or increase the size of the protection element in the input / output cell to increase the size of the parasitic element. Although measures such as an increase can be considered, an increase in the area of the input / output cells and an increase in the area of the semiconductor integrated circuit will be caused.
　前記に鑑み、本発明の目的は、入出力セルのＥＳＤ保護素子の面積を増大させることなく、サージに対する耐性に優れた構成を有する半導体集積回路を提供することである。 In view of the above, an object of the present invention is to provide a semiconductor integrated circuit having a configuration excellent in surge resistance without increasing the area of an ESD protection element of an input / output cell.
　上記の課題を解決するために、本発明のある実施形態による半導体集積回路は、電源ライン及びグランドラインと、第１の入出力端子、ドレインが第１の入出力端子に接続され、ソース及びゲートがグランドラインに接続された第１のＮＭＯＳトランジスタ、ドレインが第１の入出力端子に接続され、ソース及びゲートが電源ラインに接続された第１のＰＭＯＳトランジスタ、並びに、第１の入出力端子、第１のＮＭＯＳトランジスタのドレイン、及び第１のＰＭＯＳトランジスタのドレインに接続された第１の入出力回路を有する第１の入出力セルと、第２の入出力端子、ドレインが第２の入出力端子に接続され、ソース及びゲートがグランドラインに接続された第２のＮＭＯＳトランジスタ、ドレインが第２の入出力端子に接続され、ソース及びゲートが電源ラインに接続された第２のＰＭＯＳトランジスタ、並びに、第２の入出力端子、第２のＮＭＯＳトランジスタのドレイン及び第２のＰＭＯＳトランジスタのドレインに接続された第２の入出力回路を有する第２の入出力セルとを備えており、第１の入出力セルにおける第１のＰＭＯＳトランジスタと、第２の入出力セルにおける第２のＮＭＯＳトランジスタとが互いに隣接して配置され、且つ、第１の入出力セルにおける第１のＮＭＯＳトランジスタと、第２の入出力セルにおける第２のＰＭＯＳトランジスタとが互いに隣接して配置されるように、第１の入出力セルと第２の入出力セルとが互いに隣接して配置されている。 In order to solve the above-described problems, a semiconductor integrated circuit according to an embodiment of the present invention includes a power source line and a ground line, a first input / output terminal, and a drain connected to the first input / output terminal. A first NMOS transistor connected to the ground line, a drain connected to the first input / output terminal, a source and gate connected to the power supply line, a first PMOS transistor, and a first input / output terminal; A first input / output cell having a first input / output circuit connected to the drain of the first NMOS transistor and the drain of the first PMOS transistor; a second input / output terminal; A second NMOS transistor connected to a terminal, a source and a gate connected to a ground line, and a drain connected to a second input / output terminal; A second PMOS transistor having a source and a gate connected to the power supply line, and a second input / output terminal connected to the second input / output terminal, the drain of the second NMOS transistor, and the drain of the second PMOS transistor. A second input / output cell having a circuit, wherein the first PMOS transistor in the first input / output cell and the second NMOS transistor in the second input / output cell are arranged adjacent to each other, In addition, the first input / output cell and the second input / output cell are arranged so that the first NMOS transistor in the first input / output cell and the second PMOS transistor in the second input / output cell are adjacent to each other. Input / output cells are arranged adjacent to each other.
　本発明の上記実施形態による半導体集積回路において、第１の入出力セルと第２の入出力セルとの間には、アノードが第１の入出力端子に接続され、カソードが第２の入出力端子に接続された第１のサイリスタが構成されており、且つ、カソードが第１の入出力端子に接続され、アノードが第２の入出力端子に接続された第２のサイリスタが構成されていることが好ましい。 In the semiconductor integrated circuit according to the embodiment of the present invention, the anode is connected to the first input / output terminal and the cathode is the second input / output between the first input / output cell and the second input / output cell. A first thyristor connected to the terminal is configured, and a second thyristor is configured with the cathode connected to the first input / output terminal and the anode connected to the second input / output terminal. It is preferable.
　本発明の他の実施形態による半導体集積回路は、電源ライン及びグランドラインと、第１の入出力端子、カソードが第１の入出力端子に接続され、且つ、アノードがグランドラインに接続された第１のＮ型拡散層－Ｐ型ウェルダイオード、アノードが第１の入出力端子に接続され、且つ、カソードが電源ラインに接続された第１のＰ型拡散層－Ｎ型ウェルダイオード、並びに、第１の入出力端子、第１のＮ型拡散層－Ｐ型ウェルダイオードのカソード及び第１のＰ型拡散層－Ｎ型ウェルダイオードのアノードに接続された第１の入出力回路を有する第１の入出力セルと、第２の入出力端子、カソードが第２の入出力端子に接続され、且つ、アノードがグランドラインに接続された第２のＮ型拡散層－Ｐ型ウェルダイオード、アノードが第２の入出力端子に接続され、且つ、カソードが電源ラインに接続された第２のＰ型拡散層－Ｎ型ウェルダイオード、並びに、第２の入出力端子、第２のＮ型拡散層－Ｐ型ウェルダイオードのカソード及び第２のＰ型拡散層－Ｎ型ウェルダイオードのアノードに接続された第２の入出力回路を有する第２の入出力セルとを備えており、第１の入出力セルにおける第１のＰ型拡散層－Ｎ型ウェルダイオードと、第２の入出力セルにおける第２のＮ型拡散層－Ｐ型ウェルダイオードとが互いに隣接して配置され、且つ、第１の入出力セルにおける第１のＮ型拡散層－Ｐ型ウェルダイオードと、第２の入出力セルにおける第２のＰ型拡散層－Ｎ型ウェルダイオードとが互いに隣接して配置されるように、第１の入出力セル及び第２の入出力セルとが互いに隣接して配置されている。 A semiconductor integrated circuit according to another embodiment of the present invention includes a power line and a ground line, a first input / output terminal, a cathode connected to the first input / output terminal, and an anode connected to the ground line. 1 N-type diffusion layer-P-type well diode, first P-type diffusion layer-N-type well diode having an anode connected to the first input / output terminal and a cathode connected to the power supply line, A first N-type diffusion layer—a first input / output circuit connected to the cathode of the P-type well diode and the first P-type diffusion layer—the anode of the N-type well diode; The input / output cell, the second input / output terminal, the cathode is connected to the second input / output terminal, and the anode is connected to the ground line. 2 Second P-type diffusion layer-N-type well diode connected to input / output terminal and cathode connected to power supply line, and second input / output terminal, second N-type diffusion layer-P-type well And a second input / output cell having a second input / output circuit connected to the cathode of the diode and the anode of the second P-type diffusion layer-N-type well diode. 1 P-type diffusion layer-N-type well diode and the second N-type diffusion layer-P-type well diode in the second input / output cell are arranged adjacent to each other, and in the first input / output cell The first input / output is so arranged that the first N-type diffusion layer-P-type well diode and the second P-type diffusion layer-N-type well diode in the second input / output cell are arranged adjacent to each other. The cell and the second input / output cell It is located adjacent to.
　本発明の上記実施形態による半導体集積回路において、第１の入出力セルと第２の入出力セルとの間には、アノードが第１の入出力端子に接続され、カソードが第２の入出力端子に接続された第１のサイリスタが構成されており、且つ、カソードが第１の入出力端子に接続され、アノードが第２の入出力端子に接続された第２のサイリスタが構成されていることが好ましい。 In the semiconductor integrated circuit according to the embodiment of the present invention, the anode is connected to the first input / output terminal and the cathode is the second input / output between the first input / output cell and the second input / output cell. A first thyristor connected to the terminal is configured, and a second thyristor is configured with the cathode connected to the first input / output terminal and the anode connected to the second input / output terminal. It is preferable.
　本発明の実施形態による半導体集積回路は、隣接する第１及び第２の入出力セル間に、サイリスタが存在する構成を有するため、ＥＳＤ保護素子の面積を増大させることなく、サージに対して優れた耐性が実現される。 Since the semiconductor integrated circuit according to the embodiment of the present invention has a configuration in which a thyristor exists between adjacent first and second input / output cells, the semiconductor integrated circuit is excellent against surge without increasing the area of the ESD protection element. Tolerance is realized.
図１は、本発明の第１の実施形態に係る半導体集積回路の構成を示す平面図である。FIG. 1 is a plan view showing the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. 図２は、本発明の第１の実施形態に係る半導体集積回路の構成を示す断面図であって、具体的には、図１のII-II線の断面構成を示す共に、等価的なサイリスタ、電源ライン、グランドライン、及び入出力端子との接続関係を模式的に示している。FIG. 2 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. Specifically, it shows a cross-sectional configuration along the line II-II in FIG. 1 and is an equivalent thyristor. , A connection relationship with a power line, a ground line, and an input / output terminal is schematically shown. 図３は、本発明の第１の実施形態に係る半導体集積回路の構成を示す断面図であって、具体的には、図１のIII-III線の断面構成を示す共に、等価的なサイリスタ、電源ライン、グランドライン、及び入出力端子との接続関係を模式的に示している。FIG. 3 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. Specifically, the cross-sectional configuration along the line III-III in FIG. , A connection relationship with a power line, a ground line, and an input / output terminal is schematically shown. 図４は、本発明の第２の実施形態に係る半導体集積回路の構成を示す平面図である。FIG. 4 is a plan view showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. 図５は、本発明の第２の実施形態に係る半導体集積回路の構成を示す断面図であって、具体的には、図４のV-V線の断面構成を示す共に、等価的なサイリスタ、電源ライン、グランドライン、及び入出力端子との接続関係を模式的に示している。FIG. 5 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. Specifically, the cross-sectional configuration of the VV line in FIG. The connection relation with a line, a ground line, and an input / output terminal is shown typically. 図６は、本発明の第２の実施形態に係る半導体集積回路の構成を示す断面図であって、具体的には、図４のVI-VI線の断面構成を示す共に、等価的なサイリスタ、電源ライン、グランドライン、及び入出力端子との接続関係を模式的に示している。FIG. 6 is a cross-sectional view showing the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. Specifically, it shows the cross-sectional configuration of the VI-VI line of FIG. 4 and is an equivalent thyristor. , A connection relationship with a power line, a ground line, and an input / output terminal is schematically shown. 図７は、従来の半導体集積回路の構成を示す平面図である。FIG. 7 is a plan view showing a configuration of a conventional semiconductor integrated circuit. 図８は、従来の半導体集積回路の構成を示す断面図であって、具体的には、図７のVIII-VIII線の断面構成を示す共に、等価的なトランジスタ、電源ライン、入出力端子、及び入出力回路との接続関係を模式的に示している。FIG. 8 is a cross-sectional view showing a configuration of a conventional semiconductor integrated circuit. Specifically, it shows a cross-sectional configuration of line VIII-VIII in FIG. 7, and an equivalent transistor, power supply line, input / output terminal, And a connection relationship with the input / output circuit. 図９は、従来の半導体集積回路の構成を示す断面図であって、具体的には、図７のIX-IX線の断面構成を示す共に、等価的なトランジスタ、グランドライン、入出力端子、及び入出力回路との接続関係を模式的に示している。FIG. 9 is a cross-sectional view showing the configuration of a conventional semiconductor integrated circuit. Specifically, the cross-sectional configuration of the IX-IX line in FIG. 7 is shown, and an equivalent transistor, ground line, input / output terminal, And a connection relationship with the input / output circuit.
　図面を参照して本発明のさまざまな実施形態が以下に説明される。同じ参照符号は、同じまたは同様の構成要素を表す。 Various embodiments of the present invention are described below with reference to the drawings. The same reference signs represent the same or similar components.
　図１に示すように、本発明のある実施形態に係る半導体集積回路は、互いに隣接して配置された入出力セル１及び入出力セル２を含んでおり、入出力セル１及び２を跨ぐようにして電源ライン１１及びグランドライン１２が配置されている。 As shown in FIG. 1, a semiconductor integrated circuit according to an embodiment of the present invention includes an input / output cell 1 and an input / output cell 2 arranged adjacent to each other so as to straddle the input / output cells 1 and 2. Thus, the power supply line 11 and the ground line 12 are arranged.
　入出力セル１は、入出力端子３、ＮＭＯＳトランジスタ４、ＰＭＯＳトランジスタ５及び入出力回路６によって構成されている。また、入出力セル２は、入出力端子７、ＮＭＯＳトランジスタ８、ＰＭＯＳトランジスタ９及び入出力回路１０によって構成されている。 The input / output cell 1 includes an input / output terminal 3, an NMOS transistor 4, a PMOS transistor 5, and an input / output circuit 6. The input / output cell 2 includes an input / output terminal 7, an NMOS transistor 8, a PMOS transistor 9, and an input / output circuit 10.
　図１及び図２に示すように、図示しない半導体基板に設けられたＮ型ウェル６３内には、ＰＭＯＳトランジスタ５を構成するＰ＋拡散層からなるソース２２及び２４とＰ＋拡散層からなるドレイン２３が設けられている。また、側方下にソース２２及びドレイン２３が位置するようにＰＭＯＳトランジスタ５を構成するゲート３１がＮ型ウェル６３上に設けられ、側方下にドレイン２３及びソース２４が位置するようにＰＭＯＳトランジスタ５を構成するゲート３２がＮ型ウェル６３上に設けられている。さらに、Ｎ型ウェル６３内には、Ｎ＋拡散層からなる基板コンタクト２１及び２５が設けられており、電源ライン１１は、基板コンタクト２１及び２５、ゲート３１及び３２、並びにソース２２及び２４に接続されている。また、ドレイン２３は入出力端子３に接続されている。このように、ゲート３１、３２が電源ライン１１に接続され、ソース２２及び２４が電源ライン１１に接続され、ドレイン２３が入出力端子３に接続されたＰＭＯＳトランジスタ５が設けられている。 As shown in FIGS. 1 and 2, in an N-type well 63 provided on a semiconductor substrate (not shown), sources 22 and 24 made of a P + diffusion layer and a drain 23 made of a P + diffusion layer constituting the PMOS transistor 5 are provided. Is provided. Further, the gate 31 constituting the PMOS transistor 5 is provided on the N-type well 63 so that the source 22 and the drain 23 are located on the lower side, and the PMOS transistor so that the drain 23 and the source 24 are located on the lower side. 5 is provided on the N-type well 63. Further, substrate contacts 21 and 25 made of N + diffusion layers are provided in the N-type well 63, and the power supply line 11 is connected to the substrate contacts 21 and 25, gates 31 and 32, and sources 22 and 24. ing. The drain 23 is connected to the input / output terminal 3. As described above, the PMOS transistor 5 having the gates 31 and 32 connected to the power supply line 11, the sources 22 and 24 connected to the power supply line 11, and the drain 23 connected to the input / output terminal 3 is provided.
　一方、図示しない半導体基板に設けられ、Ｎ型ウェル６３に隣接するＰ型ウェル６４内には、ＮＭＯＳトランジスタ９を構成するＮ＋拡散層からなるソース２７及び２９とＮ＋拡散層からなるドレイン２８が設けられている。また、側方下にソース２７及びドレイン２８が位置するようにＮＭＯＳトランジスタ９を構成するゲート３３がＰ型ウェル６４上に設けられ、側方下にドレイン２８及びソース２９が位置するようにＮＭＯＳトランジスタ９を構成するゲート３４がＰ型ウェル６４上に設けられている。さらに、Ｐ型ウェル６４内には、Ｐ＋拡散層からなる基板コンタクト２６及び３０が設けられており、グランドライン１２は、基板コンタクト２６及び３０、ゲート３３及び３４、並びにソース２７及び２９に接続されている。また、ドレイン２８は入出力端子７に接続されている。このように、ゲート３３、３４がグランドライン１２に接続され、ソース２７及び２９がグランドライン１２に接続され、ドレイン２８が入出力端子７に接続されたＮＭＯＳトランジスタ９が設けられている。 On the other hand, in a P-type well 64 provided on a semiconductor substrate (not shown) and adjacent to the N-type well 63, sources 27 and 29 made of an N + diffusion layer and a drain 28 made of an N + diffusion layer constituting the NMOS transistor 9 are provided. It has been. Further, the gate 33 constituting the NMOS transistor 9 is provided on the P-type well 64 so that the source 27 and the drain 28 are located below the side, and the NMOS transistor 9 is located so that the drain 28 and the source 29 are located below the side. 9 is provided on the P-type well 64. Further, substrate contacts 26 and 30 made of a P + diffusion layer are provided in the P-type well 64, and the ground line 12 is connected to the substrate contacts 26 and 30, gates 33 and 34, and sources 27 and 29. ing. The drain 28 is connected to the input / output terminal 7. As described above, the NMOS transistor 9 having the gates 33 and 34 connected to the ground line 12, the sources 27 and 29 connected to the ground line 12, and the drain 28 connected to the input / output terminal 7 is provided.
　また、図１及び図２に示すように、入出力セル１内のＰＭＯＳトランジスタ５と入出力セル２内のＮＭＯＳトランジスタ９とが互いに隣接して配置されるように、入出力セル１と入出力セル２とは互いに隣接して配置されている。 As shown in FIGS. 1 and 2, the input / output cell 1 and the input / output cell 1 are arranged so that the PMOS transistor 5 in the input / output cell 1 and the NMOS transistor 9 in the input / output cell 2 are arranged adjacent to each other. The cells 2 are arranged adjacent to each other.
　以上説明した構成を有するＰＭＯＳトランジスタ５及びＮＭＯＳトランジスタ９により、本実施形態に係る半導体集積回路では、図２において等価的に示すように、入出力セル１及び２間には、アノードが入出力端子３に接続され、カソードが入出力端子７に接続されたサイリスタ（シリコン制御整流器（ＳＣＲ）ともいう）１３が存在している。 With the PMOS transistor 5 and the NMOS transistor 9 having the above-described configuration, in the semiconductor integrated circuit according to this embodiment, the anode is connected between the input / output cells 1 and 2 as equivalently shown in FIG. 3 and a thyristor (also referred to as a silicon controlled rectifier (SCR)) 13 having a cathode connected to the input / output terminal 7 is present.
　また、図１及び図３に示すように、図示しない半導体基板に設けられたＰ型ウェル６５内には、ＮＭＯＳトランジスタ４を構成するＮ＋拡散層からなるソース３６及び３８とＮ＋拡散層からなるドレイン３７が設けられている。また、側方下にソース３６及びドレイン３７が位置するようにＮＭＯＳトランジスタ４を構成するゲート４５がＰ型ウェル６５上に設けられ、側方下にドレイン３７及びソース３８が位置するようにＮＭＯＳトランジスタ４を構成するゲート４６がＰ型ウェル６５上に設けられている。さらに、Ｐ型ウェル６５内には、Ｐ＋拡散層からなる基板コンタクト３５及び３９が設けられており、グランドライン１２は、基板コンタクト３５及び３９、ゲート４５及び４６、並びにソース３６及び３８に接続されている。また、ドレイン３７は入出力端子３に接続されている。このように、ゲート４５、４６がグランドライン１２に接続され、ソース３６及び３８がグランドライン１２に接続され、ドレイン３７が入出力端子３に接続されたＮＭＯＳトランジスタ４が設けられている。 As shown in FIGS. 1 and 3, in a P-type well 65 provided on a semiconductor substrate (not shown), sources 36 and 38 made of N + diffusion layers constituting the NMOS transistor 4 and a drain made of N + diffusion layers. 37 is provided. Further, the gate 45 constituting the NMOS transistor 4 is provided on the P-type well 65 so that the source 36 and the drain 37 are located below the side, and the NMOS transistor 4 is located such that the drain 37 and the source 38 are located below the side. 4 is provided on the P-type well 65. Further, substrate contacts 35 and 39 made of a P + diffusion layer are provided in the P-type well 65, and the ground line 12 is connected to the substrate contacts 35 and 39, the gates 45 and 46, and the sources 36 and 38. ing. The drain 37 is connected to the input / output terminal 3. As described above, the NMOS transistor 4 having the gates 45 and 46 connected to the ground line 12, the sources 36 and 38 connected to the ground line 12, and the drain 37 connected to the input / output terminal 3 is provided.
　一方、図示しない半導体基板に設けられ、Ｐ型ウェル６５に隣接するＮ型ウェル６６内には、ＰＭＯＳトランジスタ８を構成するＰ＋拡散層からなるソース４１及び４３とＰ＋拡散層からなるドレイン４２が設けられている。また、側方下にソース４１及びドレイン４２が位置するようにＰＭＯＳトランジスタ８を構成するゲート４７がＮ型ウェル６６上に設けられ、側方下にドレイン４２及びソース４３が位置するようにＰＭＯＳトランジスタ８を構成するゲート４８がＮ型ウェル６６上に設けられている。さらに、Ｎ型ウェル６６内には、Ｎ＋拡散層からなる基板コンタクト４０及び４４が設けられており、電源ライン１１は、基板コンタクト４０及び４４、ゲート４７及び４８、並びにソース４１及び４３に接続されている。また、ドレイン４２は入出力端子７に接続されている。このように、ゲート４７、４８が電源ライン１１に接続され、ソース４１及び４３が電源ライン１１に接続され、ドレイン４２が入出力端子７に接続されたＰＭＯＳトランジスタ８が設けられている。 On the other hand, in an N-type well 66 provided on a semiconductor substrate (not shown) and adjacent to the P-type well 65, sources 41 and 43 made of a P + diffusion layer and a drain 42 made of a P + diffusion layer constituting the PMOS transistor 8 are provided. It has been. Further, the gate 47 constituting the PMOS transistor 8 is provided on the N-type well 66 so that the source 41 and the drain 42 are located on the lower side, and the PMOS transistor so that the drain 42 and the source 43 are located on the lower side. 8 is provided on the N-type well 66. Further, substrate contacts 40 and 44 made of N + diffusion layers are provided in the N-type well 66, and the power supply line 11 is connected to the substrate contacts 40 and 44, gates 47 and 48, and sources 41 and 43. ing. The drain 42 is connected to the input / output terminal 7. As described above, the PMOS transistor 8 is provided in which the gates 47 and 48 are connected to the power supply line 11, the sources 41 and 43 are connected to the power supply line 11, and the drain 42 is connected to the input / output terminal 7.
　また、図１及び図３に示すように、入出力セル１内のＮＭＯＳトランジスタ４と入出力セル２内のＰＭＯＳトランジスタ８とが互いに隣接して配置されるように、入出力セル１と入出力セル２とは互いに隣接して配置されている。 Further, as shown in FIGS. 1 and 3, the input / output cell 1 and the input / output cell 1 are arranged so that the NMOS transistor 4 in the input / output cell 1 and the PMOS transistor 8 in the input / output cell 2 are arranged adjacent to each other. The cells 2 are arranged adjacent to each other.
　以上説明した構成を有するＮＭＯＳトランジスタ４及びＰＭＯＳトランジスタ８により、本実施形態に係る半導体集積回路では、図３において等価的に示すように、入出力セル１及び２間には、カソードが入出力端子３に接続され、アノードが入出力端子７に接続されたサイリスタ１４が存在している。 With the NMOS transistor 4 and the PMOS transistor 8 having the above-described configuration, in the semiconductor integrated circuit according to the present embodiment, the cathode is connected between the input / output cells 1 and 2 as equivalently shown in FIG. 3 and a thyristor 14 having an anode connected to the input / output terminal 7 is present.
　なお、入出力回路６は、入出力端子３、ＮＭＯＳトランジスタ４のドレイン３７、及びＰＭＯＳトランジスタ５のドレイン２３に接続されている。一方、入出力回路１０は、入出力端子７、ＰＭＯＳトランジスタ８のドレイン４２、及びＮＭＯＳトランジスタ９のドレイン２８に接続されている。 The input / output circuit 6 is connected to the input / output terminal 3, the drain 37 of the NMOS transistor 4, and the drain 23 of the PMOS transistor 5. On the other hand, the input / output circuit 10 is connected to the input / output terminal 7, the drain 42 of the PMOS transistor 8, and the drain 28 of the NMOS transistor 9.
　次に、本実施形態に係る半導体集積回路の動作について説明する。 Next, the operation of the semiconductor integrated circuit according to this embodiment will be described.
　以下では、半導体集積回路のＥＳＤ評価規格である、ヒューマン・ボディ・モデル（ＨＢＭ）又はマシン・モデル（ＭＭ）などのピン・コンビネーション試験を用いて説明する。 Hereinafter, description will be made using a pin combination test such as a human body model (HBM) or a machine model (MM) which is an ESD evaluation standard of a semiconductor integrated circuit.
　まず、入出力端子７を接地基準として入出力端子３に＋（プラス）サージを加えた場合、ＰＭＯＳトランジスタ５とＮＭＯＳトランジスタ９との間に配置されたサイリスタ１３のアノードからカソードを通じてサージ電流が放電される。さらに、入出力端子７を接地基準として入出力端子３に－（マイナス）サージを加えた場合、ＮＭＯＳトランジスタ４とＰＭＯＳトランジスタ８との間に配置されたサイリスタ１４のアノードからカソードを通じてサージ電流が放電される。 First, when a + (plus) surge is applied to the input / output terminal 3 with the input / output terminal 7 as a ground reference, a surge current is discharged from the anode of the thyristor 13 disposed between the PMOS transistor 5 and the NMOS transistor 9 through the cathode. Is done. Further, when a negative surge is applied to the input / output terminal 3 with the input / output terminal 7 as a ground reference, the surge current is discharged from the anode of the thyristor 14 disposed between the NMOS transistor 4 and the PMOS transistor 8 through the cathode. Is done.
　また、入出力端子３を接地基準として入出力端子７に－サージを加えた場合、ＰＭＯＳトランジスタ５とＮＭＯＳトランジスタ９との間に配置されたサイリスタ１３のアノードからカソードを通じてサージ電流が放電される。さらに、入出力端子３を接地基準として入出力端子７に＋サージを加えた場合、ＮＭＯＳトランジスタ４とＰＭＯＳトランジスタ８との間に配置されたサイリスタ１４のアノードからカソードを通じてサージ電流が放電される。 When a surge is applied to the input / output terminal 7 with the input / output terminal 3 as the ground reference, a surge current is discharged from the anode of the thyristor 13 disposed between the PMOS transistor 5 and the NMOS transistor 9 through the cathode. Further, when + surge is applied to the input / output terminal 7 with the input / output terminal 3 as a ground reference, a surge current is discharged from the anode of the thyristor 14 disposed between the NMOS transistor 4 and the PMOS transistor 8 through the cathode.
　ここで、サイリスタ１３及び１４にサージが印加され、カソードの電圧よりもアノードの電圧が高くなると、Ｐ型ウェル６５とＮ型ウェル６６の接合部がブレークダウンし、サイリスタ１３及び１４が正帰還状態となってラッチアップ動作が誘発される。この際、本実施形態に係る半導体集積回路における隣り合う入出力セル１と２との間に存在するサイリスタ１３及び１４のサージに対する放電能力は、上記従来に係る半導体集積回路における隣り合う入出力セル１００と１０１との間に存在する寄生素子バイポーラトランジスタ１１２及び１１３よりも５倍～１０倍程度高い。したがって、本実施形態に係る半導体集積回路の構成によると、ＥＳＤ保護回路の面積を増大させることなく、隣り合う入出力セル１と２との間のサージに対する耐性を向上させることができる。このため、最近の半導体集積回路のプロセスの微細化（拡散層の浅接合化など）又は狭パッドピッチ化（保護素子の小面積化）において、上記従来の半導体集積回路における隣り合う入出力セル間に存在する寄生素子バイポーラトランジスタ１１２及び１１３に比較して、本実施形態に係る半導体集積回路は大変有用である。 Here, when a surge is applied to the thyristors 13 and 14 and the anode voltage becomes higher than the cathode voltage, the junction between the P-type well 65 and the N-type well 66 breaks down, and the thyristors 13 and 14 are in a positive feedback state. Thus, a latch-up operation is induced. At this time, the discharge capability against surge of the thyristors 13 and 14 existing between the adjacent input / output cells 1 and 2 in the semiconductor integrated circuit according to the present embodiment is the same as that of the adjacent input / output cell in the semiconductor integrated circuit according to the related art. The parasitic element bipolar transistors 112 and 113 existing between 100 and 101 are about 5 to 10 times higher. Therefore, according to the configuration of the semiconductor integrated circuit according to the present embodiment, it is possible to improve the resistance against the surge between the adjacent input / output cells 1 and 2 without increasing the area of the ESD protection circuit. Therefore, in recent semiconductor integrated circuit process miniaturization (such as shallow junction of diffusion layer) or narrow pad pitch (protection element area reduction), the adjacent input / output cells in the conventional semiconductor integrated circuit described above Compared with the parasitic element bipolar transistors 112 and 113 existing in the semiconductor integrated circuit, the semiconductor integrated circuit according to the present embodiment is very useful.
　また、上述した本実施形態では、隣接する入出力セル１及び２間にサージが印加される場合について説明したが、互いに隣り合うことなく離れて配置された入出力セル間にサージが印加される場合であっても、サージが印加される入出力セル間に上述した構成を有する複数の入出力セルが配置されている構造であれば、この複数の入出力セル間に存在するサイリスタを介して、サージ電流を放電することが可能である。 Further, in the above-described embodiment, the case where a surge is applied between the adjacent input / output cells 1 and 2 has been described. However, a surge is applied between input / output cells arranged apart from each other without being adjacent to each other. Even in such a case, if a plurality of input / output cells having the above-described configuration are arranged between input / output cells to which a surge is applied, a thyristor existing between the plurality of input / output cells is used. It is possible to discharge the surge current.
　（変形例）
　図４に示すように、本発明の代替の実施形態に係る半導体集積回路は、互いに隣接して配置された入出力セル１ａ及び入出力セル２ａを含んでおり、入出力セル１ａ及び２ａを跨ぐようにして電源ライン１１及びグランドライン１２が配置されている。 (Modification)
As shown in FIG. 4, a semiconductor integrated circuit according to an alternative embodiment of the present invention includes an input / output cell 1a and an input / output cell 2a arranged adjacent to each other, and straddles the input / output cells 1a and 2a. Thus, the power supply line 11 and the ground line 12 are arranged.
　入出力セル１ａは、入出力端子３、Ｎ型拡散層－Ｐ型ウェルダイオード５１（以下、「Ｎ＋ＰＷダイオード５１」という）、Ｐ型拡散層－Ｎ型ウェルダイオード５２（以下、「Ｐ＋ＮＷダイオード５２」という）及び入出力回路６によって構成されている。また、入出力セル２は、入出力端子７、Ｐ型拡散層－Ｎ型ウェルダイオード５３（以下、「Ｐ＋ＮＷダイオード５３」という）、Ｎ型拡散層－Ｐ型ウェルダイオード５４（以下、「Ｎ＋ＰＷダイオード５４」という）及び入出力回路１０によって構成されている。 The input / output cell 1a includes an input / output terminal 3, an N type diffusion layer-P type well diode 51 (hereinafter referred to as "N + PW diode 51"), a P type diffusion layer-N type well diode 52 (hereinafter referred to as "P + NW diode 52"). And an input / output circuit 6. The input / output cell 2 includes an input / output terminal 7, a P-type diffusion layer-N-type well diode 53 (hereinafter referred to as "P + NW diode 53"), an N-type diffusion layer-P-type well diode 54 (hereinafter referred to as "N + PW diode"). 54 ”) and the input / output circuit 10.
　図４及び図５に示すように、図示しない半導体基板に設けられたＮ型ウェル６３内には、Ｐ＋ＮＷダイオード５２を構成するＮ＋拡散層からなるカソード５５及びＰ＋拡散層からなるアノード５６が設けられている。さらに、Ｎ型ウェル６３内には、Ｎ＋拡散層からなる基板コンタクト２１及び２５が設けられており、電源ライン１１は、基板コンタクト２１及び２５、並びにカソード５５に接続されている。また、アノード５６は入出力端子３に接続されている。このように、カソード５５が電源ライン１１に接続され、アノード５６が入出力端子３に接続されたＰ＋ＮＷダイオード５２が設けられている。 As shown in FIGS. 4 and 5, a cathode 55 made of an N + diffusion layer and an anode 56 made of a P + diffusion layer constituting the P + NW diode 52 are provided in an N-type well 63 provided on a semiconductor substrate (not shown). ing. Further, substrate contacts 21 and 25 made of N + diffusion layers are provided in the N-type well 63, and the power supply line 11 is connected to the substrate contacts 21 and 25 and the cathode 55. The anode 56 is connected to the input / output terminal 3. As described above, the P + NW diode 52 having the cathode 55 connected to the power supply line 11 and the anode 56 connected to the input / output terminal 3 is provided.
　一方、図示しない半導体基板に設けられ、Ｎ型ウェル６３に隣接するＰ型ウェル６４内には、Ｎ＋ＰＷダイオード５４を構成するＮ＋拡散層からなるカソード５７とＰ＋拡散層からなるアノード５８が設けられている。さらに、Ｐ型ウェル６４内には、Ｐ＋拡散層からなる基板コンタクト２６及び３０が設けられており、グランドライン１２は、基板コンタクト２６及び３０、並びにアノード５８に接続されている。また、カソード５７は入出力端子７に接続されている。このように、アノード５８がグランドライン１２に接続され、カソード５７が入出力端子７に接続されたＮ＋ＰＷダイオード５４が設けられている。 On the other hand, a cathode 57 made of an N + diffusion layer and an anode 58 made of a P + diffusion layer constituting an N + PW diode 54 are provided in a P-type well 64 provided on a semiconductor substrate (not shown) and adjacent to the N-type well 63. Yes. Further, substrate contacts 26 and 30 made of P + diffusion layers are provided in the P-type well 64, and the ground line 12 is connected to the substrate contacts 26 and 30 and the anode 58. The cathode 57 is connected to the input / output terminal 7. Thus, the N + PW diode 54 having the anode 58 connected to the ground line 12 and the cathode 57 connected to the input / output terminal 7 is provided.
　また、図４及び図５に示すように、入出力セル１ａ内のＰ＋ＮＷダイオード５２と入出力セル２ａ内のＮ＋ＰＷダイオード５４とが互いに隣接して配置されるように、入出力セル１ａと入出力セル２ａとは互いに隣接して配置されている。 As shown in FIGS. 4 and 5, the input / output cell 1a and the input / output cell 1a are arranged so that the P + NW diode 52 in the input / output cell 1a and the N + PW diode 54 in the input / output cell 2a are arranged adjacent to each other. The cells 2a are arranged adjacent to each other.
　以上説明した構成を有するＰ＋ＮＷダイオード５２及びＮ＋ＰＷダイオード５４により、本実施形態に係る半導体集積回路では、図５において等価的に示すように、入出力セル１ａ及び２ａ間には、カソードが入出力端子３に接続され、アノードが入出力端子７に接続されたサイリスタ１３ａが存在している。 With the P + NW diode 52 and the N + PW diode 54 having the above-described configuration, in the semiconductor integrated circuit according to the present embodiment, the cathode is connected between the input / output cells 1a and 2a as equivalently shown in FIG. 3 and a thyristor 13a having an anode connected to the input / output terminal 7 is present.
　また、図４及び図６に示すように、図示しない半導体基板に設けられたＰ型ウェル６５内には、Ｎ＋ＰＷダイオード５１を構成するＰ＋拡散層からなるアノード５９とＮ＋拡散層からなるカソード６０が設けられている。さらに、Ｐ型ウェル６５内には、Ｐ＋拡散層からなる基板コンタクト３５及び３９が設けられており、グランドライン１２は、基板コンタクト３５及び３９、並びにアノード５９に接続されている。また、カソード６０は入出力端子３に接続されている。このように、アノード５９がグランドライン１２に接続され、カソード６０が入出力端子３に接続されたＮ＋ＰＷダイオード５１が設けられている。 As shown in FIGS. 4 and 6, in a P-type well 65 provided on a semiconductor substrate (not shown), an anode 59 composed of a P + diffusion layer and a cathode 60 composed of an N + diffusion layer constituting the N + PW diode 51 are provided. Is provided. Further, substrate contacts 35 and 39 made of P + diffusion layers are provided in the P-type well 65, and the ground line 12 is connected to the substrate contacts 35 and 39 and the anode 59. The cathode 60 is connected to the input / output terminal 3. Thus, the N + PW diode 51 having the anode 59 connected to the ground line 12 and the cathode 60 connected to the input / output terminal 3 is provided.
　一方、図示しない半導体基板に設けられ、Ｐ型ウェル６５に隣接するＮ型ウェル６６内には、Ｐ＋ＮＷダイオード５３を構成するＰ＋拡散層からなるアノード６１とＮ＋拡散層からなるカソード６２が設けられている。さらに、Ｎ型ウェル６６内には、Ｎ＋拡散層からなる基板コンタクト４０及び４４が設けられており、電源ライン１１は、基板コンタクト４０及び４４、並びにカソード６２に接続されている。また、アノード６１は入出力端子７に接続されている。このように、カソード６２が電源ライン１１に接続され、アノード６１が入出力端子７に接続されたＰ＋ＮＷダイオード５３が設けられている。 On the other hand, an anode 61 made of a P + diffusion layer and a cathode 62 made of an N + diffusion layer constituting the P + NW diode 53 are provided in an N type well 66 adjacent to the P type well 65 provided on a semiconductor substrate (not shown). Yes. Further, substrate contacts 40 and 44 made of an N + diffusion layer are provided in the N-type well 66, and the power supply line 11 is connected to the substrate contacts 40 and 44 and the cathode 62. The anode 61 is connected to the input / output terminal 7. As described above, the P + NW diode 53 having the cathode 62 connected to the power supply line 11 and the anode 61 connected to the input / output terminal 7 is provided.
　また、図４及び図６に示すように、入出力セル１ａ内のＮ＋ＰＷダイオード５１と入出力セル２ａ内のＰ＋ＮＷダイオード５３とが互いに隣接して配置されるように、入出力セル１ａと入出力セル２ａとは互いに隣接して配置されている。 Also, as shown in FIGS. 4 and 6, the input / output cell 1a and the input / output cell 1a are arranged so that the N + PW diode 51 in the input / output cell 1a and the P + NW diode 53 in the input / output cell 2a are arranged adjacent to each other. The cells 2a are arranged adjacent to each other.
　以上説明した構成を有するＮ＋ＰＷダイオード５１及びＰ＋ＮＷダイオード５３により、本実施形態に係る半導体集積回路では、図６において等価的に示すように、入出力セル１ａ及び２ａ間には、カソードが入出力端子３に接続され、アノードが入出力端子７に接続されたサイリスタ１４ａが存在している。 With the N + PW diode 51 and the P + NW diode 53 having the above-described configuration, in the semiconductor integrated circuit according to the present embodiment, the cathode is connected between the input / output cells 1a and 2a as equivalently shown in FIG. 3 and a thyristor 14a having an anode connected to the input / output terminal 7 is present.
　なお、入出力回路６は、入出力端子３、Ｐ＋ＮＷダイオード５２のアノード５６及びＮ＋ＰＷダイオード５１のカソード６０に接続されている。一方、入出力回路１０は、入出力端子７、Ｐ＋ＮＷダイオード５３のアノード６１及びＮ＋ＰＷダイオード５４のカソード５７に接続されている。 The input / output circuit 6 is connected to the input / output terminal 3, the anode 56 of the P + NW diode 52, and the cathode 60 of the N + PW diode 51. On the other hand, the input / output circuit 10 is connected to the input / output terminal 7, the anode 61 of the P + NW diode 53, and the cathode 57 of the N + PW diode 54.
　次に、本実施形態に係る半導体集積回路の動作について説明する。 Next, the operation of the semiconductor integrated circuit according to this embodiment will be described.
　以下では、半導体集積回路のＥＳＤ評価規格である、上記ＨＢＭ又はＭＭなどのピン・コンビネーション試験を用いて説明する。 Hereinafter, description will be made using the above-mentioned pin combination test such as HBM or MM, which is an ESD evaluation standard for semiconductor integrated circuits.
　まず、入出力端子７を接地基準として入出力端子３に＋サージを加えた場合、Ｐ＋ＮＷダイオード５２とＮ＋ＰＷダイオード５４との間に配置されたサイリスタ１３ａのアノードからカソードを通じてサージ電流が放電される。さらに、入出力端子７を接地基準として入出力端子３に－サージを加えた場合、Ｎ＋ＰＷダイオード５１とＰ＋ＮＷダイオード５３との間に配置されたサイリスタ１４ａのアノードからカソードを通じてサージ電流が放電される。 First, when a + surge is applied to the input / output terminal 3 using the input / output terminal 7 as a ground reference, a surge current is discharged from the anode of the thyristor 13a disposed between the P + NW diode 52 and the N + PW diode 54 through the cathode. Further, when −surge is applied to the input / output terminal 3 with the input / output terminal 7 as the ground reference, a surge current is discharged through the cathode from the anode of the thyristor 14 a disposed between the N + PW diode 51 and the P + NW diode 53.
　また、入出力端子３を接地基準として入出力端子７に－サージを加えた場合、Ｐ＋ＮＷダイオード５２とＮ＋ＰＷダイオード５４との間に配置されたサイリスタ１３ａのアノードからカソードを通じてサージ電流が放電される。さらに、入出力端子３を接地基準として入出力端子７に＋サージを加えた場合、Ｎ＋ＰＷダイオード５１とＰ＋ＮＷダイオード５３との間に配置されたサイリスタ１４ａのアノードからカソードを通じてサージ電流が放電される。 When a negative surge is applied to the input / output terminal 7 with the input / output terminal 3 as a ground reference, a surge current is discharged from the anode of the thyristor 13a disposed between the P + NW diode 52 and the N + PW diode 54 through the cathode. Further, when a + surge is applied to the input / output terminal 7 with the input / output terminal 3 as a ground reference, a surge current is discharged through the cathode from the anode of the thyristor 14a disposed between the N + PW diode 51 and the P + NW diode 53.
　ここで、サイリスタ１３ａ及び１４ａにサージが印加され、カソードの電圧よりもアノードの電圧が高くなると、Ｐ型ウェル６５とＮ型ウェル６６の接合部がブレークダウンし、サイリスタ１３ａ及び１４ａが正帰還状態となってラッチアップ動作が誘発される。この際、本実施形態に係る半導体集積回路における隣り合う入出力セル１ａと２ａとの間に存在するサイリスタ１３ａ及び１４ａのサージに対する放電能力は、上記従来に係る半導体集積回路における隣り合う入出力セル１００と１０１との間に存在する寄生素子バイポーラトランジスタ１１２及び１１３よりも５～１０倍程度高い。したがって、本実施形態に係る半導体集積回路の構成によると、ＥＳＤ保護回路の面積を増大させることなく、隣り合う入出力セル１ａと２ａとの間のサージに対する耐性を向上させることができる。このため、最近の半導体集積回路のプロセスの微細化（拡散層の浅接合化など）又は狭パッドピッチ化（保護素子の小面積化）において、上記従来の半導体集積回路における隣り合う入出力セル間に存在する寄生素子バイポーラトランジス１１２及び１１３に比較して、本実施形態に係る半導体集積回路は大変有用である。 Here, when a surge is applied to the thyristors 13a and 14a and the anode voltage becomes higher than the cathode voltage, the junction between the P-type well 65 and the N-type well 66 breaks down, and the thyristors 13a and 14a are in a positive feedback state. Thus, a latch-up operation is induced. At this time, the discharge capability against the surge of the thyristors 13a and 14a existing between the adjacent input / output cells 1a and 2a in the semiconductor integrated circuit according to the present embodiment is equal to the adjacent input / output cell in the semiconductor integrated circuit according to the related art. The parasitic element bipolar transistors 112 and 113 existing between 100 and 101 are about 5 to 10 times higher. Therefore, according to the configuration of the semiconductor integrated circuit according to the present embodiment, it is possible to improve the resistance against a surge between the adjacent input / output cells 1a and 2a without increasing the area of the ESD protection circuit. Therefore, in recent semiconductor integrated circuit process miniaturization (such as shallow junction of diffusion layer) or narrow pad pitch (protection element area reduction), the adjacent input / output cells in the conventional semiconductor integrated circuit described above The semiconductor integrated circuit according to the present embodiment is very useful as compared with the parasitic element bipolar transistors 112 and 113 existing in FIG.
　また、この代替の実施形態では、隣接する入出力セル１ａ及び２ａ間にサージが印加される場合について説明したが、互いに隣り合うことなく離れて配置された入出力セル間にサージが印加される場合であっても、サージが印加される入出力セル間に上述した構成を有する複数の入出力セルが配置されている構造であれば、この複数の入出力セル間に存在するサイリスタを介して、サージ電流を放電することが可能である。 In this alternative embodiment, the case where a surge is applied between adjacent input / output cells 1a and 2a has been described. However, a surge is applied between input / output cells that are spaced apart from each other without being adjacent to each other. Even in such a case, if a plurality of input / output cells having the above-described configuration are arranged between input / output cells to which a surge is applied, a thyristor existing between the plurality of input / output cells is used. It is possible to discharge the surge current.
　さらに、この代替の実施形態では、入出力セル１ａ及び入出力セル２ａ内においてダイオードタイプの保護回路を使用しているため、先に述べた実施形態の場合と比較して、入出力端子３及び７の容量を小さくすることができる。このため、本実施形態における入出力セル１ａ及び入出力セル２ａは、高解像度マルチメディアインターフェース（ＨＤＭＩ）又はユニバーサル・シリアル・バス（ＵＳＢ）などの高速インターフェースの入出力セルとして用いられることが可能である。 Furthermore, in this alternative embodiment, since the diode type protection circuit is used in the input / output cell 1a and the input / output cell 2a, the input / output terminal 3 and the input / output terminal 3 and 7 capacity can be reduced. Therefore, the input / output cell 1a and the input / output cell 2a in this embodiment can be used as an input / output cell for a high-speed interface such as a high-resolution multimedia interface (HDMI) or a universal serial bus (USB). is there.
　本発明の趣旨を逸脱しない範囲で、上述の複数の実施形態における各要素（または行為）を任意に組み合わせてもよい。 In the range which does not deviate from the meaning of this invention, you may combine each element (or action) in the above-mentioned several embodiment arbitrarily.
　上に説明されてきたものには、本発明のさまざまな例が含まれる。本発明を記載する目的では、要素や手順の考えられるあらゆる組み合わせを記載することは当然のことながら不可能であるが、当業者なら本発明の多くのさらなる組み合わせおよび順列が可能であることがわかるだろう。したがって本発明は、特許請求の範囲の精神および範囲に入るそのような改変、変更および変形例を全て含むよう意図される。 What has been described above includes various examples of the present invention. For the purposes of describing the present invention, it is of course impossible to describe every possible combination of elements and procedures, but those skilled in the art will recognize that many further combinations and permutations of the present invention are possible. right. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.
　本発明のさまざまな実施形態による半導体集積回路は、ＥＳＤ保護回路の面積を増大させることなく、サージに対する耐性に優れた半導体集積回路を実現できる。よって特に、ＥＳＤ保護回路を備えた半導体集積回路にとって有用である。 The semiconductor integrated circuit according to various embodiments of the present invention can realize a semiconductor integrated circuit excellent in surge resistance without increasing the area of the ESD protection circuit. Therefore, it is particularly useful for a semiconductor integrated circuit provided with an ESD protection circuit.
１、１ａ、２、２ａ　　　入出力セル
３　　　入出力端子
４　　　ＮＭＯＳトランジスタ
５　　　ＰＭＯＳトランジスタ
６　　　入出力回路
７　　　入出力端子
８　　　ＰＭＯＳトランジスタ
９　　　ＮＭＯＳトランジスタ
１０　　入出力回路
１１　　電源ライン
１２　　グランドライン
１３、１３ａ、１４、１４ａ　　サイリスタ
２１、２５、４０、４４　基板コンタクト
２６、３０、３５、３９　基板コンタクト
２３、４２　ＰＭＯＳトランジスタのドレイン
２８、３７　ＮＭＯＳトランジスタのドレイン
２２、２４、４１、４３　ＰＭＯＳトランジスタのソース
２７、２９、３６、３８　ＮＭＯＳトランジスタのソース
５１　Ｎ＋ＰＷダイオード
５２　Ｐ＋ＮＷダイオード
５３　Ｐ＋ＮＷダイオード
５４　Ｎ＋ＰＷダイオード
５５、６２　Ｐ＋ＮＷダイオードのカソード
５６、６１　Ｐ＋ＮＷダイオードのアノード
５７、６０　Ｎ＋ＰＷダイオードのカソード
５８、５９　Ｎ＋ＰＷダイオードのアノード
６３、６６　Ｎ型ウェル
６４、６５　Ｐ型ウェル 1, 1a, 2, 2a Input / output cell 3 Input / output terminal 4 NMOS transistor 5 PMOS transistor 6 Input / output circuit 7 Input / output terminal 8 PMOS transistor 9 NMOS transistor 10 Input / output circuit 11 Power supply line 12 Ground lines 13, 13a, 14, 14a Thyristors 21, 25, 40, 44 Substrate contacts 26, 30, 35, 39 Substrate contacts 23, 42 PMOS transistor drains 28, 37 NMOS transistor drains 22, 24, 41, 43 PMOS transistor sources 27, 29, 36 , 38 NMOS transistor source 51 N + PW diode 52 P + NW diode 53 P + NW diode 54 N + PW diode 55, 62 P + NW diode cathode 56, 61 P + NW diode The anode of the cathode 58, 59 N + PW diode de anode 57, 60 N + PW diodes 63 and 66 N-type well 64 and 65 P-type well

Claims (4)

  1. 　電源ライン及びグランドラインと、
    　第１の入出力端子、
    　ドレインが前記第１の入出力端子に接続され、ソース及びゲートが前記グランドラインに接続された第１のＮＭＯＳトランジスタ、
    　ドレインが前記第１の入出力端子に接続され、ソース及びゲートが前記電源ラインに接続された第１のＰＭＯＳトランジスタ、並びに、
    　前記第１の入出力端子、前記第１のＮＭＯＳトランジスタのドレイン、及び前記第１のＰＭＯＳトランジスタのドレインに接続された第１の入出力回路
    を有する第１の入出力セルと、
    　第２の入出力端子、
    　ドレインが前記第２の入出力端子に接続され、ソース及びゲートが前記グランドラインに接続された第２のＮＭＯＳトランジスタ、
    　ドレインが前記第２の入出力端子に接続され、ソース及びゲートが前記電源ラインに接続された第２のＰＭＯＳトランジスタ、並びに、
    　前記第２の入出力端子、前記第２のＮＭＯＳトランジスタのドレイン及び前記第２のＰＭＯＳトランジスタのドレインに接続された第２の入出力回路
    を有する第２の入出力セルとを備えており、
    　前記第１の入出力セルにおける前記第１のＰＭＯＳトランジスタと、前記第２の入出力セルにおける前記第２のＮＭＯＳトランジスタとが互いに隣接して配置され、且つ、前記第１の入出力セルにおける前記第１のＮＭＯＳトランジスタと、前記第２の入出力セルにおける前記第２のＰＭＯＳトランジスタとが互いに隣接して配置されるように、前記第１の入出力セルと前記第２の入出力セルとが互いに隣接して配置されている
    半導体集積回路。     A power line and a ground line;
    A first input / output terminal;
    A first NMOS transistor having a drain connected to the first input / output terminal and a source and a gate connected to the ground line;
    A first PMOS transistor having a drain connected to the first input / output terminal and a source and a gate connected to the power supply line; and
    A first input / output cell having a first input / output circuit connected to the first input / output terminal, the drain of the first NMOS transistor, and the drain of the first PMOS transistor;
    A second input / output terminal,
    A second NMOS transistor having a drain connected to the second input / output terminal and a source and a gate connected to the ground line;
    A second PMOS transistor having a drain connected to the second input / output terminal and a source and a gate connected to the power supply line; and
    A second input / output cell having a second input / output circuit connected to the second input / output terminal, the drain of the second NMOS transistor and the drain of the second PMOS transistor;
    The first PMOS transistor in the first input / output cell and the second NMOS transistor in the second input / output cell are arranged adjacent to each other, and the first input / output cell in the first input / output cell The first input / output cell and the second input / output cell are arranged such that the first NMOS transistor and the second PMOS transistor in the second input / output cell are arranged adjacent to each other. Semiconductor integrated circuits arranged adjacent to each other.
  2. 　前記第１の入出力セルと前記第２の入出力セルとの間には、
    　アノードが前記第１の入出力端子に接続され、カソードが前記第２の入出力端子に接続された第１のサイリスタが構成されており、且つ、
    　カソードが前記第１の入出力端子に接続され、アノードが前記第２の入出力端子に接続された第２のサイリスタが構成されている
    請求項１に記載の半導体集積回路。     Between the first input / output cell and the second input / output cell,
    A first thyristor having an anode connected to the first input / output terminal and a cathode connected to the second input / output terminal; and
    2. The semiconductor integrated circuit according to claim 1, wherein a second thyristor having a cathode connected to the first input / output terminal and an anode connected to the second input / output terminal is configured.
  3. 　電源ライン及びグランドラインと、
    　第１の入出力端子、
    　カソードが前記第１の入出力端子に接続され、且つ、アノードが前記グランドラインに接続された第１のＮ型拡散層－Ｐ型ウェルダイオード、
    　アノードが前記第１の入出力端子に接続され、且つ、カソードが前記電源ラインに接続された第１のＰ型拡散層－Ｎ型ウェルダイオード、並びに、
    　前記第１の入出力端子、前記第１のＮ型拡散層－Ｐ型ウェルダイオードのカソード及び前記第１のＰ型拡散層－Ｎ型ウェルダイオードのアノードに接続された第１の入出力回路を有する第１の入出力セルと、
    　第２の入出力端子、
    　カソードが前記第２の入出力端子に接続され、且つ、アノードが前記グランドラインに接続された第２のＮ型拡散層－Ｐ型ウェルダイオード、
    　アノードが前記第２の入出力端子に接続され、且つ、カソードが前記電源ラインに接続された第２のＰ型拡散層－Ｎ型ウェルダイオード、並びに、
    　前記第２の入出力端子、前記第２のＮ型拡散層－Ｐ型ウェルダイオードのカソード及び前記第２のＰ型拡散層－Ｎ型ウェルダイオードのアノードに接続された第２の入出力回路を有する第２の入出力セルとを備えており、
    　前記第１の入出力セルにおける前記第１のＰ型拡散層－Ｎ型ウェルダイオードと、前記第２の入出力セルにおける前記第２のＮ型拡散層－Ｐ型ウェルダイオードとが互いに隣接して配置され、且つ、前記第１の入出力セルにおける前記第１のＮ型拡散層－Ｐ型ウェルダイオードと、前記第２の入出力セルにおける前記第２のＰ型拡散層－Ｎ型ウェルダイオードとが互いに隣接して配置されるように、前記第１の入出力セル及び前記第２の入出力セルとが互いに隣接して配置されている
    半導体集積回路。     A power line and a ground line;
    A first input / output terminal;
    A first N-type diffusion layer-P-type well diode having a cathode connected to the first input / output terminal and an anode connected to the ground line;
    A first P-type diffusion layer-N-type well diode having an anode connected to the first input / output terminal and a cathode connected to the power line; and
    A first input / output circuit connected to the first input / output terminal, the first N-type diffusion layer—the cathode of the P-type well diode, and the first P-type diffusion layer—the anode of the N-type well diode; A first input / output cell having
    A second input / output terminal,
    A second N-type diffusion layer-P-type well diode having a cathode connected to the second input / output terminal and an anode connected to the ground line;
    A second P-type diffusion layer-N-type well diode having an anode connected to the second input / output terminal and a cathode connected to the power line; and
    A second input / output circuit connected to the second input / output terminal, the second N-type diffusion layer—the cathode of the P-type well diode, and the second P-type diffusion layer—the anode of the N-type well diode; A second input / output cell having
    The first P-type diffusion layer-N-type well diode in the first input / output cell and the second N-type diffusion layer-P-type well diode in the second input / output cell are adjacent to each other. The first N-type diffusion layer-P-type well diode in the first input / output cell, and the second P-type diffusion layer-N-type well diode in the second input / output cell, A semiconductor integrated circuit in which the first input / output cell and the second input / output cell are arranged adjacent to each other such that are arranged adjacent to each other.
  4. 　前記第１の入出力セルと前記第２の入出力セルとの間には、
    　アノードが前記第１の入出力端子に接続され、カソードが前記第２の入出力端子に接続された第１のサイリスタが構成されており、且つ、
    　カソードが前記第１の入出力端子に接続され、アノードが前記第２の入出力端子に接続された第２のサイリスタが構成されている
    請求項３に記載の半導体集積回路。     Between the first input / output cell and the second input / output cell,
    A first thyristor having an anode connected to the first input / output terminal and a cathode connected to the second input / output terminal; and
    4. The semiconductor integrated circuit according to claim 3, wherein a second thyristor having a cathode connected to the first input / output terminal and an anode connected to the second input / output terminal is formed.
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