JP2009146977A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is compact and tolerant of a surge. <P>SOLUTION: The semiconductor device has a protection circuit which protects an internal circuit connected to high-potential wiring, low-potential wiring, and signal wiring, against the surge input to the signal wiring. The protection circuit has a P-type well connected to the low-potential wiring and an N-type well adjacent to the P-type well and connected to the high-potential wiring. An NMOS region is formed in the P-type well. In the N-type well, a PMOS region is formed. In the P-type well within the range sandwiched between the NMOS region and N-type well, an N-type cathode region is formed, which is separated from the NMOS region and N-type well and connected to the low-potential wiring. In the N-type well within the range sandwiched between the PMOS region and P-type well, a P-type anode region is formed, which is separated from the PMOS region, P-type well, and N-type cathode region and connected to the high-potential wiring. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a protection circuit that protects an internal circuit from a surge.

  2. Description of the Related Art A semiconductor device having a protection circuit that protects an internal circuit from a surge is known. FIG. 12 is a plan view illustrating a semiconductor device provided with a plurality of wirings connected to the internal circuit 200. As shown in FIG. 12, the internal circuit 200 includes a high potential wiring 202 to which a first potential is applied, a low potential wiring 204 to which a second potential lower than the first potential is applied, a first potential and a second potential. A plurality of signal wirings 206 to which a signal potential that varies between potentials is applied are connected. The signal wiring 206 is either a wiring that inputs a signal potential input from the outside to the internal circuit 200 or a wiring that outputs a signal potential output from the internal circuit 200 to the outside. A protection circuit 210 is connected to each signal wiring 206. Each protection circuit 210 protects the internal circuit 200 from a surge input to the signal wiring 206. Although not shown in FIG. 12, the high potential wiring 202 and the low potential wiring 204 are connected to each protection circuit 210.

  FIG. 13 illustrates a cross-sectional view of the conventional protection circuit 210 (one of the plurality of protection circuits 210 shown in FIG. 12). FIG. 14 shows an equivalent circuit of the protection circuit 210 of FIG. As shown in FIGS. 13 and 14, a high potential wiring 202, a low potential wiring 204, and a signal wiring 206 are connected to the protection circuit 210. As shown in FIG. 13, the protection circuit 210 includes a P-type well 220 and an N-type well 230 adjacent to the P-type well 220. In the P-type well 220, an NMOS 228 including an N-type drain region 222, an N-type source region 224, and a gate electrode 226 is formed. The N-type drain region 222 is connected to the signal wiring 206. The P-type well 220, the N-type source region 224, and the gate electrode 226 are connected to the low potential wiring 204. That is, the NMOS 228 is connected between the signal wiring 206 and the low potential wiring 204 as shown in FIG. As shown in FIG. 13, a PMOS 238 including a P-type drain region 232, a P-type source region 234, and a gate electrode 236 is formed in the N-type well 230. The P-type drain region 232 is connected to the signal wiring 206. The N-type well 230, the P-type source region 234, and the gate electrode 236 are connected to the high potential wiring 202. That is, the PMOS 238 is interposed between the signal wiring 206 and the high potential wiring 202 as shown in FIG. As shown in FIG. 13, a diode (diode 240 in FIG. 14) that connects the signal wiring 206 and the low potential wiring 204 is formed by the P-type well 220 and the N-type drain region 222. As shown in FIG. 13, a diode (diode 250 in FIG. 14) that connects the signal wiring 206 and the high potential wiring 202 is formed by the N-type well 230 and the P-type drain region 232.

When a surge (hereinafter referred to as SIG-VDD surge) in which the signal wiring 206 is positive is applied between the signal wiring 206 and the high potential wiring 202, the diode 250 is turned on. Then, a current flows from the signal wiring 206 to the high potential wiring 202, and the SIG-VDD surge is attenuated. Therefore, a surge is prevented from being input from the signal wiring 206 to the internal circuit 200.
When a surge (hereinafter referred to as VDD-SIG surge) in which the signal wiring 206 is negative is applied between the signal wiring 206 and the high potential wiring 202, the PMOS 238 is turned on by a snapback phenomenon. Then, a current flows from the high potential wiring 202 to the signal wiring 206, and the VDD-SIG surge is attenuated. Therefore, a surge is prevented from being input from the signal wiring 206 to the internal circuit 200.
When a surge (hereinafter referred to as SIG-VSS surge) in which the signal wiring 206 is positive is applied between the signal wiring 206 and the low potential wiring 204, the NMOS 228 is turned on by a snapback phenomenon. Then, a current flows from the signal wiring 206 to the low potential wiring 204, and the SIG-VSS surge is attenuated. Therefore, a surge is prevented from being input from the signal wiring 206 to the internal circuit 200.
When a surge (hereinafter referred to as VSS-SIG surge) in which the signal wiring 206 is negative is applied between the signal wiring 206 and the low potential wiring 204, the diode 240 is turned on. Then, a current flows from the low potential wiring 204 to the signal wiring 206, and the VSS-SIG surge is attenuated. Therefore, a surge is prevented from being input from the signal wiring 206 to the internal circuit 200.

  Patent Document 1 discloses a protection circuit having substantially the same configuration as the conventional protection circuit 210 described above.

  The protection circuit 210 described above has a problem that the trigger voltage of the PMOS 238 is high. In addition, a plurality of PMOSs 238 are usually formed in order to reduce the current density when turned on. In this case, when a surge is applied, only a part of the PMOS 238 is turned on and the remaining PMOS 238 is not turned on. As described above, in the protection circuit 210 described above, the PMOS 238 may not be properly turned on, and the VDD-SIG surge cannot be sufficiently attenuated. Further, the NMOS 228 has the same problem as the PMOS 238, and there is a problem that the SIG-VSS surge cannot be sufficiently attenuated.

  As a technique for solving this problem, a semiconductor device in which a thyristor is formed at a position indicated by reference numeral 260 in FIGS. 12 and 14 is known. When the thyristor 260 is formed in this way, new current paths for the VDD-SIG surge and the SIG-VSS surge are formed. That is, when a VDD-SIG surge is applied, the diode 240 and the thyristor 260 are turned on. As a result, a current flows from the high potential wiring 202 to the signal wiring 206 along the path indicated by the arrow A1 in FIG. Further, when the SIG-VSS surge is applied, the diode 250 and the thyristor 260 are turned on. As a result, a current flows from the signal wiring 206 to the low potential wiring 204 along the path indicated by the arrow A2 in FIG.

Japanese Patent Laid-Open No. 11-017022

  In the technique of forming the thyristor 260 between the high potential wiring 202 and the low potential wiring 204 described above, the wiring path from the protection circuit 210 to the thyristor 260 becomes very long. Therefore, there is a problem that when current is passed through the thyristor 260, the surge is not sufficiently attenuated due to the influence of the wiring resistance between the protection circuit 210 and the thyristor 260. In order to solve this problem, a thyristor for connecting the high potential wiring 202 and the low potential wiring 204 may be formed at a position indicated by reference numeral 270 in FIG. 14 (that is, in the protection circuit 210). However, since the space for forming the protection circuit 210 is very limited, the semiconductor device itself must be enlarged to form the thyristor 270. In particular, as shown in FIG. 12, in a semiconductor device having a large number of protection circuits 210, the size of each protection circuit 210 increases, and thus there is a problem that the semiconductor device becomes very large.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a semiconductor device that is small in size and can suitably protect an internal circuit from a surge.

The semiconductor device of the present invention includes a high potential wiring to which a first potential is applied, a low potential wiring to which a second potential lower than the first potential is applied, and a signal potential that varies between the first potential and the second potential. The first signal wiring to which the voltage is applied, the internal circuit connected to the high potential wiring, the low potential wiring, and the first signal wiring, and the first protection circuit that protects the internal circuit from the surge input to the first signal wiring It has. The first protection circuit faces the surface of the semiconductor substrate, faces the first P-type well connected to the low-potential wiring, and faces the surface of the semiconductor substrate, and is adjacent to the first P-type well. A first N-type well connected to the potential wiring is provided. A first NMOS region having an N-type drain region, an N-type source region, and a gate electrode is formed in the first P-type well. The N-type drain region faces the surface of the first P-type well and is connected to the first signal wiring. The N-type source region faces the surface of the first P-type well, is separated from the N-type drain region, and is connected to the low potential wiring. The gate electrode faces the surface of the first P-type well between the N-type drain region and the N-type source region via an insulating film, and is connected to the low potential wiring. A first PMOS region having a P-type drain region, a P-type source region, and a gate electrode is formed in the first N-type well. The P-type drain region faces the surface of the first N-type well and is connected to the first signal wiring. The P-type source region faces the surface of the first N-type well, is separated from the P-type drain region, and is connected to the high potential wiring. The gate electrode of the first PMOS region faces the surface of the first N-type well between the P-type drain region and the P-type source region via an insulating film, and is connected to the high potential wiring. The first P-type well in the range sandwiched between the first NMOS region and the first N-type well faces the surface of the first P-type well, is separated from the first NMOS region and the first N-type well, and is connected to the low potential wiring. A connected first N-type cathode region is formed. The first N-type well in a range sandwiched between the first PMOS region and the first P-type well faces the surface of the first N-type well and is separated from the first PMOS region, the first P-type well, and the first N-type cathode region. A first P-type anode region connected to the high potential wiring is formed.
The first NMOS region may include a plurality of NMOSs each including an N-type drain region, an N-type source region, and a gate electrode. Similarly, the first PMOS region may include a plurality of PMOSs including a P-type drain region, a P-type source region, and a gate electrode.

  FIG. 15 is a plan view of a protective circuit of a semiconductor device as an example of the present invention as viewed from the upper surface side of a semiconductor substrate. In FIG. 15, reference numeral 302 indicates a high potential wiring, reference numeral 304 indicates a low potential wiring, reference numeral 306 indicates a first signal wiring, reference numeral 320 indicates a first P-type well, and reference numeral 322. Indicates an N-type drain region, reference number 324 indicates an N-type source region, reference number 326 indicates a gate electrode, reference number 328 indicates a first NMOS region, reference number 330 indicates a first N-type well, Reference number 332 indicates a P-type drain region, reference number 334 indicates a P-type source region, reference number 336 indicates a gate electrode, reference number 338 indicates a first PMOS region, and reference number 372 indicates a first N-type cathode region. Reference numeral 374 indicates a first P-type anode region. FIG. 15 shows a semiconductor device in which the first NMOS region 328 has a plurality of NMOS structures and the first PMOS region 338 has a plurality of PMOS structures. FIG. 15 illustrates a semiconductor device having this configuration, and does not limit the configuration of the semiconductor device of the present invention.

As shown in FIG. 15, in the semiconductor device of the present invention, a first N-type cathode region 372 and a first P-type anode region 374 are formed in the vicinity of the boundary between the first P-type well 320 and the first N-type well 330. That is, the first P-type anode region 374, the first N-type well 330, the first P-type well 320, and the first N-type cathode region 372 form a thyristor that connects the high-potential wiring 202 and the low-potential wiring 204. That is, the thyristor is formed in the protection circuit. Therefore, even if the NMOS structure of the first NMOS region 328 or the PMOS structure of the first PMOS region 338 is not properly turned on, the surge can be suitably attenuated.
The thyristor is formed using a PN junction between the first P-type well 320 and the first N-type well 330. Further, a space near the boundary between the first P-type well 320 and the first N-type well 330 is a space that has existed conventionally to separate the first NMOS region 328 and the first PMOS region 338, and the first N-type cathode region 372 exists in the space. And a first P-type anode region 374 is formed. Therefore, the thyristor is formed without increasing the size of the protection circuit. Therefore, this semiconductor device is hardly increased in size from the conventional semiconductor device.

  A semiconductor device having a plurality of signal wirings, that is, a signal potential that varies between the first potential and the second potential is applied, and the second signal wiring connected to the internal circuit is input to the second signal wiring. The semiconductor device further including the second protection circuit for protecting the internal circuit from the surge is preferably configured as follows. That is, the second protection circuit has a second P-type well and a second N-type well. The second P-type well faces the surface of the semiconductor substrate, is adjacent to the first N-type well, and is connected to the low potential wiring. The second N-type well faces the surface of the semiconductor substrate, is adjacent to the first P-type well and the second P-type well, and is connected to the high potential wiring. A second NMOS region having an N-type drain region, an N-type source region, and a gate electrode is formed in the second P-type well. A second PMOS region including a P-type drain region, a P-type source region, and a gate electrode is formed in the second N-type well. The second P-type well in the range sandwiched between the second NMOS region and the second N-type well faces the surface of the second P-type well and is separated from the second NMOS region and the second N-type well. A connected second N-type cathode region is formed. The second N-type well in the range sandwiched between the second PMOS region and the second P-type well faces the surface of the second N-type well and is separated from the second PMOS region, the second P-type well, and the second N-type cathode region. Thus, a second P-type anode region connected to the high potential wiring is formed. The first P-type well in the range sandwiched between the first NMOS region and the second N-type well faces the surface of the first P-type well, is separated from the first NMOS region and the second N-type well, and is connected to the low potential wiring. A connected third N-type cathode region is formed. The second N-type well in a range sandwiched between the second PMOS region and the first P-type well faces the surface of the second N-type well and is separated from the second PMOS region, the first P-type well, and the third N-type cathode region. Thus, a third P-type anode region connected to the high potential wiring is formed. The first N-type well in the range sandwiched between the first PMOS region and the second P-type well faces the surface of the first N-type well and is separated from the first PMOS region and the second P-type well. A connected fourth P-type anode region is formed. The second P-type well sandwiched between the second NMOS region and the first N-type well faces the surface of the second P-type well and is separated from the second NMOS region, the first N-type well, and the fourth P-type anode region. In addition, a fourth N-type cathode region connected to the low potential wiring is formed.

  FIG. 16 is a plan view of an example of the protection circuit of the semiconductor device having this configuration as viewed from the upper surface side of the semiconductor substrate. In FIG. 16, reference numeral 310 indicates the first protection circuit, reference numeral 410 indicates the second protection circuit, reference numeral 420 indicates the second P-type well, reference numeral 428 indicates the second NMOS region, and reference numeral Reference numeral 430 denotes a second PMOS region, reference numeral 472 denotes a second N-type cathode region, reference numeral 474 denotes a second P-type anode region, and reference numeral 476 denotes a third N-type well. Reference numeral 478 indicates a third P-type anode area, reference numeral 480 indicates a fourth P-type anode area, and reference numeral 482 indicates a fourth N-type cathode area. Other reference numbers correspond to FIG. In FIG. 16, the high-potential wiring, the low-potential wiring, the first signal wiring, and the second signal wiring are not illustrated for easy viewing. Also, the reference numbers are not assigned to the respective parts (drain region, source region and gate electrode) of the first NMOS region, the first PMOS region, the second NMOS region and the second PMOS region. FIG. 16 exemplifies a semiconductor device having this configuration, and does not limit the configuration of the semiconductor device of the present invention.

As shown in FIG. 16, in this semiconductor device, a second protection circuit 410 is formed adjacent to the first protection circuit 310. In the second protection circuit 410, the second N-type well 430 is adjacent to the first P-type well 320 of the first protection circuit 310, and the second P-type well 420 is adjacent to the first N-type well 330 of the first protection circuit 310. It is formed as follows. In the vicinity of the boundary between the second P-type well 420 and the second N-type well 430, the second P-type anode region 474, the second N-type well 430, the second P-type well 420, and the second N-type cathode region 472 provide high potential wiring and low A thyristor for connecting the potential wiring is formed. In the vicinity of the boundary between the second N-type well 430 and the first P-type well 320, a high-potential wiring and a low potential are formed by the third P-type anode region 478, the second N-type well 430, the first P-type well 320, and the third N-type cathode region 476. A thyristor for connecting the wiring is formed. A thyristor is formed in the vicinity of the boundary between the second P-type well 420 and the first N-type well 330 by the fourth P-type anode region 480, the first N-type well 330, the second P-type well 420, and the fourth N-type cathode region 482. That is, a plurality of thyristors are connected in parallel between the high potential wiring and the low potential wiring. Therefore, when a surge is applied, a larger current can flow between the high potential wiring and the low potential wiring. The surge can be attenuated more preferably.
Further, in this semiconductor device, each well is disposed so that a PN junction is formed at the boundary between the first protection circuit 310 and the second protection circuit 410. The PN at the boundary between the first protection circuit 310 and the second protection circuit 410 (that is, the boundary between the first P-type well 320 and the second N-type well 430 and the boundary between the first N-type well 330 and the second P-type well 420). A thyristor is formed by using the junction. Therefore, a thyristor can be formed without increasing the size of the first protection circuit 310 and the second protection circuit 410.

  In the semiconductor device described above, the first signal wiring extends linearly on the semiconductor substrate and connects at least one of the N-type drain region of the first NMOS region and at least one of the P-type drain region of the first PMOS region. It is preferable. The first P-type well sandwiched between the first NMOS region and the first N-type well and faces the surface of the first P-type well in the lower range of the first signal wiring. It is preferable that a fifth N-type cathode region that is separated from the 1N-type cathode region and the first P-type anode region and is connected to the first signal wiring is formed. Furthermore, the first N-type well is sandwiched between the first PMOS region and the first P-type well and faces the surface of the first N-type well in the lower portion of the first signal wiring, and the first PMOS region, the first P-type well, Preferably, a fifth P-type anode region is formed that is separated from the 1P-type anode region, the first N-type cathode region, and the fifth N-type cathode region and is connected to the first signal wiring.

  FIG. 17 is a plan view of an example of the protection circuit of the semiconductor device having this configuration as viewed from the upper surface side of the semiconductor substrate. In FIG. 17, reference numeral 500 indicates the fifth N-type cathode region, and reference numeral 510 indicates the fifth P-type anode region. Other reference numbers correspond to FIG. In FIG. 17, the high-potential wiring and the low-potential wiring are not shown in consideration of easy viewing, and only a part of the first signal wiring 306 is illustrated. FIG. 17 exemplifies a semiconductor device having this configuration, and does not limit the configuration of the semiconductor device of the present invention.

According to the configuration of FIG. 17, the first P-type well 320 and the fifth N-type cathode region 500 form a diode that connects the first signal wiring 306 and the low potential wiring 304. That is, a diode similar to the diode formed by the first P-type well 320 and the N-type drain region 322 (a diode corresponding to the diode 240 in FIG. 14) is further formed between the first signal wiring 306 and the low potential wiring 304. Has been. Therefore, a larger current can flow from the low potential wiring 304 to the first signal wiring 306. The surge can be attenuated more preferably.
Further, according to the configuration of FIG. 17, the first N-type well 330 and the fifth P-type anode region 510 form a diode that connects the first signal wiring 306 and the high potential wiring 302. That is, a diode similar to the diode formed by the first N-type well 330 and the P-type drain region 332 (a diode corresponding to the diode 250 in FIG. 14) is further formed between the first signal wiring 306 and the high potential wiring 302. Has been. Therefore, a larger current can flow from the first signal wiring 306 to the high potential wiring 302. The surge can be attenuated more preferably.
Further, since the fifth N-type cathode region 500 and the fifth P-type anode region 510 are formed in a space near the boundary between the first P-type well 320 and the first N-type well 330, the size of the first protection circuit may be increased. Absent. Furthermore, since the fifth N-type cathode region 500 and the fifth P-type anode region 510 are formed on a straight line connecting the N-type drain region 322 and the P-type drain region 332, the first signal extending linearly on the semiconductor substrate. The wiring 306 can connect the N-type drain region 322, the P-type drain region 332, the fifth N-type cathode region 500, and the fifth P-type anode region 510. That is, the first signal wiring can be efficiently arranged.

  According to the present invention, it is possible to provide a semiconductor device that is small and resistant to surge.

The main features of the embodiments described in detail below are listed first.
(Feature 1) A plurality of NMOSs are formed in the first NMOS region. Each NMOS shares an N-type drain region and an N-type source region with an adjacent NMOS.
(Feature 2) A plurality of PMOSs are formed in the first PMOS region. Each PMOS shares a P-type drain region and a P-type source region with an adjacent PMOS.

  Embodiments in which the present invention is applied to an IC will be described with reference to the drawings. The IC of this embodiment includes a semiconductor substrate, wiring formed on the semiconductor substrate, an insulating film, and the like. An internal circuit and a plurality of protection circuits are formed on the semiconductor substrate. On the semiconductor substrate, a plurality of electrode pads and wiring for connecting each electrode pad to an internal circuit are formed. FIG. 1 is an enlarged plan view of a range in which a wiring for connecting an electrode pad and an internal circuit is formed on the upper surface of the IC 10 (semiconductor substrate 12) of the present embodiment. In the following, the left-right direction in FIG. 1 is referred to as the X direction, and the up-down direction (the direction orthogonal to the X direction) is referred to as the Y direction. As shown in the drawing, electrode pads 20a to 20e are formed on the end portion (left end in FIG. 1) of the upper surface of the semiconductor substrate 12. The electrode pads 20a to 20e are arranged in the Y direction. The electrode pads 20a to 20e are connected to the internal circuit 14 by corresponding wirings 22a to 22e. The IC 10 has a large number of electrode pads and wirings outside the range shown in FIG.

The electrode pad 20a is a VDD pad to which a power supply potential is applied. The VDD pad 20a is connected to the internal circuit 14 by a VDD wiring 22a. A protection circuit 24a that protects the internal circuit 14 from a surge input to the VDD pad 20a is formed on the semiconductor substrate 12 in the vicinity of the VDD wiring 22a.
The electrode pad 20b is a GND pad to which a ground potential is applied. The GND pad 20b is connected to the internal circuit 14 by a GND wiring 22b. A protection circuit 24b that protects the internal circuit 14 from a surge input to the GND pad 20b is formed on the semiconductor substrate 12 in the vicinity of the GND wiring 22b.
The electrode pads 20c to 20e are signal pads to which a signal potential that varies between a power supply potential and a ground potential is applied. More specifically, each of the signal pads 20c to 20e is either an input pad that inputs a signal potential input from the outside to the internal circuit 14, or an output pad that outputs the signal potential output from the internal circuit 14 to the outside. is there. The signal pads 20c to 20e are connected to the internal circuit 14 by corresponding signal wirings 22c to 22e. Protection circuits 24c to 24e that protect the internal circuit 14 from surges input to the signal pads 20c to 20e are formed on the semiconductor substrate 12 in the vicinity of the signal wirings 22c to 22e. Although not shown in FIG. 1, the VDD wiring 22a and the GND wiring 22b are also connected to the protection circuits 24c to 24e.

  Next, the structure of the IC 10 will be described in detail. The IC 10 of the present embodiment is characterized by the protection circuits 24c to 24e, and a general structure is adopted for the internal circuit 14 and the protection circuits 24a and 24b. Therefore, the protection circuits 24c to 24e will be described below, and the description of the internal circuit 14 and the protection circuits 24a and 24b will be omitted.

  FIG. 2 is a plan view of the semiconductor substrate 12 in a range where the protection circuits 24c to 24e are formed, as viewed from above. FIG. 2 shows only the arrangement of regions formed in each protection circuit, and details thereof are not shown. As shown in FIG. 2, the protection circuits 24c to 24e are arranged in the Y direction. The protection circuits 24 c to 24 e include a P-type well 30 and an N-type well 50. The P-type well 30 is a P-type region in which P-type impurities are implanted in a certain depth range from the upper surface of the semiconductor substrate 12. The N-type well 50 is an N-type region in which N-type impurities are implanted in a certain depth range from the upper surface of the semiconductor substrate 12. As shown in the figure, in each of the protection circuits 24c to 24e, the P-type well 30 and the N-type well 50 are formed adjacent to each other in the X direction. In the protection circuits 24c and 24e, the N-type well 50 is disposed on the left side, and the P-type well 30 is disposed on the right side. In the protection circuit 24d, the P-type well 30 is disposed on the left side, and the N-type well 50 is disposed on the right side. Therefore, the P-type well 30 of the protection circuit 24d is adjacent to the N-type well 50 of the protection circuit 24c in the Y direction, and is adjacent to the N-type well 50 of the protection circuit 24e in the Y direction. The N-type well 50 of the protection circuit 24d is adjacent to the P-type well 30 of the protection circuit 24c in the Y direction, and is adjacent to the P-type well 30 of the protection circuit 24e in the Y direction. An NMOS region 38 is formed in the P-type well 30 of the protection circuits 24c to 24e. The NMOS region 38 is a region where a plurality of NMOSs are formed near the upper surface of the semiconductor substrate 12. A PMOS region 58 is formed in the N-type well 50 of the protection circuits 24c to 24e. The PMOS region 58 is a region where a plurality of PMOSs are formed near the upper surface of the semiconductor substrate 12.

  Next, details of the protection circuit will be described. The protection circuits 24c to 24e described above differ only in the arrangement of the P-type well 30 (that is, the NMOS region 38) and the N-type well 50 (that is, the PMOS region 58). Since the structure in the well 50 is the same, the protection circuit 24d will be described below.

  FIG. 3 is a plan view of the protection circuit 24d as viewed from the upper surface side of the semiconductor substrate 12. FIG. Note that a VDD wiring 22a, a GND wiring 22b, and a signal wiring 22d are extended on the semiconductor substrate 12 in a range where the protection circuit 24d is formed, but are not illustrated in FIG. In FIG. 3, the gate electrodes 34 and 54 and the STI layers 60, 70, 76, 82, and 88 are shown in a hatched pattern for easy viewing.

  As shown in FIG. 3, an NMOS region 38 in which a plurality of N-type drain regions 32, gate electrodes 34, and N-type source regions 36 are formed is formed in the P-type well 30. The N-type drain region 32, the gate electrode 34, and the N-type source region 36 extend long in the X direction and are arranged in the Y direction.

FIG. 4 shows a cross-sectional view of the semiconductor substrate 12 taken along the line IV-IV in FIG. As shown in FIG. 4, the N-type drain region 32 and the N-type source region 36 are formed in a range facing the upper surface of the semiconductor substrate 12 (that is, the upper surface of the P-type well 30). As shown in FIGS. 3 and 4, the N-type drain region 32 and the N-type source region 36 are alternately and repeatedly formed in the Y direction at a predetermined interval. Therefore, as shown in FIG. 4, the P-type well 30 is exposed on the upper surface of the semiconductor substrate 12 between the N-type drain region 32 and the N-type source region 36. A gate insulating film 35 is formed on the semiconductor substrate 12 in a range where the P-type well 30 is exposed on the upper surface. A gate electrode 34 is formed on the gate insulating film 35. That is, the gate electrode 34 is opposed to the upper surface of the P-type well 30 between the N-type drain region 32 and the N-type source region 36 with the gate insulating film 35 interposed therebetween. The gate electrode 34 is connected to the GND wiring 22b.
The N-type drain region 32 includes a first region 32a, a high resistance region 32b, and a second region 32c. Although not shown, a low-resistance silicide film is formed over the entire upper surface of the first region 32a and the second region 32c. The resistance of the first region 32a and the second region 32c is reduced by the silicide film. The high resistance region 32b is formed in a shallower range than the first region 32a and the second region 32c. The high resistance region 32b has a lower impurity concentration than the first region 32a and the second region 32c. Further, no silicide film is formed on the upper surface of the high resistance region 32b. Therefore, the high resistance region 32b has a high resistance. As shown in FIG. 3, the high resistance region 32b extends in the X direction, and separates the first region 32a and the second region 32c. This increases the resistance of the current path from the first region 32a to the second region 32c. Although not shown, an insulating film is formed on the upper surface of the N-type drain region 32 (on the silicide film in the first region 32a and the second region 32c). A contact hole is formed in the insulating film on the first region 32a. The first region 32a is connected to the signal wiring 22d by a contact hole as shown in FIG.
A silicide film is formed on the upper surface of the N-type source region 36. Thereby, the resistance of the N-type source region 36 is reduced. An insulating film is formed on the silicide film of the N-type source region 36. A contact hole is formed in the insulating film. The N-type source region 36 is connected to the GND wiring 22b by a contact hole as shown in FIG.
Due to the structure of the NMOS region 38 described above, a plurality of NMOSs 40 are formed in the NMOS region 38. That is, the NMOS 40 is formed by the gate electrode 34, the P-type well 30 in a range facing the gate electrode 34, and the N-type drain region 32 and the N-type source region 36 adjacent to the gate electrode 34. Each NMOS 40 shares the N-type drain region 32 and the N-type source region 36 with the adjacent NMOS 40. As a result, the NMOS 40 is formed in the NMOS region 38 with high density.

  As shown in FIG. 3, the P-type well 30 includes a P-type well contact region 30 a formed so as to surround the periphery of the NMOS region 38. The P-type well contact region 30a is formed in a range facing the upper surface of the semiconductor substrate 12 (that is, the upper surface of the P-type well 30). The P-type well contact region 30a has a higher impurity concentration than the P-type well 30 outside the region. The upper surface of the P-type well 30 is covered with an insulating film (not shown). A contact hole is formed in the insulating film above the P-type well contact region 30a. The P-type well contact region 30a is connected to the GND wiring 22b through the contact hole as shown in FIG. The P-type well contact region 30a is connected to the GND wiring 22b via a poly resistance layer (not shown) formed on the insulating film. The resistor 31 in FIG. 4 indicates the electrical resistance of the poly resistance layer.

FIG. 5 is a circuit diagram showing an equivalent circuit of the protection circuit 24d.
The NMOS 40 described above is connected between the signal wiring 22d and the GND wiring 22b as shown in FIG. Each NMOS 40 in the NMOS region 38 is connected in parallel between the signal wiring 22d and the GND wiring 22b, and substantially operates as one NMOS. Therefore, only one NMOS 40 is shown in FIG. The P-type well 30 (that is, the back gate of the NMOS 40) is connected to the GND wiring 22b through a poly resistance layer. The resistor 31a in FIG. 5 indicates the electrical resistance of the poly resistance layer (the same resistance as the resistor 31 in FIG. 4).
Further, in the above-described NMOS region 38, the path from the GND wiring 22b to the signal wiring 22d via the P-type well 30 (including the P-type well contact region 30a) and the N-type drain region 32 is shown in FIG. The diode 42 shown is formed. Note that the P-type well 30 (that is, the anode of the diode 42) is connected to the GND wiring 22b through a poly resistance layer. A resistor 31b in FIG. 5 indicates the electrical resistance of the poly resistance layer (the same resistance as the resistor 31 in FIG. 4).

  As shown in FIG. 3, a PMOS region 58 in which a plurality of P-type drain regions 52, gate electrodes 54, and P-type source regions 56 are formed is formed in the N-type well 50. FIG. 6 shows a cross-sectional view of the semiconductor substrate 12 taken along line VI-VI in FIG. As shown in FIG. 6, each region is arranged in the PMOS region 58 in the same manner as the NMOS region 38 described above. That is, the P-type drain region 52 is formed at a position corresponding to the N-type drain region 32, the gate electrode 54 is formed at a position corresponding to the gate electrode 34, and the P-type source region 56 is an N-type source region. It is formed at a position corresponding to 36. The P-type drain region 52 is connected to the signal wiring 22d. The gate electrode 54 and the P-type source region 56 are connected to the VDD wiring 22a. As shown in FIGS. 3 and 6, a high resistance region 52 b is formed in the P-type drain region 52. As a result, the P-type drain region 52 has a high resistance. Due to the structure of the PMOS region 58 described above, a plurality of PMOSs 44 are formed in the PMOS region 58.

  As shown in FIG. 3, the N-type well 50 includes an N-type well contact region 50 a formed so as to surround the periphery of the PMOS region 58. The N-type well contact region 50 a is formed in a range facing the upper surface of the N-type well 50. The N-type well contact region 50a has a higher impurity concentration than the N-type well 50 outside the region. N-type well contact region 50a is connected to VDD wiring 22a through a contact hole. The N-type well contact region 50a is connected to the VDD wiring 22a through a poly resistance layer (not shown) formed on the insulating film above the N-type well contact region 50a. The resistor 33 in FIG. 6 indicates the electrical resistance of the poly resistance layer.

The PMOS 44 described above is connected between the VDD wiring 22a and the signal wiring 22d as shown in FIG. Each PMOS 44 in the PMOS region 58 is connected in parallel between the VDD wiring 22a and the signal wiring 22d, and substantially operates as one PMOS. Therefore, only one PMOS 44 is shown in FIG. Further, the N-type well 50 (that is, the back gate of the PMOS 44) is connected to the VDD wiring 22a through a poly resistance layer. The resistor 33a in FIG. 5 indicates the electrical resistance of the poly resistance layer (the same resistance as the resistor 33 in FIG. 6).
Further, in the above-described PMOS region 58, the path from the signal wiring 22d through the P-type drain region 52 and the N-type well 50 (including the N-type well contact region 50a) to the VDD wiring 22a is shown in FIG. A diode 46 is formed. Note that the N-type well 50 (that is, the cathode of the diode 46) is connected to the VDD wiring 22a through a poly resistance layer. A resistor 33b in FIG. 5 indicates an electric resistance of the poly resistance layer (the same resistance as the resistor 33 in FIG. 6).

  As shown in FIG. 3, at the boundary between the P-type well 30 and the N-type well 50, an STI layer 60, an N-type cathode region 62, a P-type anode region 64, an N-type cathode region 66, and a P-type An anode region 68 is formed.

FIG. 7 shows a cross-sectional view of the semiconductor substrate 12 taken along line VII-VII in FIG.
As illustrated, the STI layer 60 is an insulating layer in which an insulator is embedded in a trench 61 on the upper surface of the semiconductor substrate 12. As shown in FIG. 3, the STI layer 60 is formed along the boundary between the P-type well 30 and the N-type well 50.
The N-type cathode region 62 is formed in the P-type well 30. As shown in FIG. 3, the N-type cathode region 62 is formed along the STI layer 60. As shown in FIG. 7, the N-type cathode region 62 faces the upper surface of the semiconductor substrate 12 and is formed in a range shallower than the STI layer 60. The upper surface of the N-type cathode region 62 is covered with an insulating film (not shown). A contact hole is formed in the insulating film. The N-type cathode region 62 is connected to the GND wiring 22b through a contact hole.
The P-type anode region 64 is formed in the N-type well 50. As shown in FIG. 3, the P-type anode region 64 is formed along the STI layer 60. As shown in FIG. 7, the P-type anode region 64 faces the upper surface of the semiconductor substrate 12 and is formed in a shallower range than the STI layer 60. The upper surface of the P-type anode region 64 is covered with an insulating film (not shown). A contact hole is formed in the insulating film. The P-type anode region 64 is connected to the VDD wiring 22a through a contact hole.
A thyristor 48 that connects the VDD wiring 22a and the GND wiring 22b through a path from the VDD wiring 22a to the GND wiring 22b through the P-type anode region 64, the N-type well 50, the P-type well 30, and the N-type cathode region 62. Is formed. That is, a thyristor 48 is connected as shown in FIG.

FIG. 8 shows a cross-sectional view of the semiconductor substrate 12 taken along line VIII-VIII in FIG.
As illustrated, the N-type cathode region 66 is formed in the P-type well 30. The N-type cathode region 66 is formed along the STI layer 60. The N-type cathode region 66 faces the upper surface of the semiconductor substrate 12 and is formed in a range shallower than the STI layer 60. The upper surface of the N-type cathode region 66 is covered with an insulating film (not shown). A contact hole is formed in the insulating film. The N-type cathode region 66 is connected to the signal wiring 22d through a contact hole.
A path from the GND wiring 22b to the signal wiring 22d via the P-type well 30 (including the P-type well contact region 30a) and the N-type cathode region 66 forms a diode 100 that connects the GND wiring 22b and the signal wiring 22d. is doing. The diode 100 is connected in parallel with the above-described diode 42 (see FIG. 5). Therefore, in FIG. 5, the diode 42 and the diode 100 are indicated by one circuit symbol.

As shown in FIG. 8, the P-type anode region 68 is formed in the N-type well 50. The P-type anode region 68 is formed along the STI layer 60. The P-type anode region 68 faces the upper surface of the semiconductor substrate 12 and is formed in a range shallower than the STI layer 60. The upper surface of the P-type anode region 68 is covered with an insulating film (not shown). A contact hole is formed in the insulating film. The P-type anode region 68 is connected to the signal wiring 22d through a contact hole.
A path from the signal wiring 22d to the VDD wiring 22a through the P-type anode region 68 and the N-type well 50 (including the N-type well contact region 50a) forms a diode 102 that connects the signal wiring 22d and the VDD wiring 22a. is doing. The diode 102 is connected in parallel with the above-described diode 46 (see FIG. 5). Therefore, in FIG. 5, the diode 46 and the diode 102 are shown by one circuit symbol.

  FIG. 9 is a plan view showing the position of the signal wiring 22d on the protection circuit 24d. As shown in the figure, on the semiconductor substrate 12, three signal wirings 22d extend linearly along the X direction. Each signal line 22 d passes over the N-type drain region 32 and the P-type drain region 52. An insulating film is formed between the semiconductor substrate 12 and the signal wiring 22d. The N-type drain region 32 and the P-type drain region 52 are connected to the signal wiring 22d through a contact hole formed in the upper part thereof. The N-type cathode region 66 and the P-type anode region 68 described above are formed below the central signal wiring 22d. The N-type cathode region 66 and the P-type anode region 68 are connected to the signal wiring 22d through a contact hole formed in the upper part thereof.

As described above, the P-type well 30 of the protection circuit 24d is adjacent to the N-type well 50 of the protection circuit 24c and the N-type well 50 of the protection circuit 24e in the Y direction.
As shown in FIG. 3, an STI layer 70, an N-type cathode region 72, and a P-type anode region 74 are formed at the boundary between the P-type well 30 of the protection circuit 24d and the N-type well 50 of the protection circuit 24c. ing. The STI layer 70 is formed along the boundary between the P-type well 30 of the protection circuit 24d and the N-type well 50 of the protection circuit 24c. The N-type cathode region 72 is formed along the STI layer 70 in the P-type well 30 of the protection circuit 24d. The P-type anode region 74 is formed along the STI layer 70 in the N-type well 50 of the protection circuit 24c. The STI layer 70, the N-type cathode region 72, and the P-type anode region 74 have the same cross-sectional structure as that of FIG. The N-type cathode region 72 is connected to the GND wiring 22b. The P-type anode region 74 is connected to the VDD wiring 22a. Therefore, the path from the VDD wiring 22a to the GND wiring 22b via the P-type anode region 74, the N-type well 50 of the protection circuit 24c, the P-type well 30 of the protection circuit 24d, and the N-type cathode region 72 is the VDD wiring 22a. And a thyristor 104 for connecting the GND wiring 22b.
Similarly, an STI layer 76, an N-type cathode region 78, and a P-type anode region 80 are formed at the boundary between the P-type well 30 of the protection circuit 24d and the N-type well 50 of the protection circuit 24e. A thyristor 106 that connects the VDD wiring 22a and the GND wiring 22b is formed by the P-type anode region 80, the N-type well 50 of the protection circuit 24e, the P-type well 30 of the protection circuit 24d, and the N-type cathode region 78.

As described above, the N-type well 50 of the protection circuit 24d is adjacent to the P-type well 30 of the protection circuit 24c and the P-type well 30 of the protection circuit 24e in the Y direction.
As shown in FIG. 3, an STI layer 82, a P-type anode region 84, and an N-type cathode region 86 are formed at the boundary between the N-type well 50 of the protection circuit 24d and the P-type well 30 of the protection circuit 24c. ing. The STI layer 82 is formed along the boundary between the N-type well 50 of the protection circuit 24d and the P-type well 30 of the protection circuit 24c. The P-type anode region 84 is formed along the STI layer 82 in the N-type well 50 of the protection circuit 24d. The N-type cathode region 86 is formed along the STI layer 82 in the P-type well 30 of the protection circuit 24c. The STI layer 82, the P-type anode region 84, and the N-type cathode region 86 have the same cross-sectional structure as that of FIG. The P-type anode region 84 is connected to the VDD wiring 22a. The N-type cathode region 86 is connected to the GND wiring 22b. Therefore, the path from the VDD wiring 22a to the GND wiring 22b via the P-type anode region 84, the N-type well 50 of the protection circuit 24d, the P-type well 30 of the protection circuit 24c, and the N-type cathode region 86 is the VDD wiring 22a. The thyristor 108 that connects the GND wiring 22b is formed.
Similarly, an STI layer 88, a P-type anode region 90, and an N-type cathode region 92 are formed at the boundary between the N-type well 50 of the protection circuit 24d and the P-type well 30 of the protection circuit 24e. A thyristor 110 that connects the VDD wiring 22a and the GND wiring 22b is formed by the P-type anode region 90, the N-type well 50 of the protection circuit 24d, the P-type well 30 of the protection circuit 24e, and the N-type cathode region 92.

  The thyristors 104, 106, 108 and 110 are connected in parallel with the thyristor 48 (see FIG. 5) described above. Therefore, in FIG. 5, the thyristors 48, 104, 106, 108 and 110 are indicated by one circuit symbol.

  FIG. 10 shows the boundary between the four wells of the P-type well 30 of the protection circuit 24d, the N-type well 50 of the protection circuit 24d, the P-type well 30 of the protection circuit 24c, and the N-type well 50 of the protection circuit 24c. The enlarged view (The top view which looked at the semiconductor substrate 12 from the upper side) is shown. As shown in the figure, the N-type well 50 of the protection circuit 24d and the N-type well 50 of the protection circuit 24c are continuous at the boundary between the four wells. This prevents the boundary lines of the wells from intersecting. Thus, each well can be easily formed at the time of manufacturing the IC 10. Similarly, each well is formed at the boundary between the protection circuit 24d and the protection circuit 24e.

  Next, the operation of the protection circuit 24d will be described. The protection circuit 24d protects the internal circuit 14 from a surge input to the signal wiring 22d. The signal wiring 22d includes a surge in which the signal wiring 22d is positive with respect to the VDD wiring 22a (hereinafter referred to as SIG-VDD surge) and a surge in which the signal wiring 22d is negative with respect to the VDD wiring 22a (hereinafter referred to as VDD-SIG surge), a surge in which the signal wiring 22d is positive with respect to the GND wiring 22b (hereinafter referred to as SIG-GND surge), and a surge in which the signal wiring 22d is negative with respect to the GND wiring 22b (hereinafter, referred to as “VDD-SIG surge”). Then, four types of surges (referred to as GND-SIG surge) may be input. Hereinafter, the operation of the protection circuit 24d when each surge is input will be described.

(Operation when SIG-VDD surge is input)
When the SIG-VDD surge is input to the signal wiring 22d, the diode 46 (102) in FIG. 5 is turned on. As a result, a current flows from the signal wiring 22d to the VDD wiring 22a, and the SIG-VDD surge is attenuated.
As shown in FIG. 5, two diodes 46 and 102 are connected between the signal wiring 22d and the VDD wiring 22a. Therefore, a high current can flow from the signal wiring 22d to the VDD wiring 22a when the SIG-VDD surge is input. Preferably, the SIG-VDD surge can be attenuated.

(Operation when VDD-SIG surge is input)
When a VDD-SIG surge is input to the signal wiring 22d, the PMOS 44 in FIG. 5 is turned on by a snapback phenomenon. As a result, a current flows from the VDD wiring 22a to the signal wiring 22d, and the VDD-SIG surge is attenuated.
The snapback phenomenon of the PMOS 44 will be described in detail. FIG. 11 is a graph illustrating the snapback phenomenon. 11 indicates the surge voltage V1 (voltage when the VDD wiring 22a is positive) applied between the VDD wiring 22a and the signal wiring 22d, and the vertical axis in FIG. 11 indicates a signal from the VDD wiring 22a. A current I1 flowing through the wiring 22d is shown.
First, with the input of the VDD-SIG surge, the voltage V1 starts to rise as shown by the arrow B1 in FIG. At this time, a voltage substantially equal to the voltage V1 is applied to the PN junction (see FIG. 6) at the boundary between the N-type well 50 and the P-type drain region 52 in the reverse direction. At this stage, the current I1 is zero. When the voltage V1 rises to the avalanche voltage VA of the PN junction, the PN junction at the boundary between the N-type well 50 and the P-type drain region 52 breaks down. Then, the current I1 starts to flow from the VDD wiring 22a to the signal wiring 22d via the N-type well 50 (including the N-type well contact region 50a) and the P-type drain region 52. Thereafter, as indicated by an arrow B2 in FIG. 11, the current I1 increases as the voltage V1 increases. The current I1 flowing at this time flows to the N-type well 50 (N-type well contact region 50a) via the resistor 33 (resistor 33a in FIG. 5). Therefore, due to the voltage drop in the resistor 33, the potential of the N-type well 50 becomes lower than the potential of the VDD wiring 22a. When the current I1 flows in the N-type well 50, a potential distribution is generated in the N-type well 50 due to the electrical resistance in the N-type well 50. That is, the potential is higher near the N-type well contact region 50a, and the potential is lower near the P-type drain region 52. Therefore, when the current I1 increases, the potential of the N-type well 50 in the vicinity of the P-type source region 56 decreases. Then, since the potential of the P-type source region 56 is substantially equal to that of the VDD wiring 22a, a forward voltage is applied to the PN junction at the boundary between the P-type source region 56 and the N-type well 50. When the voltage V1 rises to a predetermined voltage (trigger voltage VT), the forward voltage applied to the PN junction at the boundary between the P-type source region 56 and the N-type well 50 becomes higher than the ON voltage of the PN junction. Turns on. That is, the PMOS 44 is turned on (snapback phenomenon). That is, the current I1 flows from the VDD wiring 22a toward the signal wiring 22d via the P-type source region 56, the N-type well 50, and the P-type drain region 52. Then, as indicated by an arrow B3 in FIG. 11, the voltage V1 rapidly decreases while the current I1 increases. After the voltage V1 decreases to a predetermined value, the current I1 rises and the voltage V1 rises gently as shown by an arrow B4 in FIG. The amount of charge corresponding to the magnitude of the VDD-SIG surge flows from the VDD wiring 22a to the signal wiring 22d, so that the VDD-SIG surge is attenuated. Therefore, the voltage V1 is prevented from becoming higher than the trigger voltage VT. In the protection circuit 24d, the resistance of the P-type drain region 52 is increased by the high resistance region 52b. As a result, the increase of the voltage V1 is suppressed after the snap-back of the PMOS 44 (in the operating state indicated by the arrow B4 in FIG. 11).

The PMOS 44 described above has a problem that the trigger voltage VT is relatively high and it is difficult to turn on when a VDD-SIG surge is input. Further, as described above, a plurality of PMOSs 44 are formed in the PMOS region 58. However, there is a case where only a part of the PMOSs 44 is turned on when the VDD-SIG surge is input, and the remaining PMOSs 44 are not turned on. is there. In this case, the PMOS 44 cannot appropriately attenuate the VDD-SIG surge. In addition, a high current flows through the PMOS 44 that is turned on, and the PMOS 44 is easily damaged. Therefore, the protection circuit 24 d includes a current path that attenuates the VDD-SIG surge, in addition to the PMOS 44.
That is, when a VDD-SIG surge is input, the thyristor 48 (104, 106, 108, 110) is turned on and the diode 42 (100) is turned on. As a result, a current flows from the VDD wiring 22a to the signal wiring 22d along the path indicated by the arrow C1 in FIG. As a result, the VDD-SIG surge is attenuated. As described above, in the protection circuit 24d, when the VDD-SIG surge is applied, in addition to the path via the PMOS 44, the path C1 via the thyristor 48 (104, 106, 108, 110) and the diode 42 (100) also has VDD. A current flows from the wiring 22a to the signal wiring 22d. Therefore, even when the PMOS 44 is not properly turned on, the internal circuit 14 can be protected from the VDD-SIG surge.
As described above, when a VDD-SIG surge is input, the potential of the N-type well 50 decreases due to a voltage drop caused by the resistor 33. Thereby, the thyristor 48 (104, 106, 108, 110) is easily turned on. That is, the trigger voltage of the thyristor 48 (104, 106, 108, 110) is reduced by the resistor 33.
Further, as shown in FIG. 5, five thyristors 48, 104, 106, 108 and 110 are connected between the signal wiring 22d and the VDD wiring 22a. Therefore, a high current can flow from the VDD wiring 22a to the signal wiring 22d. As shown in FIG. 5, two diodes 42 and 100 are connected between the GND wiring 22b and the signal wiring 22d. Therefore, a high current can flow from the GND wiring 22b to the signal wiring 22d. That is, when a VDD-SIG surge is input, a high current can flow through the path C1 in FIG. Preferably, the SIG-VDD surge can be attenuated.

(Operation when SIG-GND surge is input)
When a SIG-GND surge is input to the signal wiring 22d, the NMOS 40 in FIG. 5 is turned on by a snapback phenomenon. As a result, a current flows from the signal wiring 22d to the GND wiring 22b, and the SIG-GND surge is attenuated.
The snapback phenomenon of the NMOS 40 is substantially the same as that of the PMOS 44. That is, first, a voltage substantially equal to a surge voltage (hereinafter referred to as voltage V2) is reversed at the PN junction (see FIG. 4) at the boundary between the P-type well 30 and the N-type drain region 32 by the input of the SIG-GND surge. Applied in the direction. At this stage, the current flowing from the signal wiring 22d to the GND wiring 22b (hereinafter referred to as current I2) is zero. When the voltage V2 rises to the avalanche voltage of the PN junction, the current I2 starts to flow through the N-type drain region 32 and the P-type well 30 (including the P-type well contact region 30a) due to avalanche breakdown. The current I2 flowing at this time flows to the P-type well 30 (including the P-type well contact region 30a) via the resistor 31 (the resistor 31a in FIG. 5). Therefore, due to the voltage drop in the resistor 31, the potential of the P-type well 30 becomes higher than the potential of the GND wiring 22b. When the current I2 flows in the P-type well 30, a potential distribution is generated in the P-type well 30 due to the electrical resistance in the P-type well 30. Therefore, when the current I2 increases, the potential of the P-type well 30 near the N-type source region 36 increases. Then, since the potential of the N-type source region 36 is substantially equal to that of the GND wiring 22b, a forward voltage is applied to the PN junction at the boundary between the N-type source region 36 and the P-type well 30. When the voltage V2 rises to the trigger voltage, the forward voltage applied to the PN junction becomes higher than the ON voltage of the PN junction, and the PN junction is turned on. That is, the NMOS 40 is turned on (snapback phenomenon). As a result, the current I2 flows from the signal wiring 22d to the GND wiring 22b via the NMOS 40, and the SIG-GND surge is attenuated. In the protection circuit 24d, the resistance of the N-type drain region 32 is increased by the high resistance region 32b. This suppresses the voltage V2 from rising after the NMOS 40 snaps back.

Note that the NMOS 40 described above has a problem that the trigger voltage is relatively high and it is difficult to turn on when a SIG-GND surge is input. As described above, a plurality of NMOSs 40 are formed in the NMOS region 38. However, there is a case in which only a part of the NMOSs 40 is turned on when the SIG-GND surge is input, and the remaining NMOSs 40 are not turned on. is there. Therefore, the protection circuit 24 d includes a current path that attenuates the SIG-GND surge, in addition to the NMOS 40.
That is, when a SIG-GND surge is input, the diode 46 (102) is turned on and the thyristor 48 (104, 106, 108, 110) is turned on. As a result, a current flows from the signal wiring 22d to the GND wiring 22b along the path indicated by the arrow C2 in FIG. As a result, the SIG-GND surge is attenuated. As described above, in the protection circuit 24d, when the SIG-GND surge is applied, in addition to the path through the NMOS 40, the signal is also transmitted through the path C2 through the diode 46 (102) and the thyristor 48 (104, 106, 108, 110). A current flows from the wiring 22d toward the GND wiring 22b. Therefore, even when the NMOS 40 is not properly turned on, the internal circuit 14 can be protected from the SIG-GND surge.
As described above, when a SIG-GND surge is input, the potential of the P-type well 30 rises due to a voltage drop due to the resistor 31. Thereby, the thyristor 48 (104, 106, 108, 110) is easily turned on. That is, the trigger voltage of the thyristor 48 (104, 106, 108, 110) is reduced by the resistor 31.
As described above, the VDD wiring 22a and the GND wiring 22b are connected by the five thyristors 48, 104, 106, 108, and 110. The GND wiring 22b and the signal wiring 22d are connected by two diodes 42 and 102. Therefore, a high current can be passed through the path C2 in FIG. 5 when a VDD-SIG surge is input. Preferably, the SIG-GND surge can be attenuated.

(Operation when GND-SIG surge is input)
When a GND-SIG surge is input to the signal wiring 22d, the diode 42 (100) in FIG. 5 is turned on. As a result, a current flows from the GND wiring 22b to the signal wiring 22d, and the GND-SIG surge is attenuated.
As described above, the GND wiring 22b and the signal wiring 22d are connected by the two diodes 42 and 102. Therefore, when a GND-SIG surge is input, a high current can flow from the GND wiring 22b toward the signal wiring 22d. A GND-SIG surge can be suitably attenuated.

  As described above, in the IC 10 of this embodiment, the protection circuit 24d includes the thyristors 48, 104, 106, 108, and 110 that connect the VDD wiring 22a and the GND wiring 22b. Therefore, the internal circuit 14 can be appropriately protected from VDD-SIG surge and SIG-GND.

  The thyristor 48 is formed using a PN junction at the boundary between the P-type well 30 and the N-type well 50. Further, an N-type cathode region 62 and a P-type anode region 64 are formed in a space near the boundary between the P-type well 30 and the N-type well 50. Therefore, the thyristor 48 can be formed without increasing the size of the protection circuit 24d.

  Further, in the IC 10 of this embodiment, the protection circuits 24c and 22e are adjacent to the protection circuit 24d in the Y direction, and the arrangement of the P-type well 30 and the N-type well 50 of the protection circuits 24c and 22e is protected. The circuit 24d is reversed. Therefore, a PN junction is formed at the boundary between the protection circuit 24d and the protection circuit 24c and at the boundary between the protection circuit 24d and the protection circuit 24e. The thyristors 104, 106, 108, and 110 are formed using the PN junction. Therefore, the thyristors 104, 106, 108, and 110 can be formed without increasing the size of the protection circuit 24d. By forming the thyristors 104, 106, 108, and 110, a high current can flow from the VDD wiring 22a to the GND wiring 22b.

  Further, in the IC 10 of this embodiment, as shown in FIG. 9, the N-type drain region 32 extends linearly in the X direction, and the P-type is located at a position overlapping the straight line extending the N-type drain region 32. A drain region 52 is formed. Further, an N-type cathode region 66 and a P-type anode region 68 are formed at a position overlapping with a straight line extending from the N-type drain region 32. Therefore, the N-type drain region 32, the P-type drain region 52, the N-type cathode region 66, and the P-type anode region 68 can be connected by the signal wiring 22d that extends linearly. The signal wiring 22d can be arranged efficiently. Further, since the N-type cathode region 66 and the P-type anode region 68 are formed in the space near the boundary between the P-type well 30 and the N-type well 50, the protection circuit 24d does not increase in size. In addition, by forming the N-type cathode region 66, a high current can flow from the GND wiring 22b to the signal wiring 22d. Further, by forming the P-type anode region 68, it is possible to cause a high current to flow from the VDD wiring 22a to the signal wiring 22d.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

The enlarged plan view of the upper surface of IC10 of an Example. The enlarged plan view of the upper surface of the semiconductor substrate 12 of the range in which the protection circuits 24c-24e are formed. The enlarged plan view of the upper surface of the protection circuit 24d. IV-IV sectional view taken on the line of FIG. The circuit diagram which shows the equivalent circuit of the protection circuit 24d. VI-VI sectional view taken on the line of FIG. VII-VII line sectional drawing of FIG. VIII-VIII sectional view taken on the line of FIG. It is an enlarged plan view of the upper surface of the protection circuit 24d, and is a diagram showing the arrangement of the signal wiring 22d. The top view which shows the boundary part of four wells. A graph explaining the snapback phenomenon. The top view of the conventional semiconductor device provided with the protection circuit. Sectional drawing of the conventional protection circuit. The circuit diagram which shows the equivalent circuit of the conventional protection circuit. 1 is a top view of a protection circuit of a semiconductor device of the present invention exemplified as a first example; FIG. 6 is a top view of a protection circuit for a semiconductor device according to the present invention, which is exemplified second. FIG. 6 is a top view of a protection circuit for a semiconductor device of the present invention, which is exemplified as a third example.

Explanation of symbols

10: IC
12: Semiconductor substrate 14: Internal circuit 22a: VDD wiring 22b: GND wiring 22d: Signal wiring 24a-24e: Protection circuit 30: P-type well 30a: P-type well contact region 32: N-type drain region 34: Gate electrode 35: Gate insulating film 36: N-type source region 38: NMOS region 50: N-type well 50a: N-type well contact region 52: P-type drain region 54: Gate electrode 56: P-type source region 58: PMOS region 62: N-type cathode Region 64: P-type anode region 66: N-type cathode region 68: P-type anode region 72: N-type cathode region 74: P-type anode region 78: N-type cathode region 80: P-type anode region 84: P-type anode region 86 : N-type cathode region 90: P-type anode region 92: N-type cathode region

Claims (3)

A high potential wiring to which a first potential is applied, a low potential wiring to which a second potential lower than the first potential is applied, and a first signal to which a signal potential that varies between the first potential and the second potential is applied. A semiconductor device comprising: a wiring; an internal circuit connected to a high potential wiring; a low potential wiring; and a first signal wiring; and a first protection circuit protecting the internal circuit from a surge input to the first signal wiring. There,
The first protection circuit faces the surface of the semiconductor substrate, faces the first P-type well connected to the low-potential wiring, and faces the surface of the semiconductor substrate, and is adjacent to the first P-type well. And a first N-type well connected to the high potential wiring,
The first P-type well faces the surface of the first P-type well, faces the N-type drain region connected to the first signal wiring, and the surface of the first P-type well, N An N-type source region isolated from the type drain region and connected to the low-potential wiring, and opposed to the surface of the first P-type well between the N-type drain region and the N-type source region via an insulating film A first NMOS region having a gate electrode connected to the low-potential wiring is formed;
The first N-type well faces the surface of the first N-type well, faces the P-type drain region connected to the first signal wiring, and the surface of the first N-type well, P A P-type source region that is isolated from the type drain region and connected to the high-potential wiring, and faces the surface of the first N-type well between the P-type drain region and the P-type source region via an insulating film And a first PMOS region having a gate electrode connected to the high potential wiring is formed,
The first P-type well in a range between the first NMOS region and the first N-type well faces the surface of the first P-type well and is separated from the first NMOS region and the first N-type well. A first N-type cathode region connected to the low-potential wiring is formed, and the first N-type well in a range sandwiched between the first PMOS region and the first P-type well includes the first N-type well A first P-type anode region is formed which is separated from the first PMOS region, the first P-type well, and the first N-type cathode region, and is connected to the high potential wiring.
A semiconductor device. A signal potential that varies between the first potential and the second potential is applied, a second signal wiring connected to the internal circuit, and a second signal line that protects the internal circuit from a surge input to the second signal wiring. 2 further includes a protection circuit,
The second protection circuit faces the surface of the semiconductor substrate, is adjacent to the first N-type well and is connected to the low-potential wiring, and faces the surface of the semiconductor substrate. A second N type well adjacent to the first P type well and the second P type well and connected to the high potential wiring;
The second P-type well faces the surface of the second P-type well, faces the N-type drain region connected to the second signal wiring, and the surface of the second P-type well, N An N-type source region isolated from the type drain region and connected to the low-potential wiring, and opposed to the surface of the second P-type well between the N-type drain region and the N-type source region via an insulating film A second NMOS region having a gate electrode connected to the low-potential wiring is formed,
The second N-type well faces the surface of the second N-type well, faces a P-type drain region connected to the second signal wiring, and the surface of the second N-type well, P A P-type source region which is isolated from the type drain region and is connected to the high-potential wiring, and faces the surface of the second N-type well between the P-type drain region and the P-type source region via an insulating film A second PMOS region having a gate electrode connected to the high-potential wiring is formed;
The second P-type well in a range sandwiched between the second NMOS region and the second N-type well faces the surface of the second P-type well and is separated from the second NMOS region and the second N-type well. A second N-type cathode region connected to the low-potential wiring is formed, and the second N-type well in a range sandwiched between the second PMOS region and the second P-type well includes the second N-type well A second P-type anode region is formed which is separated from the second PMOS region, the second P-type well, and the second N-type cathode region and connected to the high-potential wiring;
The first P-type well in a range sandwiched between the first NMOS region and the second N-type well faces the surface of the first P-type well and is separated from the first NMOS region and the second N-type well. A third N-type cathode region connected to the low-potential wiring is formed,
The second N-type well sandwiched between the second PMOS region and the first P-type well faces the surface of the second N-type well, and the second PMOS region, the first P-type well, and the third N-type well A third P-type anode region that is separated from the type cathode region and connected to the high-potential wiring is formed;
The first N-type well in a range sandwiched between the first PMOS region and the second P-type well faces the surface of the first N-type well and is separated from the first PMOS region and the second P-type well. A fourth P-type anode region connected to the high-potential wiring is formed, and the second P-type well in a range sandwiched between the second NMOS region and the first N-type well includes the second P-type well A fourth N-type cathode region is formed, which is separated from the second NMOS region, the first N-type well, and the fourth P-type anode region, and is connected to the low potential wiring.
The semiconductor device according to claim 1. A first signal line extending linearly on the semiconductor substrate and connecting at least one of the N-type drain region of the first NMOS region and at least one of the P-type drain region of the first PMOS region;
The first P-type well sandwiched between the first NMOS region and the first N-type well and facing the surface of the first P-type well in a range below the first signal wiring, A first N-type well, the first N-type cathode region, and the first P-type anode region are separated from each other, and a fifth N-type cathode region connected to the first signal wiring is formed. The first N-type well sandwiched between the first P-type well and the lower portion of the first signal wiring faces the surface of the first N-type well, and the first PMOS region, the first P-type well, A fifth P-type anode that is separated from the first P-type anode region, the first N-type cathode region, and the fifth N-type cathode region and is connected to the first signal line An area is formed,
The semiconductor device according to claim 1, wherein:

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