JP5297495B2 - Electrostatic discharge protection element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic discharge protection element that is excellent in both anti-ESD protection performance and latch-up resistance performance, and small in layout area. <P>SOLUTION: The electrostatic discharge protection element has: a first well of a first-conductivity type which is formed at a surface of a semiconductor substrate and rectangular viewed from a direction vertical to the surface of the semiconductor substrate; and a second well of a first-conductivity type which is formed to surround the first well of first-conductivity type at the surface of the semiconductor substrate, in contact with an end edge extended in a second direction perpendicular to a first direction at the first well of the first-conductivity type and not in contact with an end edge extended in the first direction, and to which reference potential is applied. The resistivity of a region between an end edge extended in the first direction of the first well of the first-conductivity type and the second well of the first-conductivity type is higher than the resistivity of the first and second wells of the first-conductivity type. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an electrostatic discharge protection element that is formed in a semiconductor integrated circuit and protects a circuit element from destruction due to electrostatic discharge, and more particularly to an electrostatic discharge protection element in which a plurality of MOS type protection elements are connected in parallel to each other.

  Recently, an electrostatic discharge protection element (hereinafter also referred to as an ESD (Electro Static Discharge) protection element) provided in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit is an ESD composed of a diode or a resistance element. The protection element has been replaced with a MOS type protection element utilizing parasitic bipolar operation with lower resistance and higher discharge capability. This MOS type protective element is a protective element that utilizes the snapback phenomenon of a MOSFET (MOS Field Effect Transistor).

  FIG. 12 is a circuit diagram showing a semiconductor device in which an ESD protection element is incorporated in an input circuit. As shown in FIG. 12, in this semiconductor device, an input buffer 101 of an internal circuit to be protected is provided, and an input pad 103 is connected to the input buffer 101 via a wiring 102. The input buffer 101 is connected to the power supply potential wiring VDD and the ground potential wiring GND. A primary protection element 104 and a secondary protection element 105 are connected in parallel to each other between the wiring 102 and the ground potential wiring GND. The primary protection element 104 and the secondary protection element 105 are ESD protection elements, respectively. The primary protection element 104 is connected to the input pad 103 side of the wiring 102, and the secondary protection element 105 is connected to the input buffer 101 side of the wiring 102. An input protection resistor 106 is provided between the connection point of the wiring 102 with the primary protection element 104 and the connection point of the secondary protection element 105.

  When a surge current such as an ESD current is input to the input pad 103 from the outside, the primary protection element 104 becomes low resistance, and most of the surge current is discharged to the ground potential wiring GND. In addition, the secondary discharge protection element 105 is disposed in the vicinity of the internal circuit to prevent an excessive voltage from being applied to the internal circuit.

  Next, the operation principle of the ESD protection element will be described. FIG. 13 is a cross-sectional view showing a MOS type ESD protection element. In FIG. 14, the horizontal axis represents the voltage applied to one finger of the ESD protection element, and the vertical axis represents the current flowing through this finger. It is a graph which shows operation | movement of a finger. As shown in FIG. 13, in the ESD protection element, a P well 113 is formed on the surface of a P type substrate 112 made of, for example, P type silicon. An STI (Shallow Trench Isolation) region 114 is selectively formed on the surface of the P well 113, and the surface of the P well 113 is partitioned into a plurality of regions.

A pair of N ⁺ regions are formed in one region on the surface of the P-well 113 so as to be separated from each other, and serve as a source region 115 and a drain region 116, respectively. The source region 115 is connected to the ground potential wiring GND, and the drain region 116 is connected to the input pad 103. Further, a region between the source region 115 and the drain region 116 is a channel region 117, and a gate oxide film (not shown) is interposed in the region directly above the channel region 117 on the P-type substrate 112. An electrode 118 is provided. One set of source region 115, drain region 116, channel region 117, gate oxide film and gate electrode 118 constitutes one MOSFET, and one MOSFET serves as one finger 111. In FIG. 13, only one finger is shown, but the MOS type ESD protection element has a plurality of fingers.

On the other hand, a P ⁺ region is formed in another region separated from the region where the source region 115 and the drain region 116 are formed (hereinafter also referred to as a transistor formation region) on the surface of the P well 113 by the STI region 114. It is a guard ring 119. A ground potential is applied to the guard ring 119.

  Hereinafter, the operation of the ESD protection element shown in FIG. 13 will be described. When a surge current flows into the drain region 116, the drain voltage increases. When the drain voltage becomes equal to or higher than the voltage Vt0 shown in FIG. 14, avalanche breakdown starts at the PN junction surface at the interface between the drain region 116 and the channel region 117, and electrons and holes are generated in pairs. Among these, the electrons are absorbed by the drain region 116. On the other hand, the hole becomes a substrate current and flows in the P well 103, and finally most reaches the guard ring 119.

  The element operation in this case can be described as an operation of a parasitic bipolar transistor in which the source region 115 is an emitter, the P-type substrate 112 including the guard ring 119 is a base, and the drain region 116 is a collector. That is, a potential difference corresponding to the product of this current and the resistance of the P-type substrate 112 is generated in the P-type substrate 112 due to the substrate current flowing in the P-type substrate 112, and near the bottom surface of the source region 115 in the P-type substrate 112. The potential rises with respect to the guard ring 119.

  Then, as shown in FIG. 14, when the voltage applied to the ESD protection element 111 reaches the voltage Vt1, the potential near the bottom surface of the source region 115 with respect to the guard ring 119 is changed at the interface between the source region 115 and the channel region 117. The degree of forward biasing the PN junction, for example, about 0.7V. Then, this PN junction is forward-biased to form a low-resistance current path from the drain region 116 to the source region 115. That is, the parasitic bipolar transistor described above becomes conductive and enters a low resistance state. This phenomenon is called snapback, and the voltage Vt1 is called snapback start voltage or trigger voltage. As a result of the snapback, a larger current flows between the drain region 116 and the source region 115, and the surge current input to the drain region 116 is applied to the ground potential wiring GND via the source region 115. It becomes possible to discharge. Even after the finger 111 of the ESD protection element snaps back, when the voltage applied to the finger 111 reaches the voltage Vt2, the destruction current It2 flows through the finger 111, and the finger 111 is destroyed.

  At this time, if the snapback start voltage Vt1 is too high, the current concentrates on a small number of fingers because all fingers do not turn on, and the ESD protection element itself may be destroyed, The circuit may be destroyed.

  For this reason, Patent Document 1 discloses a technique in which a P well block region in which no P well is formed is provided between a transistor formation region and a guard ring in an ESD protection element. FIG. 15 is a plan view showing the ESD protection element described in Patent Document 1. FIG. In FIG. 15, components corresponding to the components shown in FIG. 13 are denoted by the same reference numerals as those in FIG. 13, and detailed description thereof is omitted.

  As shown in FIG. 15, a P well 113 is formed on the surface of a P-type substrate 112 (see FIG. 13), and a source region 115 and a drain region 116 are formed on the surface of the P well 113 in a channel region 117 (FIG. 13). The gate electrode 118 is provided on the channel region 117. Note that contacts 120 are provided on the surfaces of the source region 115 and the drain region 116 to connect these regions to the upper wiring.

  A guard ring 119 is formed on the surface of the P well 113 so as to surround the transistor formation region in which the source region 115 and the drain region 116 are formed. Between the transistor formation region and the guard ring 119 on the surface of the P-type substrate 112, a P well block region 121 (or a low concentration N type region) where the P well 113 is not formed is formed so as to surround the transistor formation region. Is set. Thereby, the substrate resistance value between the transistor formation region and the guard ring 119 can be increased, and the snapback start voltage can be reduced. Note that an STI region 114 (see FIG. 13) is formed in a region between the transistor formation region and the guard ring 119 on the surface of the P-type substrate 112, but is not shown in FIG. 15 for convenience.

  On the other hand, an ESD protection element is often formed by a CMOS transistor in which a P-channel MOS transistor and an N-channel MOS transistor are formed close to each other and the drain regions of both MOS transistors are connected to a common wiring. That is, both the drain region of the ESD protection element made of a P-channel MOS transistor and the drain region of the ESD protection element made of an N-channel MOS transistor are connected to the wiring (for example, the wiring 112 shown in FIG. 13) connected to the internal circuit. Then, a power supply potential is applied to the source region of the P-type ESD protection element, and a ground potential is applied to the source region of the N-type ESD protection element.

FIG. 16 is a cross-sectional view showing an ESD protection circuit using CMOS transistors. FIG. 16 is a diagram schematically showing an electrical relationship between components in the ESD protection circuit, and the positional relationship of each component does not necessarily correspond to the cross section of the actual ESD protection circuit. . As shown in FIG. 16, a P-channel MOS transistor (PMOS) 132 and an N-channel MOS transistor (NMOS) 133 are formed on the surface of a P-type substrate 131. In the PMOS 132, an N well 134 is formed on the surface of a P-type substrate 131, and a P ⁺ region is formed on the surface of the N well 134, which serves as a source region 135. A drain region composed of a P ⁺ region is also formed on the surface of the N well 134, but it is not shown. A guard ring 136 made of an N ⁺ region is formed so as to surround the source region 135. The source region 135 and the guard ring 136 are connected to the power supply potential wiring VDD.

Similarly, in the NMOS 133, a P well 137 is formed, a source region 138 made of an N ⁺ region is formed on the surface of the P well 137, and a guard made of a P ⁺ region surrounds the source region 138. A ring 139 is formed. The source region 138 and the guard ring 139 are connected to the ground potential wiring GND. Thereby, an internal circuit can be protected from both a positive surge current and a negative surge current.

However, in a CMOS integrated circuit, PMOS and NMOS transistors are formed in the same substrate, so that a parasitic pnpn structure, that is, a thyristor structure is inevitably generated. That is, as shown as an equivalent circuit in FIG. 16, a parasitic bipolar transistor Q1 having a source region 135 (P ⁺ region) of PMOS 132 as an emitter, an N well 134 as a base, and a P type substrate 131 as a collector, and an N well 134 as a collector. As a result, a parasitic bipolar transistor Q2 having a P-type substrate 131 and a P-well 137 as a base and a source region 138 (N ⁺ region) as an emitter is generated. In the equivalent circuit shown in FIG. 16, the substrate resistance in the N well 134 is Rn1 to Rn4, the substrate resistance in the P well 137 is Rp1 to Rp4, the collector of the transistor Q1 in the P-type substrate 131, and the base of the transistor Q2 The substrate resistance between is represented by Rsub.

In the circuit shown in FIG. 16, for example, when carriers (electrons) are injected into the drain region (not shown) of the PMOS 132 from the outside, a part of this carrier is absorbed by the guard ring 136 which is the N ⁺ region. The carriers that cannot be absorbed by the guard ring 136 flow toward the source region 135 connected to the power supply potential wiring VDD. At this time, a potential drop corresponding to the product of the resistance value and the current value of the N well 134 occurs in the N well 134, and this potential drop occurs between the base (N well 134) and emitter (source region 135) of the transistor Q1. A bias is applied between them to turn on transistor Q1. Since the collector of the transistor Q1 and the base of the transistor Q2 are shared by the P-type substrate 131, when the transistor Q1 is turned on, the base potential of the transistor Q2 rises and the transistor Q2 is also turned on. As a result, the parasitic thyristor (pnpn structure) becomes conductive, and is composed of the power supply potential wiring VDD−source region 135 (P ⁺ region) −N well 134−P well 137−source region 138 (N ⁺ region) −ground potential wiring GND. A current path is formed, leading to latch-up.

  Latch-up may occur between CMOS internal circuits close to the input circuit or output circuit, or between peripheral circuits. In an actual integrated circuit, when a noise exceeding the maximum rating, a difference in power supply rise time at power start-up, power supply voltage fluctuation, ESD current, etc. is applied to the integrated circuit, the parasitic thyristor is triggered to enter a latch-up state. There are many cases. In the latch-up state, the resistance value between the power supply potential wiring and the ground potential wiring decreases, an excessive current flows between the two wirings, and in the worst case, the element may be destroyed.

  For example, Non-Patent Document 1 includes a photo emission photograph of a CMOS element at the time of latch-up. According to this, at the time of latch-up, the current is concentrated in the central portion of the element. This is considered to be because the base resistance of the central portion is the highest in the two bipolar transistors formed in the CMOS element.

  In order to prevent latch-up, it is effective to increase the distance between PMOS and NMOS to reduce the current amplification factor. In particular, it is safest to set the holding voltage at the time of latching to a voltage higher than the power supply voltage. However, this method has a problem that the layout area increases.

  In order to prevent latch-up, it is effective to make the substrate resistance as low as possible. As described above, the potential in the substrate changes according to the product of the magnitude of the current flowing in the substrate and the substrate resistance. Therefore, if the substrate resistance is lowered, the potential in the substrate is reduced even if current flows in the substrate. The change is small and the parasitic bipolar transistor becomes difficult to conduct. Therefore, the parasitic thyristor is difficult to conduct and latch-up is less likely to occur.

  However, as described above, when the substrate resistance is lowered, the snapback start voltage (voltage Vt1 shown in FIG. 14) of the ESD protection element is increased, and the protection performance against ESD is lowered. As described above, in the MOS type ESD protection element, the ESD protection performance and the latch-up resistance have a trade-off relationship with respect to the substrate resistance.

  Therefore, Patent Document 1 described above proposes a method for achieving both ESD protection performance and latch-up performance. FIG. 17 is a plan view showing another ESD protection element disclosed in Patent Document 1. In FIG. As shown in FIG. 17, in this conventional ESD protection element, a P well block region 121 is set only between a source region 115 and a guard ring 119 located at both ends of a transistor formation region, and a gate in the transistor formation region is formed. A P well block region is not set between the side 122 extending in the direction orthogonal to the direction in which the electrode 118 extends and the guard ring 119. Thereby, the substrate resistance between each finger of the ESD protection element and the guard ring can be reduced uniformly, and latch-up can be prevented.

Japanese Patent No. 3237110 (FIGS. 1 and 2)

Liao S., Niou C., Chien K., Guo A., Dong W., Huang C., "New observance and analysis of various guard-ring structures on latch-up hardness by backside photo emission image" Reliability Physics Symposium Proceedings , 2003 41st Annual. 2003 IEEE International, 30 March-4 April 2003, Pages: 92-98

  However, the conventional techniques described above have the following problems. In the method of surrounding the periphery of the transistor formation region as shown in FIG. 15 with the P well block region, the substrate resistance value between the transistor formation region and the guard ring (hereinafter also simply referred to as the substrate resistance value) is set to the P well block. Control is performed by adjusting the width of the region. Note that the width of the P well block region is controlled by the width of the mask when the impurity is implanted into the substrate, and the width of the mask is controlled by adjusting the exposure width when exposing the photoresist. Thereby, to some extent, the substrate resistance value can be set low by narrowing the exposure width. However, if the width of the P-well block region is reduced to a certain extent, impurities contained in the P-well on both sides of the P-well block region diffuse into the P-well block region, so that the P-well block region disappears. End up. For this reason, the width of the P-well block region cannot be controlled to a certain extent or less, and the substrate resistance value cannot be controlled to a certain extent or less. As a result, the balance between the ESD resistance and the latch-up resistance may not be optimized.

  In the method of setting the P well block region only between the source region and the guard ring at both ends of the transistor formation region as shown in FIG. 17, the direction orthogonal to the direction in which the gate electrode 118 extends in the transistor formation region. The substrate resistance value is controlled by adjusting the distance between the side 122 extending to the guard ring 119 and the guard ring 119. For this reason, in order to obtain a necessary substrate resistance value, it is necessary to increase the distance between the side 122 of the transistor formation region and the guard ring 119, which increases the layout area.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an electrostatic discharge protection element that is excellent in both ESD resistance and latch-up resistance and has a small layout area.

  The electrostatic discharge protection element according to the present invention includes a semiconductor substrate, a first first conductivity type well formed on the surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate, A plurality of first second conductivity type regions to which electrostatic discharge is input and a plurality of second second conductivity type regions to which a reference potential is applied are alternately and mutually formed on the surface of the first conductivity type well. Second conductivity type transistors spaced apart and arranged in a first direction, and formed on the surface of the semiconductor substrate so as to surround the first first conductivity type well, the first conductivity type well in the first first conductivity type well. A second first conductivity type well to which a reference potential is applied, which is in contact with an edge extending in a second direction orthogonal to one direction but not in contact with the edge extending in the first direction, An edge extending in the first direction of the first conductivity type well and the front Resistivity region between the second first-conductivity-type wells, being higher than the resistivity of said first and second first-conductivity-type well.

Another electrostatic discharge protection element according to the present invention includes a semiconductor substrate, a first first conductivity type well formed on the surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate, A second first conductivity type well that is formed on the surface of the semiconductor substrate so as to surround the first first conductivity type well and is spaced apart from the first first conductivity type well and to which a reference potential is applied; A plurality of first second conductivity type regions formed on the surface of the first first conductivity type well, to which electrostatic discharge is input, and a plurality of second second conductivity type regions to which a reference potential is applied are alternately arranged and Second conductivity type transistors formed apart from each other, a resistor provided on a part of the first first conductivity type well, and the resistor connected to the second first conductivity type well It has a wiring, the resistivity of the resistor, the first及It is higher than the resistivity of the second first-conductivity-type well.

  In the second conductivity type transistor, a plurality of the first and second second conductivity type regions are alternately arranged along the first direction, and the first second conductivity type region and the second conductivity type region are arranged. A plurality of gate electrodes provided above the region between the two second conductivity type regions, and the plurality of gate electrodes are connected to each other and a part thereof is the second first conductivity type well. It is preferable to have a resistor connected to.

  Thereby, when electrostatic discharge is input, the gate electrode potential of one finger can be made higher than the gate electrode potential of another finger. Thus, the one finger can be snapped back first, and then the other finger can be snapped back in a chain. As a result, the ESD protection performance is improved.

According to the present invention, it is possible to achieve both superior resistance to ESD protection performance and resistance to latch-up performance was, it is possible to reduce the layout area.

It is a top view which shows the ESD protection element which concerns on the 1st Embodiment of this invention. It is an equivalent circuit diagram which shows this ESD protection element. It is a top view which shows the ESD protection element which concerns on the modification of 1st Embodiment. It is a top view which shows the ESD protection element which concerns on the 2nd Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 3rd Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 4th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 5th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 6th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 7th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 8th Embodiment of this invention. It is a top view which shows the ESD protection element which concerns on the 9th Embodiment of this invention. It is a circuit diagram which shows the semiconductor device which incorporated the ESD protection element in the input circuit. It is sectional drawing which shows a MOS type ESD protection element. It is a graph which shows the operation | movement of each finger, taking the voltage applied to one finger of an ESD protection element on a horizontal axis, and taking the electric current which flows into this finger on a vertical axis | shaft. It is a top view which shows the ESD protection element described in patent document 1. It is sectional drawing which shows the ESD protection circuit by a CMOS transistor. It is a top view which shows the other ESD protection element disclosed by patent document 1. FIG.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1 is a plan view showing an ESD protection element according to this embodiment, and FIG. 2 is an equivalent circuit diagram showing the ESD protection element. As shown in FIG. 1, in the semiconductor device 1 of the present embodiment, a P-well 2 is formed on the surface of a P-type substrate made of, for example, P-type silicon, and viewed from a direction perpendicular to the surface of the P-type substrate. (Hereinafter referred to in plan view), an N well 3 is formed inside the P well 2.

An ESD protection element 4 is formed on the surface of the P well 2. In the ESD protection element 4, source regions 5 and drain regions 6 made of N ⁺ regions are formed alternately and spaced apart from each other on the surface of the P well 2. For example, four source regions 5 and three drain regions 6 are alternately arranged, and both ends of the arrangement are source regions 5. In plan view, the source region 5 and the drain region 6 are rectangular in shape, and their longitudinal directions are the same. A region between the source region 5 and the drain region 6 on the surface of the P well 2 is a channel region (not shown), and a gate electrode 7 is provided immediately above the channel region. An N channel MOS transistor structure is formed by one drain region 6, a channel region in contact with the drain region 6, and a source region 5 in contact with the channel region, forming one finger. In the ESD protection element 4, for example, six fingers are connected in parallel to each other. Note that the source region 5 or the drain region 6 is shared between two fingers adjacent to each other.

  The longitudinal direction of the gate electrode is the same as the longitudinal direction of the source region 5 and the drain region 6. Hereinafter, this direction is referred to as a gate direction. The direction orthogonal to the gate direction, that is, the arrangement direction of the source region 5, the drain region 6, and the channel region is referred to as a current direction. Further, a region where the source region 5, the drain region 6, and the channel region are formed is referred to as a transistor formation region 8.

  A plurality of contacts 9 are arranged in a line on the source region 5 and the drain region 6, respectively, and the source region 5 and the drain region 6 are connected to a wiring (not shown) provided in an upper layer. . A contact 9 is also formed between both ends of the gate electrode 7 and the P well 2. Further, a frame-like silicide block region 10 is set in a region surrounding the region where the contact 9 is formed on the surface of the drain region 6. Silicide is not formed in the silicide block region 10 on the surface of the drain region 6. On the other hand, silicide (not shown) is formed on the surface of the drain region 6 except the silicide block region 10, the surface of the source region 5, and the surface of the gate electrode 7.

  A P well block region 11 is set so as to surround the transistor formation region 8. In the P well block region 11, the P well 2 is not formed, and the STI region is formed on the surface of the P type substrate. For this reason, the resistivity of the P well block region 11 is higher than the resistivity of the P well 2.

  In plan view, the P-well block region 11 has a rectangular frame shape with one notch 11a, and the P-well 2 is formed in the notch 11a. The notch 11a is provided at a position separated in the gate direction when viewed from the drain region 6 located in the center of the transistor formation region 8 in the current direction. That is, the P well 2 formed in the notch 11 a forms a part of one edge of the P well 2 formed in the rectangular region surrounded by the P well block region 11 outside the P well block region 11. Connected to the P-well 2.

The width of the cut 11a, that is, the length in the current direction is shorter than the length of the drain region 6 in the current direction, for example. A frame-like guard ring 12 made of a P ⁺ region is formed in a region surrounding the P well block region 11 on the surface of the P well 2 so as to be separated from the P well block region 11. The impurity concentration in the guard ring 12 is higher than the impurity concentration in the P well 2.

Similarly, an ESD protection element 14 is formed on the surface of the N well 3. The ESD protection element 14 is provided on the side of the P well block region 11 where the notch 11a is provided as viewed from the ESD protection element 4. In the ESD protection element 14, the source region 15 and the drain region 16 made of a P ⁺ region are formed alternately and spaced apart from each other on the surface of the N well 3, and between the source region 15 and the drain region 16. This region is a channel region. A gate electrode 17 is provided immediately above the channel region. The longitudinal direction of the source region 15, the drain region 16, the channel region, and the gate electrode 17 in the ESD protection element 14 is the same direction as those in the ESD protection element 4 and is the gate direction.

Further, a plurality of contacts 9 are arranged in one row on the source region 15 and the drain region 16. A frame-shaped silicide block region 20 is set in a region surrounding the region where the contact 9 is formed on the surface of the drain region 16. A frame-shaped guard ring 22 made of an N ⁺ region is formed so as to surround the transistor formation region 18 in which the source region 15 and the drain region 16 in the ESD protection element 14 are formed. Other configurations of the ESD protection element 14 are the same as those of the ESD protection element 4. In addition, although STI regions are formed in regions other than the transistor formation regions 8 and 18 and the guard rings 12 and 22 on the surfaces of the P well 2 and the N well 3, the illustration is omitted in FIG. .

In the semiconductor device of this embodiment, an internal circuit (not shown) to be protected is formed on the surface of the P-type substrate, and the drain region 6 of the ESD protection element 4 and the drain region of the ESD protection element 14 16 is connected to this internal circuit. For example, the input buffer of the internal circuit is connected to the wiring 26 (see FIG. 2) that connects to the input pad 25 (see FIG. 2) of the semiconductor device. The source region 5 (N ⁺ region) of the ESD protection element 4 made of an NMOS transistor is connected to the ground potential wiring GND, and the source region 15 (P ⁺ region) of the ESD protection element 14 made of a PMOS transistor is a power supply potential. It is connected to wiring (not shown).

  FIG. 2 shows an equivalent circuit of the ESD protection element 4. As shown in FIG. 2, in the ESD protection element 4, six fingers F1 to F6 are connected in parallel to each other. In each finger, the silicide block region 10 is provided in the drain region 6, so that a drain resistance Rd is formed between the drain of each finger and the wiring 26. In FIG. 2, resistance values between the channel regions of the fingers are represented by substrate resistances Rsub1, Rsub1a, Rsub2, 3, Rsub2a, Rsub5a, Rsub4, 5, Rsub6a and Rsub6. For example, the channel region of the finger F1 and the channel region of the finger F2 are connected to each other via substrate resistances Rsub1, Rsub1a, Rsub2, 3, and the channel region of the finger F3 and the channel region of the finger F4 are The resistors Rsub2,3, Rsub2a, Rsub5a, Rsub4,5 are connected to each other.

  Further, since the P well block region 11 is provided between the transistor formation region 8 and the guard ring 12, the substrate resistance corresponding to the notch 11a is formed between the channel region of each finger and the ground potential wiring GND. Rsub is interposed, and the substrate resistance Rsub is connected to a connection point between the channel region of the finger F3 and the channel region of the finger F4. For this reason, the substrate resistance between the channel regions of the fingers F1 and F6 located at both ends of the transistor formation region 8 in the current direction and the ground potential wiring GND is relatively large, and is located in the center of the transistor formation region 8 in the current direction. The substrate resistance between the channel regions of the fingers F3 and F4 and the ground potential wiring GND is relatively small.

  Furthermore, the gate electrode 7 of each finger is connected to the P-well 2 via the contact 9, and the connection between the gate electrode 7 in the well 2 and the guard ring 12 is cut at the center in the current direction. A P well block region 11 in which 11a is formed is provided. Therefore, the resistance value between the gate electrode 7 of the fingers F2 to F5 and the ground potential wiring GND is extremely small, and the NMOS transistors constituting the fingers F2 to F5 are substantially gg-NMOS (gate-grounded-NMOS). However, for the fingers F1 and F6 at both ends, the resistance value between the gate electrode 7 and the ground potential wiring GND is higher than that of the fingers F2 to F5. In FIG. 2, this is represented by gate resistors Rg1 and Rg6 connected between the gate electrodes 7 of the fingers F1 and F6 and the ground potential wiring GND. The gate resistances Rg1 and Rg6 are, for example, 100Ω to 1kΩ.

  Next, the operation of the ESD protection element according to this embodiment will be described with reference to FIGS. For example, when a positive surge current is applied to the input pad 25 of the semiconductor device, this surge current is applied to the drain region 6 of the ESD protection element 4, and among the fingers F 1 to F 6 constituting the ESD protection element 4, Fingers F1 and F6 having a high substrate resistance snap back. Then, since the substrate current generated from the fingers F1 and F6 flows toward the notch 11a, this substrate current flows through the substrate portions of the fingers F2 and F3 and the fingers F5 and F4, and raises the substrate potential of these fingers. As a result, the fingers F2 and F5 whose substrate potential becomes higher next to the fingers F1 and F6 snap back, and then the fingers F3 and F4 snap back. In this way, all the fingers F1 to F6 constituting the ESD protection element 4 are snapped back sequentially from both ends of the transistor formation region 8 toward the center. Thereby, the ESD protection element 4 discharges the surge current to the ground potential wiring GND, and prevents the surge current from being input to the internal circuit. When a negative surge current is applied to the input pad 25, the ESD protection element 14 snaps back and discharges the surge current to the power supply potential wiring VDD.

  Next, the effect of this embodiment will be described. In the present embodiment, a P well block region 11 is provided in the ESD protection element 4, and one notch 11 a is provided in the central portion in the current direction of the portion extending in the current direction of the P well block region 11. . And the width | variety of the notch | incision 11a can be arbitrarily set so that the board | substrate resistance value which can balance ESD protection performance and latch-up performance optimally is implement | achieved. As a result, the substrate resistance value is optimally controlled without excessively reducing the width of the P-well block region 11 and without increasing the distance between the transistor formation region 8 and the guard ring 12, thereby improving the resistance. Both ESD protection performance and anti-latch-up performance can be achieved.

  Further, since the notch 11a is provided in the central portion in the current direction on the side facing the ESD protection element 14 in the P well block region 11, the substrate resistance of the finger located in the central portion in the current direction of the transistor formation region 8 is It can be made lower than the substrate resistance of the fingers located at both ends in the current direction. In particular, the resistance value between the P well 2 and the N well 3 in the central portion in the current direction can be reduced. Thereby, latch-up can be effectively prevented in the central portion of the transistor formation region 8 where latch-up is most likely to occur.

  Furthermore, since the substrate resistance of the fingers located at both ends in the current direction in the transistor formation region 8 is higher than the substrate resistance of the fingers located in the center portion, when the surge current is input to the ESD protection element 4, the both ends The finger located in the part is easy to snap back first. When the fingers located at both ends snap back, the substrate current flows toward the notch 11a and raises the substrate potential of the fingers located at the center, so that the fingers located at the center snap. Back. Thereby, all the fingers constituting the ESD protection element 4 sequentially snap back in a chain. As a result, all fingers can be snapped back reliably, and the ESD protection performance can be further improved. In order to obtain this effect, the width of the notch 11a is preferably small, and specifically, it is preferably smaller than the width of one drain region 6.

  Conventionally, as a method of chain-backing all fingers in an ESD protection element, the gate electrodes of the fingers are connected to each other, and a gate resistance is provided between the gate electrode and a reference potential wiring (for example, ground potential wiring). The method is known. Hereinafter, this effect will be described. When a surge current flows into the ESD protection element, the potentials of the drain regions of all fingers rapidly increase. Since the drain region and the gate electrode are coupled to each other via a parasitic capacitance, when the drain potential increases, the gate potential also increases. At this time, if a resistance element of about several k to several tens of kΩ is connected between the gate electrode and the reference potential wiring, the gate potential of all fingers rises almost simultaneously, and current flows in the channel regions of all fingers. Flows almost uniformly, so that avalanche breakdown occurs almost simultaneously, ensuring that all fingers snap back.

  However, when such an ESD protection element is applied to a high-frequency circuit, the rise time of the input signal is extremely short in the high-frequency circuit, so that the transition current flowing through the gate electrode at the time of signal rise is large, and the potential rise of the gate electrode is large. Leakage current due to potential rise increases. For this reason, an ESD protection element provided with a gate resistance is not suitable as an ESD protection element to be incorporated in a high-frequency circuit, and an gg-MOS ESD protection element in which the potential of the gate electrode is fixed is suitable. The resistance to be connected is preferably at most 1 kΩ. However, conversely, when the resistance value connected to the gate electrode is lowered, avalanche breakdown is likely to occur in a specific finger or a specific region such as a region where the electric field is strong in the specific finger, and each finger snaps. The back timing is likely to shift, making it difficult to snap back all fingers.

  On the other hand, in the present embodiment, as described above, by forming the notch 11a in the P well block region 11 to realize chained snapback of fingers, it is necessary to provide a gate resistance. In addition, the resistance value connected to the gate electrode can be sufficiently low, and in some cases, the ESD protection element can be formed by gg-MOS. For this reason, even when applied to a high frequency circuit, the ESD protection performance can be improved without degrading the high frequency characteristics.

  In the present embodiment, an example in which the STI region is formed in the P well block region 11 is shown, but the present invention is not limited to this, and the P well block region 11 may be a high resistance region, For example, a reverse conductivity type region, that is, an N-type region may be formed.

Next, a modification of the first embodiment will be described. FIG. 3 is a plan view showing an ESD protection element according to this modification. As shown in FIG. 3, in this modification, the guard ring 12 made of the P ⁺ region has a frame-shaped portion 12a and an extension extending from the frame-shaped portion 12a into the notch 11a of the P-well block region 11. It is comprised from the output part 12b. The configuration other than the above in the present modification is the same as that in the first embodiment.

  In this modification, the substrate resistance between the transistor formation region 8 and the guard ring 12 can be further reduced as compared with the first embodiment described above. For this reason, the width | variety of the notch | incision 11a can be made smaller, and the effect of chain-snapping back all the above-mentioned fingers can be increased further. Further, the substrate resistance can be adjusted by changing the extension length of the extension part 12b. Operations and effects other than those described above in the present modification are the same as those in the first embodiment described above.

  Next, a second embodiment of the present invention will be described. FIG. 4 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 4, in this embodiment, two cuts 11 a and 11 b are provided in the P well block region 11 of the ESD protection element 4. That is, the notch 11b is provided on the opposite side of the notch 11a provided on the side facing the ESD protection element 14 (see FIG. 1) made of PMOS. A P well 2 is formed inside the notches 11a and 11b.

  In the ESD protection element 4, six source regions 5 and five drain regions 6 are formed, thereby forming ten fingers. The P well 2 is not formed at the center of each source region 5 and each drain region 6, and the P well 2 is formed only at the periphery of each source region 5 and each drain region 6 and the channel region. Yes. Specifically, P wells 2 are formed in the regions at both ends in the current direction in the source region 5 and the drain region 6, that is, in the region in contact with the channel region. The width of this region, that is, the length in the current direction is, for example, 0.3 μm. A P well 2 is also formed in the peripheral portion of the transistor formation region 8. The width of this peripheral portion is, for example, 1 to 2 μm.

  Further, in this embodiment, no silicide block region is provided, and silicide (not shown) is formed on the entire surface of the source region and the drain region. Other configurations in the present embodiment are the same as those in the first embodiment.

  In the first embodiment described above, the notch 11 a is provided only on one side of the transistor formation region 8. However, in this case, snapback is likely to occur at the end of each finger where the notch 11a is formed, current is concentrated at this end, thermal runaway occurs, and the ESD protection element is destroyed. There is a possibility. On the other hand, in the present embodiment, since two cuts 11a and 11b are provided at positions opposite to each other in the P well block region 11, each finger is formed mainly from the center portion of the transistor. Snapback tends to occur toward both ends in the width direction (gate direction). Thereby, it can suppress that an electric current concentrates on the side edge part (gate direction both ends) of a transistor, and can prevent thermal runaway.

  In the present embodiment, since the P well 2 is not formed in the center of each source region 5 and each drain region 6, the substrate resistance in the transistor formation region 8 is compared with the first embodiment described above. , The chain reaction of snapback is more likely to occur, and the protection performance against ESD is further improved. When a parasitic thyristor is formed in a semiconductor substrate, a current flowing in the thyristor flows mainly between end portions of the diffusion layer. In general, the electric field is strong at the end of the diffusion layer. For this reason, the current amplification factor of the bipolar transistor may be increased by a strong electric field at the end of the diffusion layer. In the present embodiment, in consideration of this point, the P well 2 is formed in the peripheral portion of the transistor formation region 8, and the substrate resistance in the peripheral portion is lowered to prevent latch-up.

  Next, a third embodiment of the present invention will be described. FIG. 5 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 5, in the present embodiment, no cut is provided in the P well block region 11 of the ESD protection element 4. Instead, a resistor 31 made of polysilicon is provided above the portion of the P-well block region 11 that faces the ESD protection element 14 (see FIG. 1). The resistor 31 is formed in the same process as the gate electrode 7, for example. Two upper layer wirings 32 that extend to above the guard ring 12 are provided above both ends of the resistor 31. A contact 33 is provided between the guard ring 12 and the upper layer wiring 32 and between the resistor 31 and the upper layer wiring 32. The guard ring 12 is connected to the upper layer wiring 32, and the upper layer wiring 32 is connected to the resistor 31. Connected.

A plurality of P ⁺ regions 34 are formed so as to correspond to the source regions 5 and the drain regions 6 in a portion facing the resistor 31 in a region between the P well block region 11 and the transistor formation region 8. Has been. The plurality of P ⁺ regions 34 are arranged in a line in the current direction. A T-shaped upper layer wiring 35 is provided so as to extend from above the P ⁺ region 34 to above the central portion of the resistor 31. Further, a contact 33 is provided between the P ⁺ region 34 and the upper layer wiring 35, and between the resistor 31 and the upper layer wiring 35, and the resistor 31 is connected to the upper layer wiring 35. Is connected to the P ⁺ region 34. As a result, the P well 2 located inside the P well block region 11 passes through the P ⁺ region 34, the contact 33, the upper layer wiring 35, the contact 33, the resistor 31, the contact 33, the upper layer wiring 32, and the contact 33. It is connected to the guard ring 12.

  In the present embodiment, the same effect as in the first embodiment can be obtained by providing the resistor 31, the upper layer wirings 32 and 35, and the contact 33 in place of the notch 11a in the first embodiment. Yes. Thereby, in this embodiment, the substrate resistance can be controlled by adjusting the resistance value of the resistor 31. For this reason, in some cases, the substrate resistance can be adjusted with higher precision than providing the notch 11a in the P-well block region 11. The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

  Next, a fourth embodiment of the present invention will be described. FIG. 6 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 6, in this embodiment, in the P well block region 11, a total of four cuts 11c to 11f are provided at two positions on one side at positions corresponding to both sides in the current direction when viewed from the transistor formation region 8. Is provided. That is, the cuts 11c and 11d are provided apart from each other on one side in the current direction when viewed from the transistor formation region 8, and the cuts 11e and 11f are provided apart from each other on the other side. It has been. The position of the cut 11c in the gate direction is equal to the position of the cut 11e in the gate direction, and the position of the cut 11d in the gate direction is equal to the position of the cut 11f in the gate direction. In the P well block region 11, no cut is provided at a position corresponding to the gate direction when viewed from the transistor formation region 8. A P well 2 is formed in the notches 11c to 11f. Other configurations in the present embodiment are the same as those in the second embodiment described above.

  Next, the operation of this embodiment will be described. In the present embodiment, the substrate resistance between the current direction central portion and the guard ring 12 in the transistor formation region 8 is higher than the substrate resistance between the current direction both ends and the guard ring 12. For this reason, when a surge current is applied to the ESD protection element 4, the finger located at the center in the current direction of the transistor formation region 8 first snaps back. Then, the substrate current generated from the finger located at the center flows in the transistor forming region 8 on both sides in the current direction, and each finger is directed from the finger adjacent to the finger snapped back to the finger located at both ends. And then snap back. Operations other than those described above in the present embodiment are the same as those in the second embodiment described above.

  In the present embodiment, since the substrate current can flow in the current direction, that is, the finger arrangement direction, a chain of snapbacks can be generated more reliably. The effects of the present embodiment other than those described above are the same as those of the second embodiment described above.

  In this embodiment, the ESD protection element 14 made of PMOS (see FIG. 1) may be arranged in a region separated in the gate direction as viewed from the ESD protection element 4 made of NMOS, but in the current direction. You may arrange | position in the position spaced apart. Further, the ESD protection element 14 may not be provided.

  Next, a fifth embodiment of the present invention will be described. FIG. 7 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 7, in the present embodiment, as in the above-described fourth embodiment, notches are provided at positions corresponding to both sides in the current direction when viewed from the transistor formation region 8 in the P well block region 11. However, unlike the fourth embodiment, a total of 14 notches 11g are provided on each side, 7 locations. Similarly to the first embodiment described above, the ESD protection element 4 includes six fingers, and the P well 2 is provided in the entire source region 5 and drain region 6, so that the drain region 6 is provided with a silicide block region 10. Note that the sheet resistance of the portion where the STI region (not shown) is provided on the surface of the P well 2 is about 1 kΩ, for example, and the sheet resistance in the silicide block region 10 of the drain region 6 is about 200Ω, for example. Other configurations in the present embodiment are the same as those in the fourth embodiment described above.

  In the present embodiment, the substrate current can be made to flow uniformly in the gate direction as compared with the fourth embodiment described above. Thereby, snapback occurs uniformly in each finger, and the ESD protection performance is further improved. Operations and effects other than those described above in the present embodiment are the same as those in the above-described fourth embodiment.

  Next, a sixth embodiment of the present invention will be described. FIG. 8 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 8, in the present embodiment, in the ESD protection element 4, P well block regions 11 are provided only on both sides in the gate direction when viewed from the transistor formation region 8, and P well blocks are provided on both sides in the current direction. The region 11 is not provided. Compared with the fourth embodiment described above, the distance between the guard ring 12 and both ends of the transistor formation region 8 in the current direction is shorter. Other configurations in the present embodiment are the same as those in the fourth embodiment described above.

  In the present embodiment, by not providing the P well block regions 11 on both sides in the current direction as viewed from the transistor formation region 8, the substrate resistance of the entire transistor formation region 8 is reduced, and latch-up is less likely to occur. The layout area can be reduced by shortening the length of the protection element 4 in the current direction.

  Then, in order to compensate for the decrease in the ESD protection performance accompanying the decrease in the substrate resistance, the substrate resistance of the transistor formation region 8 is increased by not forming the P well 2 in the center of each source region 5 and each drain region 6. Thus, the snapback start voltage is reduced. Further, by providing the P-well block regions 11 on both sides in the gate direction as viewed from the transistor formation region 8, the substrate current is suppressed from flowing in the gate direction and flows in the current direction, so that the snapback chain phenomenon is more reliably performed. Is generated. As a result, both the ESD protection performance and the latch-up performance can be achieved, and the layout area can be reduced.

  Further, in this embodiment, the length D shown in FIG. 8, that is, the gate direction edge of the region where the P well 2 is not formed in the source region 5 located at both ends of the transistor forming region 8 in the current direction and the transistor By adjusting the distance between the edge of the formation region 8 in the gate direction, the substrate resistance value of the entire transistor formation region 8 can be adjusted. Operations and effects other than those described above in the present embodiment are the same as those in the above-described fourth embodiment.

  Next, a seventh embodiment of the present invention will be described. FIG. 9 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 9, in the present embodiment, compared with the fourth embodiment described above, the transistor formation region 8 is a region surrounded by the guard ring 12 and outside the transistor formation region 8. Resistors 41 made of polysilicon, for example, are provided at positions separated on both sides in the gate direction. The resistors 41 are provided on the P-type substrate, and two resistors 41 are provided, one on each side in the gate direction of the transistor formation region 8. The shape of the resistor 41 is a straight line extending in the current direction, and the length in the current direction is substantially equal to the distance between the gate electrodes 7 located at both ends in the current direction. The resistance value of the entire length of the resistor 41 in the current direction is, for example, 200 to 1000Ω. The resistor 41 is formed, for example, in the same process as the gate electrode 7, and silicide (not shown) is formed on the upper surface thereof.

  In addition, a plurality of vias 42 are provided on the resistor 41, and an upper layer wiring 43 as many as the gate electrode 7 is provided thereon, and is connected to the resistor 41 via the vias 42. . The upper layer wiring 43 extends from a region directly above the resistor 41 to a region directly above the end of each gate electrode 7. A via 44 is provided on the end of the gate electrode 7, and the gate electrode 7 is connected to the upper wiring 43 through the via 44. Further, the upper layer wiring 43 connected to the gate electrodes 7 at both ends in the current direction in the transistor formation region 8 extends in the current direction and reaches the region directly above the guard ring 12. A contact 45 is provided between the upper layer wiring 43 and the guard ring 12, and the upper layer wiring 43 is connected to the guard ring 12 through the contact 45.

  For this reason, the shape of the upper layer wiring 43 arranged at both ends extends from the region directly above the resistor 41 to the region directly above the end of the gate electrode 7 in the plan view and directly above the guard ring 12. It has an L shape extending in the current direction up to the region. Further, the shape of the upper layer wiring 43 other than this is a rectangular shape extending in the gate direction from the region directly above the resistor 41 to the region directly above the end of the gate electrode 7. As a result, the gate electrodes 7 are connected to each other through the resistor 41, the vias 42 and 44, the contact 45, and the upper layer wiring 43, and are also connected to the ground potential wiring through the guard ring 12. At this time, the resistance value between the gate electrodes 7 adjacent to each other is, for example, about 100Ω. Other configurations in the present embodiment are the same as those in the fourth embodiment described above.

  Next, the operation of this embodiment will be described. In the present embodiment, the gate electrodes 7 are connected to each other via the resistor 41, and the gate electrodes 7 at both ends in the current direction are connected to the guard ring 12. Thereby, the resistance value between the gate electrode 7 located at both ends in the current direction and the guard ring 12 is extremely low, and the resistance value between the guard ring 12 is higher in the gate electrode 7 closer to the center in the current direction, The resistance value between the gate electrode 7 and the guard ring 12 located at the center in the current direction is the highest. In each finger, the gate electrode 7 and the drain region 6 are capacitively coupled by a parasitic capacitance formed therebetween.

  For this reason, when a surge current is input to the drain region 6 of each finger, the potential of the gate electrode 7 rises due to capacitive coupling, but the gate electrode 7 located at the center in the current direction of the transistor formation region 8 is connected to the guard ring 12. Since the resistance value between them is the highest, the potential of the gate electrode 7 becomes the highest. Then, the potential of the gate electrode 7 adjacent to the gate electrode 7 located in the central portion becomes higher next to the potential of the gate electrode 7 in the central portion, and the potential of the gate electrode 7 closer to both ends becomes lower. In the NMOS transistor, the higher the potential of the gate electrode 7 is, the easier it is to conduct. For this reason, the finger closer to the center in the current direction is more likely to snap back when combined with the effect that the substrate resistance becomes higher and snapback becomes easier. Then, the fingers snap back in a chain toward both ends.

  Next, the effect of this embodiment will be described. In the above-described fourth embodiment, it is designed to snap back in order from the central finger having the highest substrate resistance, but when the substrate resistance is small between the fingers and when the characteristics of each finger vary. Does not necessarily mean that the finger located in the center will snap back first. On the other hand, according to the present embodiment, the finger that snaps back first can be reliably identified by making a difference in resistance value between the gate electrode and the guard ring between the fingers. Specifically, the resistance value between the gate electrode and the guard ring in the finger located in the middle portion in the current direction in the transistor formation region 8 is higher than that in the other fingers, thereby being located in this middle portion. The fingers can be reliably snapped back first. As a result, the chain phenomenon of snapback can be generated stably, and the ESD protection performance is stabilized.

  Next, an eighth embodiment of the present invention will be described. FIG. 10 is a plan view showing the ESD protection element according to this embodiment. As shown in FIG. 10, in this embodiment, compared with the first embodiment described above, the region surrounded by the guard ring 12 and from the transistor formation region 8 in the region outside the transistor formation region 8. Resistors 51 made of polysilicon, for example, are provided at positions separated on both sides in the gate direction. Two resistors 51 are provided on the P-type substrate, one on each side of the transistor formation region 8 in the gate direction. The shape of the resistor 51 is a straight line extending in the current direction, and the length in the current direction is substantially equal to the distance between the gate electrodes 7 located at both ends in the current direction. The resistance value of the entire length of the resistor 51 in the current direction is, for example, 200 to 1000Ω. The resistor 51 is formed in the same process as the gate electrode 7, for example.

  A plurality of vias 52 are provided on the resistor 51, and the same number of source regions 5 as that of the one resistor 51, that is, four upper wirings 53 are provided thereon. The resistor 51 is connected via the via 52. On the upper surface of the resistor 51, the silicide 57 is formed only in the region where the via 52 is formed, and the silicide 57 is not formed in the region therebetween. The resistance value of the portion of the resistor 51 where the silicide 57 is not formed is about several kΩ or less. The upper layer wiring 53 extends from a region directly above the resistor 51 to a region directly above the end of each gate electrode 7. A via 54 is provided on the end of the gate electrode 7, and the gate electrode 7 is connected to the upper layer wiring 53 through the via 54. At this time, the gate electrode 7 of the finger F1 is connected to the first upper layer wiring 53, the gate electrodes 7 of the fingers F2 and F3 are connected to the second upper layer wiring 53 in common, and the fingers F4 and F5 are connected. The gate electrode 7 of the finger F6 is connected in common to the third upper layer wiring 53, and the gate electrode 7 of the finger F6 is connected to the fourth upper layer wiring 53.

  Furthermore, an upper layer wiring 56 extending in the gate direction from a region directly above the central portion in the current direction of the resistor 51 to a region directly above the guard ring 12 is provided. A contact 55 is provided between the upper layer wiring 56 and the guard ring 12, and the upper layer wiring 56 is connected to the guard ring 12 through the contact 55. The shapes of the upper layer wirings 53 and 56 are rectangular shapes extending in the gate direction in plan view.

  As a result, the gate electrodes 7 are connected to each other through the resistor 51, the vias 52 and 54, and the upper layer wiring 53. At this time, the resistance value between the gate electrodes 7 adjacent to each other is, for example, about 100Ω. Further, the central portion of the resistor 51 in the current direction is connected to the guard ring 12 through the via 52, the upper layer wiring 56, and the contact 55, and further connected to the ground potential wiring through the guard ring 12. Other configurations in the present embodiment are the same as those in the first embodiment.

  Next, the operation of this embodiment will be described. In the present embodiment, the gate electrodes 7 are connected to each other via the resistor 51, and the central portion in the current direction of the resistor 51 is connected to the guard ring 12. Thereby, the resistance value between the gate electrode 7 and the guard ring 12 positioned at the center in the current direction is extremely low, and the resistance value between the guard ring 12 and the gate electrode 7 closer to both ends in the current direction becomes higher. The resistance value between the gate electrode 7 located at both ends in the current direction and the guard ring 12 is the highest. In each finger, the gate electrode 7 and the drain region 6 are capacitively coupled by a parasitic capacitance formed therebetween.

  For this reason, when a surge current is input to the drain region 6 of each finger, the potential of the gate electrode 7 rises due to capacitive coupling, but the gate electrode 7 located at both ends in the current direction of the transistor formation region 8 is connected to the guard ring 12. Since the resistance value between them is the highest, the potential of the gate electrode 7 becomes the highest. Then, the potential of the gate electrode 7 adjacent to the gate electrode 7 located at both ends becomes higher next to the potential of the gate electrode 7 at both ends, and the potential of the gate electrode 7 closer to the center becomes lower. In the NMOS transistor, the higher the potential of the gate electrode 7, the easier it is to conduct. For this reason, in combination with the effect that the finger closer to both ends in the current direction described in the first embodiment has a higher substrate resistance and is easy to snap back, when surge current is input, The fingers that are positioned surely snap back, and then the fingers snap back in a chain toward the center.

  Next, the effect of this embodiment will be described. In the present embodiment, as in the first embodiment described above, the substrate resistance of the fingers at both ends is higher than the substrate resistance of the other fingers. In addition, in this embodiment, the resistance value between the gate electrode and the guard ring in the fingers at both ends is higher than that of the other fingers. For this reason, the finger located in both ends can be snapped back more reliably first. As a result, the chain phenomenon of snapback can be generated stably, and the ESD protection performance is stabilized.

  Next, a ninth embodiment of the present invention will be described. FIG. 11 is a plan view showing an ESD protection element according to this embodiment. As shown in FIG. 11, in this embodiment, as compared with the first embodiment, a source per side is formed in a portion corresponding to both sides in the gate direction when viewed from the transistor formation region 8 in the P well block region 11. The same number of areas 5, that is, four cuts 11h are provided. That is, the P well block region 11 is provided with a total of eight cuts 11h. Each notch 11h is provided at a position corresponding to both sides in the gate direction when viewed from each source region 5. Other configurations in the present embodiment are the same as those in the first embodiment.

  In this embodiment, the number of cuts 11h formed on one side in the gate direction is made equal to the number of source regions 5, and the position of each cut 11h corresponds to the gate direction when viewed from the source region 5. The position. As a result, a pair of cuts 11h correspond to one finger regardless of the number of fingers constituting the ESD protection element. The width of 11h may be determined. As a result, even if the number of fingers provided in the ESD protection element 4 changes, the number of cuts 11h also changes accordingly. Therefore, it is necessary to readjust the width of each cut 11h according to the number of fingers. Absent. For this reason, the ESD protection element according to the present embodiment is easy to design.

  Note that, in the present embodiment, unlike the first embodiment described above, the effect of causing the fingers to snap back in a chain is reduced by flowing the substrate current in the current direction. However, by connecting the gate electrodes of each finger to each other and providing a resistance between the gate electrode and the ground potential wiring, the substrate resistance value of each finger can be set to be high to some extent. Snapback can be ensured. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

  In each of the above-described embodiments or modifications thereof, an example in which the ESD protection element 14 made of PMOS is provided in a region adjacent to the gate direction when viewed from the ESD protection element 4 made of an NMOS transistor has been described. The ESD protection element 14 may be provided in a region adjacent to the current direction when viewed from the ESD protection element 4, or the ESD protection element 14 may not be provided. Even in this case, it is possible to prevent latch-up from occurring with a PMOS transistor that is a part of the internal circuit element and is formed in a region close to the ESD protection element 4.

  Moreover, you may combine several embodiment or modification among each above-mentioned embodiment or its modification. For example, in the above-described second, fourth, fifth, seventh, eighth, and ninth embodiments, a guard ring is formed inside the notch of the P well block region as in the modification of the first embodiment. May be extended.

  Further, in each of the above-described embodiments or modifications thereof, the number of fingers constituting the ESD protection element is not limited to the number shown in the drawings. For example, in the ESD protection elements 4 and 14 shown in FIG. 1, four source regions 5 and three drain regions 6 are alternately formed to form six fingers. (N is a natural number) drain regions and (N + 1) source regions may be alternately arranged via a channel region to form 2N fingers.

  Furthermore, the electrostatic discharge protection element according to the present invention is not limited to a MOS transistor type electrostatic discharge protection element, and can be applied to, for example, a MOS transistor provided in a trigger circuit that triggers a thyristor type electrostatic discharge protection element. . An analog circuit having a P-well block region in the guard ring to isolate the internal circuit from power supply noise and the like uses the same structure as the electrostatic discharge protection element of the present invention in order to adjust the substrate resistance. can do.

(Appendix 1)
This application is a divisional application of Japanese Patent Application No. 2004-176237. The invention described in the claims at the beginning of the filing of this Japanese Patent Application No. 2004-176237 will be added. The embodiments described above are also embodiments of the invention described in the following claims.
(Claim 1)
A semiconductor substrate, a first first conductivity type well formed on the surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate, and the first first conductivity on the surface of the semiconductor substrate A second first conductivity type well that is formed apart from the first first conductivity type well so as to surround the type well and to which a reference potential is applied, and is formed on the surface of the first first conductivity type well. A second conductivity type transistor in which a first second conductivity type region to which electrostatic discharge is input and a second second conductivity type region to which a reference potential is applied is formed apart from each other; A part of at least one edge of the first first conductivity type well provided between the first conductivity type well and the second first conductivity type well is connected to the second first conductivity type well. A first well of the first conductivity type, and the first first conductivity type. Of the region between the well and the second first conductivity type well, the resistivity of the region excluding the third first conductivity type well is the resistivity of the first to third conductivity type wells. Electrostatic discharge protection element characterized by being higher than.
(Claim 2)
The length of the third first conductivity type well in a direction perpendicular to the direction from the connection portion with the first first conductivity type well to the connection portion with the second first conductivity type well is The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is smaller than a length of the first second conductivity type region in the orthogonal direction.
(Claim 3)
In the second conductivity type transistor, a plurality of the first and second second conductivity type regions are alternately arranged along the first direction, and the third first conductivity type well is the first conductivity type well. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is connected to an edge of the first conductivity type well extending in the first direction.
(Claim 4)
The electrostatic discharge protection element according to claim 3, wherein the third first conductivity type well is connected to a central portion of the edge in the first direction.
(Claim 5)
The third first conductivity type well is connected to a position corresponding to a second direction orthogonal to the first direction when viewed from the second second conductivity type region at the edge. The electrostatic discharge protection element according to claim 3.
(Claim 6)
In the second conductivity type transistor, a plurality of the first and second second conductivity type regions are alternately arranged along the first direction, and the third first conductivity type well is the first conductivity type well. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is connected to an edge of the first conductivity type well extending in a second direction orthogonal to the first direction.
(Claim 7)
A first conductivity type guard ring, the impurity concentration of which is higher than the impurity concentration of the second first conductivity type well, is applied to the surface of the second first conductivity type well. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is formed so as to surround one first conductivity type well.
(Claim 8)
8. The electrostatic discharge protection element according to claim 7, wherein the guard ring extends into the third first conductivity type well.
(Claim 9)
9. The region according to claim 1, wherein a region in which the first first conductivity type well is not formed is provided in the first and second second conductivity type regions. The electrostatic discharge protection element of description.
(Claim 10)
The impurity concentration of the first first conductivity type well, the impurity concentration of the second first conductivity type well, and the impurity concentration of the third first conductivity type well are mutually equal. The electrostatic discharge protection element according to claim 1.
(Claim 11)
The substrate current of one transistor composed of one first second conductivity type region and the second second conductivity type region adjacent to the first first conductivity type region is the other current in the semiconductor substrate. The electrostatic discharge protection element according to claim 3, wherein the electrostatic discharge protection element passes through a region directly under the transistor.
(Claim 12)
12. The shape and position of the third first conductivity type well are adjusted so that the substrate resistance of the second conductivity type transistor has a desired distribution. The electrostatic discharge protection element according to item 1.
(Claim 13)
A semiconductor substrate, a first first conductivity type well formed on the surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate, and formed on the surface of the first first conductivity type well The plurality of first second conductivity type regions to which electrostatic discharge is input and the plurality of second second conductivity type regions to which the reference potential is applied are arranged in the first direction alternately and spaced apart from each other. A second conductivity type transistor, formed on the surface of the semiconductor substrate so as to surround the first first conductivity type well, and extending in a second direction perpendicular to the first direction of the first first conductivity type well; And a second first conductivity type well to which a reference potential is applied without contacting an edge extending in the first direction and in contact with the edge, and the first conductivity type well of the first first conductivity type well. A region between an edge extending in one direction and the second first conductivity type well The resistivity of said first and second electrostatic discharge protection device being higher than the resistivity of the first conductive type well.
(Claim 14)
A semiconductor substrate, a first first conductivity type well formed on the surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate, and the first first conductivity on the surface of the semiconductor substrate A second first conductivity type well that is formed apart from the first first conductivity type well so as to surround the type well and to which a reference potential is applied, and is formed on the surface of the first first conductivity type well. A plurality of first second conductivity type regions to which electrostatic discharge is input and a plurality of second second conductivity type regions to which a reference potential is applied are formed alternately and spaced apart from each other A transistor and a wiring connecting a part of the first first conductivity type well to the second first conductivity type well, the first first conductivity type well and the second first conductivity type well; The resistivity of the region between the conductivity type wells is the first and second first conductivity. Electrostatic discharge protection device being higher than the resistivity of the well.
(Claim 15)
A first conductivity type guard ring, the impurity concentration of which is higher than the impurity concentration of the second first conductivity type well, is applied to the surface of the second first conductivity type well. 15. The electrostatic discharge protection element according to claim 13, wherein the electrostatic discharge protection element is formed so as to surround one first conductivity type well.
(Claim 16)
The substrate current of one transistor composed of one first second conductivity type region and the second second conductivity type region adjacent to the first first conductivity type region is the other current in the semiconductor substrate. The electrostatic discharge protection element according to claim 13, wherein the electrostatic discharge protection element passes through a region immediately below the transistor.
(Claim 17)
In the second conductivity type transistor, a plurality of the first and second second conductivity type regions are alternately arranged along the first direction, and the first second conductivity type region and the second conductivity type region are arranged. A plurality of gate electrodes provided above a region between the second conductivity type regions and the plurality of gate electrodes are connected to each other and a part thereof is connected to the second first conductivity type well. The electrostatic discharge protection element according to claim 1, further comprising: a resistor.
(Claim 18)
18. The electrostatic discharge protection element according to claim 17, wherein both ends of the resistor in the first direction are connected to the second first conductivity type well.
(Claim 19)
18. The electrostatic discharge protection element according to claim 17, wherein a central portion of the resistor in the first direction is connected to the second first conductivity type well.
(Claim 20)
A second conductivity type well formed in the inside of the second first conductivity type well or in a region adjacent to the second first conductivity type well on the surface of the semiconductor substrate, and a surface of the second conductivity type well; And a part of an edge of the first first conductivity type well facing the second conductivity type well is formed in the second first conductivity type well. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is connected.
(Claim 21)
A first wiring to which electrostatic discharge is input, a second wiring to which a reference potential is applied, and a plurality of transistors connected in parallel to each other between the first wiring and the second wiring; An electrostatic discharge protection element comprising: a resistor for connecting channels of the plurality of transistors to each other; and a third wiring for connecting a part of the resistors to the second wiring.
(Claim 22)
The transistor is formed on a surface of a semiconductor substrate, and a substrate current of one transistor passes through a region immediately below another transistor in the semiconductor substrate. The electrostatic discharge protection element of description.
(Claim 23)
The size of the resistor and the position connected to the third wiring are adjusted so that the resistance between the channel of the transistor and the second wiring has a desired distribution. The electrostatic discharge protection element according to claim 21 or 22.

(Appendix 2)
An electrostatic discharge protection element according to one of the above inventions includes a semiconductor substrate and a first first conductivity type well formed on a surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate. And a second first conductivity type well that is formed on the surface of the semiconductor substrate so as to surround the first first conductivity type well and is spaced apart from the first first conductivity type well and to which a reference potential is applied. And a first second conductivity type region formed on the surface of the first first conductivity type well to which electrostatic discharge is input and a second second conductivity type region to which a reference potential is applied are separated from each other. At least one end of the first first conductivity type well provided between the first first conductivity type well and the second first conductivity type well. A third portion connecting a portion of the edge to the second first conductivity type well; A first conductivity type well, and a region excluding the third first conductivity type well in a region between the first first conductivity type well and the second first conductivity type well. The resistivity is higher than the resistivity of the first to third first conductivity type wells.
In the electrostatic discharge protection element, the width of the region between the first first conductivity type well and the second first conductivity type well is adjusted by adjusting the size of the third first conductivity type well. The substrate resistance can be optimally controlled without being excessively reduced. As a result, both excellent ESD protection performance and latch-up performance can be achieved, and the layout area can be reduced.
The length of the third first conductivity type well in a direction perpendicular to the direction from the connection portion with the first first conductivity type well to the connection portion with the second first conductivity type well is It is preferable that the length of the first second conductivity type region is smaller than the length in the orthogonal direction.

  The present embodiment can be suitably applied to an electrostatic discharge protection element incorporated in a semiconductor integrated circuit device.

DESCRIPTION OF SYMBOLS 1; Semiconductor device 2; P well 3; N well 4, 14; ESD protection element 5, 15; Source region 6, 16; Drain region 7, 17; Gate electrode 8, 18; ; Silicide block region 11; P well block region 11a to 11h; notches 12, 22; guard ring 12a; frame-like portion 12b; extension 25; input pad 26; wiring 31; resistor 32, 35; Contact 34; P ⁺ region 41; resistor 42, 44; via 43; upper layer wiring 45; contact 51; resistor 52, 54; via 53, 56; upper layer wiring 55; contact 57; silicide 101; input buffer 102; Wiring 103; input pad 104; primary protection element 105; secondary protection element 106; input protection resistance 111 Finger 112; P-type substrate 113; P well 114; STI region 115; source region 116; drain region 117; channel region 118; gate electrode 119; guard ring 120; contact 121; P well block region 122; Mold substrate 132; P-channel MOS transistor (PMOS)
133; N-channel MOS transistor (NMOS)
134; N well 135; source region 136; guard ring 137; P well 138; source region 139; guard ring F1 to F6; finger D; length GND; ground potential wiring VDD; , Rsub1a, Rsub2,3, Rsub2a, Rsub5a, Rsub4,5, Rsub6a, Rsub6; substrate resistance

Claims (8)

  A semiconductor substrate, a first first conductivity type well formed on the surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate, and formed on the surface of the first first conductivity type well The plurality of first second conductivity type regions to which electrostatic discharge is input and the plurality of second second conductivity type regions to which the reference potential is applied are arranged in the first direction alternately and spaced apart from each other. A second conductivity type transistor, formed on the surface of the semiconductor substrate so as to surround the first first conductivity type well, and extending in a second direction perpendicular to the first direction of the first first conductivity type well; And a second first conductivity type well to which a reference potential is applied without contacting an edge extending in the first direction and in contact with the edge, and the first conductivity type well of the first first conductivity type well. A region between an edge extending in one direction and the second first conductivity type well The resistivity of said first and second electrostatic discharge protection device being higher than the resistivity of the first conductive type well. A semiconductor substrate, a first first conductivity type well formed on the surface of the semiconductor substrate and having a rectangular shape when viewed from a direction perpendicular to the surface of the semiconductor substrate, and the first first conductivity on the surface of the semiconductor substrate A second first conductivity type well that is formed apart from the first first conductivity type well so as to surround the type well and to which a reference potential is applied, and is formed on the surface of the first first conductivity type well. A plurality of first second conductivity type regions to which electrostatic discharge is input and a plurality of second second conductivity type regions to which a reference potential is applied are formed alternately and spaced apart from each other A transistor, a resistor provided on a portion of the first first conductivity type well, and a wiring connecting the resistor to the second first conductivity type well ; The resistivity is higher than the resistivity of the first and second first conductivity type wells. Electrostatic discharge protection element characterized that no.   A first conductivity type guard ring, the impurity concentration of which is higher than the impurity concentration of the second first conductivity type well, is applied to the surface of the second first conductivity type well. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is formed so as to surround one first conductivity type well.   The substrate current of one transistor composed of one first second conductivity type region and the second second conductivity type region adjacent to the first first conductivity type region is the other current in the semiconductor substrate. 4. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element passes through a region immediately below the first transistor.   In the second conductivity type transistor, a plurality of the first and second second conductivity type regions are alternately arranged along the first direction, and the first second conductivity type region and the second conductivity type region are arranged. A plurality of gate electrodes provided above a region between the second conductivity type regions and the plurality of gate electrodes are connected to each other and a part thereof is connected to the second first conductivity type well. 5. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is provided with a resistor.   6. The electrostatic discharge protection element according to claim 5, wherein both ends of the resistor in the first direction are connected to the second first conductivity type well.   6. The electrostatic discharge protection element according to claim 5, wherein a central portion of the resistor in the first direction is connected to the second first conductivity type well.   A second conductivity type well formed in the inside of the second first conductivity type well or in a region adjacent to the second first conductivity type well on the surface of the semiconductor substrate, and a surface of the second conductivity type well; And a part of an edge of the first first conductivity type well facing the second conductivity type well is formed in the second first conductivity type well. The electrostatic discharge protection element according to claim 1, wherein the electrostatic discharge protection element is connected.

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