CN103187416A

CN103187416A - Integrated circuit with element charging mode electrostatic discharge protection

Info

Publication number: CN103187416A
Application number: CN 201210587481
Authority: CN
Inventors: 叶致廷; 梁咏智
Original assignee: Industrial Technology Research Institute ITRI
Current assignee: Industrial Technology Research Institute ITRI
Priority date: 2011-12-30
Filing date: 2012-12-28
Publication date: 2013-07-03
Anticipated expiration: 2032-12-28
Also published as: CN103187416B

Abstract

An integrated circuit with device charge mode electrostatic discharge (CDM ESD) protection includes an input/output circuit, at least one device charge mode electrostatic discharge (CDM ESD) protection device, and an internal circuit. The internal circuit further includes at least one through-silicon via (TSV) configured to be coupled between a ground of at least one ground of the input/output circuit and the at least one device charge mode esd protection device, wherein each of the at least one device charge mode esd protection device is coupled between the at least one TSV and a ground of the at least one internal circuit.

Description

Integrated circuit with element charge mode electrostatic discharge protective

Technical field

The present invention is about a kind of integrated circuit with element charge mode electrostatic discharge protective.

Background technology

In three-dimensional stacked chip, can interconnect with the substrate that will respectively pile up by the plain conductor of each suprabasil circuit, therefore when this stacked chips was subjected to element charge mode electrostatic discharge event, the stored charge of each stack layer substrate can conflux through the plain conductor that connects each suprabasil circuit and discharge fast.

Yet when element charge mode electrostatic discharge event takes place, the electric charge that accumulates on each stack layer will flow simultaneously and produce big electric current in a flash.

As shown in Figure 1, wave mode 11 is the discharging current wave mode of the stored charge of an internal circuit, wave mode 13 is the summation of the discharging current wave mode that discharges in same time of the stored charge of the internal circuit of each stack layer, its element charge mode static discharge current will conflux and concentrate on certain time point, form the short discharge behavior of high current peak and release time.

Be subjected to the injury of element charge mode static discharge in order to reduce this instantaneous large-current for the element in the input/output circuitry, in three-dimensional stacked chip, hope can have a kind of protection mechanism that reduces above-mentioned this instantaneous large-current injury.

Summary of the invention

One embodiment of the invention disclose a kind of integrated circuit with element charge mode electrostatic discharge protective, comprise an input/output circuitry and at least one electrostatic discharge protective device, be configured to be coupled between the earthing potential of at least one earthing potential of this input/output circuitry and at least one internal circuit.

Above-mentioned integrated circuit, wherein this at least one electrostatic discharge protective device is coupled between the earthing potential of an earthing potential of this at least one internal circuit and another this at least one internal circuit.

Above-mentioned integrated circuit, wherein this at least one electrostatic discharge protective device comprises an element charge mode electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this element charge mode electrostatic discharge protective device comprises a turnpike formula circuit.

Above-mentioned integrated circuit, wherein this turnpike formula circuit is one to have the guiding path of low resistance when this integrated circuit normal manipulation mode.

Above-mentioned integrated circuit, wherein this turnpike formula circuit is one to have the guiding path of two-way admittance characteristic when element charge mode electrostatic discharge event takes place.

Above-mentioned integrated circuit, wherein this turnpike formula circuit is when element charge mode electrostatic discharge event takes place, and this turnpike formula circuit has a conducting voltage.

Above-mentioned integrated circuit wherein more comprises: the earthing potential that at least one through-silicon-via is coupled to this at least one earthing potential of this input/output circuitry reaches between this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is coupled between the earthing potential and this at least one electrostatic discharge protective device of this at least one internal circuit.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is coupled to another this at least one through-silicon-via.

Another embodiment of the present invention discloses a kind of integrated circuit with element charge mode electrostatic discharge protective, comprises an input/output circuitry, at least one electrostatic discharge protective device and at least one through-silicon-via.Wherein each this at least one through-silicon-via is coupled between the earth terminal and this at least one electrostatic discharge protective device of this input/output circuitry, and each this at least one electrostatic discharge protective device is configured to be coupled between the earth terminal of this at least one through-silicon-via and this at least one internal circuit.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is configured to be coupled between the earthing potential and this at least one electrostatic discharge protective device of this at least one internal circuit.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is configured to be coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is configured to be coupled to another this at least one through-silicon-via.

Above-mentioned integrated circuit, wherein when this integrated circuit normal manipulation mode, this turnpike formula circuit is one to have the guiding path of low resistance.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event takes place, this turnpike formula circuit is one to have the guiding path of two-way admittance characteristic.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event took place, this turnpike formula circuit had a conducting voltage.

An embodiment more of the present invention discloses a kind of integrated circuit of element charge mode electrostatic discharge protective device, comprise one and have one first end, first circuit of one second end and one the 3rd end, wherein this first end of this first circuit is coupled to a power supply, the 3rd end that this second end of this first circuit is coupled to one first earthing potential of an input/output circuitry or an internal circuit and this first circuit is coupled to one second earthing potential of another internal circuit, one has one first end, the second circuit of one second end and one the 3rd end, wherein this of this second circuit first end is coupled to this power supply, the 3rd end that this of this second circuit second end is coupled to this second earthing potential and this second circuit is coupled to this first earthing potential and one and has one first end, the tertiary circuit of one second end and one the 3rd end, wherein the 3rd end of this tertiary circuit is coupled to this power supply, and this first end that this of this tertiary circuit second end is coupled to this second earthing potential and this tertiary circuit is coupled to this first earthing potential.

Above-mentioned integrated circuit, wherein this tertiary circuit comprises a switch.

Above-mentioned integrated circuit, wherein this tertiary circuit provides a guiding path with two-way admittance characteristic of low resistance when this integrated circuit normal manipulation mode.

Above-mentioned integrated circuit, wherein this tertiary circuit provides a guiding path with two-way admittance characteristic when this integrated circuit meets with the generation of element charge mode electrostatic discharge event.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event took place, this tertiary circuit had a conducting voltage.

Above-mentioned integrated circuit, wherein when this integrated circuit normal manipulation mode, this first circuit and this second circuit are in closing state.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event took place, state and this second circuit that this first circuit is in conducting were in closing state, and the 3rd end of this of this tertiary circuit first end and this tertiary circuit is equipotential.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event took place, state and this first circuit that this second circuit is in conducting were in closing state, and the 3rd end of this of this tertiary circuit second end and this tertiary circuit is equipotential.

An embodiment more of the present invention discloses a kind of integrated circuit of element charge mode electrostatic discharge protective device, comprises a substrate, at least one the first transistor and and has first doped region that second type mixes.This at least one the first transistor is arranged in this substrate, wherein this transistor comprises one and has first doped region and that first type mixes and have second doped region that this first type mixes, and wherein this has first doped region that first type mixes and this and has one of second doped region that this first type mixes and be electrically connected at one first earth terminal of an input/output circuitry or an internal circuit and another and have one second earth terminal that first doped region that this first type mixes is electrically connected at another internal circuit.This has first doped region that second type mixes, and it is arranged in this substrate, and wherein this first doped region with the doping of second type is electrically connected at one of this first earth terminal or this second earth terminal.Wherein when this integrated circuit normal manipulation mode, this at least one the first transistor is in the state of conducting and wherein when element charge mode electrostatic discharge event takes place, and the conducting path that this at least one the first transistor is in closing state and a parasitic two-way admittance is provided is to discharge stored charge.

Above-mentioned integrated circuit, wherein this substrate more comprises a wellblock, and wherein this first doped region, this second doped region with this first type doping and this first doped region with this second type doping with this first type doping is arranged in this wellblock.

Above-mentioned integrated circuit wherein more comprises: a transistor seconds, and it is arranged in this substrate, and wherein this transistor seconds has the structure identical with this at least one the first transistor; And one have second doped region that this second type mixes, and it is arranged in this substrate, and wherein this has second doped region that this second type mixes and is electrically connected at another of this first earthing potential and this second earthing potential.

Above-mentioned integrated circuit, wherein more comprise: one first wellblock, it is arranged in this substrate, and wherein this of this at least one the first transistor has first doped region that this first type mixes and this and have this first type second doped region that mixes and first doped region that this has this second type doping and be positioned at this first wellblock.

Above-mentioned integrated circuit, wherein more comprise: one second wellblock, it is arranged in this substrate, and wherein this of this transistor seconds has first doped region that this first type mixes and this and have this first type second doped region that mixes and first doped region that this has this second type doping and be positioned at this second wellblock.

Above-mentioned integrated circuit wherein more comprises: one first diode structure, it comprises one and has the 3rd doped region that this first type mixes and this has first doped region that this second type mixes.

Above-mentioned integrated circuit wherein more comprises: one first wellblock, wherein this has the 3rd doped region that this first type mixes and is arranged in this first wellblock and this and has first doped region that this second type mixes and partly be arranged in this first wellblock.

Above-mentioned integrated circuit wherein more comprises: one has the doped region that this second type mixes, and it is electrically connected at this and has the 3rd doped region that this first type mixes.

Above-mentioned integrated circuit wherein more comprises: a transistor seconds, and it is arranged in this substrate, and wherein this transistor seconds has the structure identical with this at least one the first transistor; And one second diode structure, it comprises another the 3rd doped region and one with this first type doping and has second doped region that this second type mixes, and wherein this second doped region with this second type doping is electrically connected at another of this first earthing potential and this second earthing potential.

Above-mentioned integrated circuit wherein more comprises: one second wellblock, wherein this another have the 3rd doped region that this first type mixes and be arranged in this second wellblock and this and have second doped region that this second type mixes and partly be arranged in this second wellblock.

Above-mentioned integrated circuit wherein more comprises: one has the doped region that this second type mixes, its be electrically connected at this another have the 3rd doped region that this first type mixes.

Use protection mechanism of the present invention, can reduce the element charge mode static discharge of injury instantaneous large-current is subjected to to(for) the element in the input/output circuitry.

Those skilled in the art should understand, and hereinafter the concept of Jie Shiing can be used as the basis with specific embodiment and revised or design other structure quite easily or technology and realize the purpose identical with the present invention.Those skilled in the art also should understand, and the construction of this class equivalence also can't break away from the spirit and scope of the present invention that claims propose.

Description of drawings

Fig. 1 is the wave mode schematic diagram of the high current peak of element charge mode static discharge;

Fig. 2 has the static discharge current wave mode schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective device for one of one embodiment of the invention;

One of Fig. 3 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

One of Fig. 4 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

One of Fig. 5 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

One of Fig. 5-1 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

Another of Fig. 5-2 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective

The schematic diagram of the integrated circuit of a kind of element charge mode electrostatic discharge protective of Fig. 6 one embodiment of the invention;

The integrated circuit schematic diagram of a kind of element charge mode electrostatic discharge protective device of Fig. 7 one embodiment of the invention;

The schematic diagram of the integrated circuit of a kind of element charge mode electrostatic discharge protective device of Fig. 8 one embodiment of the invention;

The schematic diagram of the integrated circuit of a kind of element charge mode electrostatic discharge protective device of Fig. 9 another embodiment of the present invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 10 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 11 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 12 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 13 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 14 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 15 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 16 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 17 one embodiment of the invention; And

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 18 one embodiment of the invention.

Wherein, Reference numeral:

Resd resistance

Mp1 P transistor npn npn

Mn1 N-type transistor

11 wave modes

13 wave modes

21 wave modes

30 have the integrated circuit of element charge mode electrostatic discharge protective

31 element charge mode electrostatic discharge protective devices

38 input/output circuitries

39 internal circuits

31 element charge mode electrostatic discharge protective devices

40 have the integrated circuit of element charge mode electrostatic discharge protective

41 element charge mode electrostatic discharge protective devices

42 element charge mode electrostatic discharge protective devices

46 stack layers

46-1 first order stack layer

46-2 second level stack layer

49-1 first internal circuit

49-2 second internal circuit

50 have the integrated circuit of element charge mode electrostatic discharge protective

50-1 has the integrated circuit of element charge mode electrostatic discharge protective

50-2 has the integrated circuit of element charge mode electrostatic discharge protective

51 element charge mode electrostatic discharge protective devices

52 element charge mode electrostatic discharge protective devices

The 53-1 through-silicon-via

The 53-2 through-silicon-via

561 stack layers

56-1 level stack layer

562 stack layers

56-2 level stack layer

The 58-1 through-silicon-via

The 58-2 through-silicon-via

59-1 first internal circuit

59-2 second internal circuit

The integrated circuit of 60 element charge mode electrostatic discharge protectives

61 element charge mode electrostatic discharge protective devices

62 element charge mode electrostatic discharge protective devices

661 stack layers

66-1 level stack layer

662 stack layers

66-2 level stack layer

69-1 first internal circuit

69-2 second internal circuit

The integrated circuit of 70 element charge mode electrostatic discharge protective devices

71 first circuit

First end of 71-1 first circuit

Second end of 71-2 first circuit

The 3rd end of 71-3 first circuit

72 second circuits

First end of 72-1 second circuit

Second end of 72-2 second circuit

The 3rd end of 72-3 second circuit

73 tertiary circuits

First end of 73-1 tertiary circuit

Second end of 73-2 tertiary circuit

The 3rd end of 73-3 tertiary circuit

The integrated circuit of 80 element charge mode electrostatic discharge protective devices

81 the first transistors

82 1 transistor secondses

83-1 the 3rd transistor

83-2 the 3rd transistor

89 resistance

The integrated circuit of 90 element charge mode electrostatic discharge protective devices

91 transistors

92 transistors

The 93-1 transistor

The 93-2 transistor

The semiconductor structure of 101 element charge mode electrostatic discharge protective devices

The semiconductor structure of 102 element charge mode electrostatic discharge protective devices

110 metal-oxide-semiconductor field effect transistor structures

111 first heavily doped regions

112 second heavily doped regions

113 gate regions

120 metal-oxide-semiconductor field effect transistor structures

121 the one n type doped regions

122 the 2nd n type doped regions

123 gate regions

141 p-type doped regions

142 p-type doped regions

150 substrates

The semiconductor structure of 201 element charge mode electrostatic discharge protective devices

The semiconductor structure of 202 element charge mode electrostatic discharge protective devices

210 metal-oxide-semiconductor field effect transistor structures

211 first p-type doped regions

212 second p-type doped regions

213 gate regions

220 metal-oxide-semiconductor field effect transistor structures

221 first p-type doped regions

222 second p-type doped regions

223 gate regions

241 n type doped regions

242 n type doped regions

251 N wellblocks

252 N wellblocks

The semiconductor structure of 300 element charge mode electrostatic discharge protective devices

301 structures for the first time

302 structures for the second time

351 first N-type wellblocks

352 second N-type wellblocks

The semiconductor structure of 400 element charge mode electrostatic discharge protective devices

401 structures for the first time

402 structures for the second time

451 first N-type wellblocks

452 second N-type wellblocks

471 second diode structures

472 second N-type wellblocks

481 the 3rd n type doped regions

482 p-type doped regions

491 the 3rd n type doped regions

492 p-type doped regions

The semiconductor of 500 element charge mode electrostatic discharge protective devices

501 structures for the first time

502 structures for the second time

The semiconductor structure of 601 element charge mode electrostatic discharge protective devices

The semiconductor structure of 602 element charge mode electrostatic discharge protective devices

631 first diodes

632 second diodes

650 deep-well districts

651 N-type wellblocks

652 N-type wellblocks

681 first diodes

682 second diodes

Embodiment

The invention provides and a kind ofly have the integrated circuit of element charge mode electrostatic discharge protective so that stored charge is discharged step by step.

Fig. 2 has the static discharge current wave mode schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective for one of one embodiment of the invention.

As shown in Figure 2, wave mode 11 respectively is the discharging current wave mode of the stored charge of an internal circuit, wave mode 13 is the summation of the discharging current wave mode that discharges in same time of the stored charge of each internal circuit, and wave mode 21 then is the static discharge current wave mode of integrated circuit with element charge mode electrostatic discharge protective.

Shown in wave mode 21, this integrated circuit with element charge mode electrostatic discharge protective is when element charge mode electrostatic discharge event takes place, can reduce the peak value of discharging current and prolong release time, to avoid excessive electric current one input/output circuitry be damaged.

One of Fig. 3 one embodiment of the invention has the schematic diagram of the integrated circuit 30 of element charge mode electrostatic discharge protective.As shown in Figure 3, this integrated circuit 30 with element charge mode electrostatic discharge protective comprises an input/output circuitry 38, an element charge mode electrostatic discharge protective device (or claiming CDM Gating) 31 and one internal circuit 39.This input/output circuitry 38 is in order to the signal between an internal circuit that transmits a pad (Pad) and this integrated circuit 30, and can comprise ESD (Electrostatic Discharge) clamp circuit (indicating) to suppress the static discharge of this integrated circuit 30.

This input/output circuitry 38 can other forms presents and is not limit by embodiments of the invention.This element charge mode electrostatic discharge protective device 31 is coupled to one first earth terminal (example: one first reference voltage or earthing potential VSS or a VSSIO) and the one second earth terminal (example: an earthing potential of second reference voltage or this internal circuit 39) of this input/output circuitry 38.

This element charge mode electrostatic discharge protective device 31 comprises a turnpike formula circuit, and wherein this turnpike formula circuit is one to have the guiding path of low resistance when these integrated circuit 30 normal manipulation modes.The resistance of this guiding path depends on the electric current demand of internal circuit.

For example the electric current demand of internal circuit is 100mA, and the cross-pressure that allows to be consumed in turnpike formula circuit can push away to such an extent that this resistance is 0.1 ohm when being 10mV, can instead push away the component size designed size of turnpike formula circuit whereby, and this is an embodiment, but not as limit.

And when element charge mode electrostatic discharge event took place, this turnpike formula circuit had a conducting voltage.This turn-on voltage needs less than the grid breakdown voltage of inner member or connects the face breakdown voltage, and when the two ends cross-pressure of this turnpike formula circuit surpassed this conducting voltage, the electrostatic charge that accumulates on internal circuit can see through this turnpike formula circuit and discharge.

When for example the grid breakdown voltage of inner member was 3V, the design maximum of its conducting voltage needed less than 3V voltage, if with the diode be Dao Tong Lu ? element, its conducting voltage is 0.7V, but not as limit.

At this moment, this element charge mode electrostatic discharge protective device 31 is that a pair of is to the charge-conduction path of conducting, be configured to the stored charge of this internal circuit 39 is released into this input/output circuitry 38 step by step, cause excessive rush of current for this input/output circuitry 38 when flowing out this internal circuit 39 in a large number to reduce stored charge.

Because the polarity of the accumulation electrostatic charge of this element charge mode comprises positive or negative polarity, the conducting path that sees through two-way admittance all can discharge step by step.This element charge mode electrostatic discharge protective device 31 will be specified in the paragraph of Fig. 7 to Fig. 9.

One of Fig. 4 one embodiment of the invention has the schematic diagram of the integrated circuit 40 of element charge mode electrostatic discharge protective.As shown in Figure 4, this integrated circuit 40 with element charge mode electrostatic discharge protective comprises one first internal circuit 49-1, one first element charge mode electrostatic discharge protective device (CDM Gating), 41,1 second internal circuit 49-2, at least one second element charge mode electrostatic discharge protective device 42 and this input/output circuitry 38.

This first element charge mode electrostatic discharge protective device 41 wherein, this element charge mode electrostatic discharge protective device 31 as shown in Figure 3 is coupled to one first earth terminal (example: one first reference voltage or earthing potential VSS or a VSSIO) and the one second earth terminal (example: the earthing potential of second reference voltage or this first internal circuit 49-1) of this input/output circuitry 38.

In addition, this second element charge mode electrostatic discharge protective device 42 is coupled to this earthing potential of this first internal circuit 49-1 and the earthing potential of this second internal circuit 49-2.

In addition, each this first element charge mode electrostatic discharge protective device 41 and this second element charge mode electrostatic discharge protective device 42 are similar to this element charge mode electrostatic discharge protective device 31 shown in Figure 3.

This first element charge mode electrostatic discharge protective device 41 and this second element charge mode electrostatic discharge protective device 42 respectively comprise a turnpike formula circuit, this turnpike formula circuit is when these integrated circuit 40 normal manipulation modes, be one to have the guiding path of low resistance, in order to the conduction of electric current, wherein the resistance of the guiding path of this low resistance depends on the electric current demand of internal circuit.

At this moment, this first element charge mode electrostatic discharge protective device 41 and this second element charge mode electrostatic discharge protective device 42 are that a pair of is to the charge-conduction path of conducting, be configured to the stored charge of this internal circuit is released into this input/output circuitry 38 step by step, cause excessive rush of current for this input/output circuitry 38 when flowing out this internal circuit 49-1 and this internal circuit 49-2 in a large number to reduce stored charge.

Because the polarity of the accumulation electrostatic charge of this element charge mode comprises positive or negative polarity, the conducting path that sees through two-way admittance all can discharge step by step.

One of Fig. 5 one embodiment of the invention has the schematic diagram of the integrated circuit 50 of element charge mode electrostatic discharge protective.Compared to this integrated circuit 40 shown in Figure 4, this integrated circuit 50 shown in Figure 5 comprises other element charge mode electrostatic discharge protective device and internal circuit in addition in other stack layers.

Specifically, this integrated circuit 50 comprises several stack layers 46,561,562,661 and 662, and this integrated circuit 50 comprises several through-silicon-vias in addition, and each through-silicon-via is coupled between two stack layers that link to each other.

In present embodiment, be example with five stack layers and four through-silicon-vias.Yet those stack layers and those through-silicon-vias only are example, and in other embodiment, the quantity of stack layer and through-silicon-via can be greater or less than this example.

In addition, be the convenient present embodiment of explaining, vertically be coupled to the through-silicon-via 58-1 between this

stack layer

561 and 562 and vertically be coupled to through-silicon-via 58-2 between this

stack layer

661 and 662 laterally to represent.

Each stack layer 46,561,562,661 and 662 comprises one-level stack layer at least.In present embodiment, this stack layer 46 comprises first order stack layer 46-1 and second level stack layer 46-2.This first order stack layer 46-1 more comprises this first element charge mode electrostatic discharge protective device 41 and this first internal circuit 49-1, and this second level stack layer 46-2 comprises this second element charge mode electrostatic discharge protective device 42 and this second internal circuit 49-2 in addition.

In addition, this stack layer 561 comprises one-level stack layer 56-1 and this stack layer 562 comprises one-level stack layer 56-2.This grade stack layer 56-1 more comprises one first element charge mode electrostatic discharge protective device 51 and one first internal circuit 59-1, and this grade stack layer 56-2 more comprises one second element charge mode electrostatic discharge protective device 52 and one second internal circuit 59-2.

This first element charge mode electrostatic discharge protective device 51 of this grade stack layer 56-1 of this stack layer 561 is coupled to an earth terminal (example: the earthing potential of second reference voltage or this first internal circuit 59-1) of one first earth terminal (example: one first reference voltage or earthing potential VSS or a VSSIO) and this first internal circuit 59-1 of this input/output circuitry 38 by a through-silicon-via 53-1.

In addition, this second element charge mode electrostatic discharge protective device 52 of this grade stack layer 56-2 of this stack layer 562 is coupled between the earthing potential of this earthing potential of this first internal circuit 59-1 and this second internal circuit 59-2 by this through-silicon-via 58-1.

Similarly, this stack layer 661 comprises one-level stack layer 66-1 and this stack layer 662 comprises one-level stack layer 66-2.This grade stack layer 66-1 more comprises one first element charge mode electrostatic discharge protective device 61 and one first internal circuit 69-1, and this grade stack layer 66-2 more comprises one second element charge mode electrostatic discharge protective device 62 and one second internal circuit 69-2.

This first element charge mode electrostatic discharge protective device 61 of this grade stack layer 66-1 of this stack layer 661 is coupled to an earth terminal (example: the earthing potential of second reference voltage or this first internal circuit 69-1) of one first earth terminal (example: one first reference voltage or earthing potential VSS or a VSSIO) and this first internal circuit 69-1 of this input/output circuitry 38 by a through-silicon-via 53-2

In addition, this second element charge mode electrostatic discharge protective device 62 of this grade stack layer 66-2 of this stack layer 662 is coupled between the earthing potential of this earthing potential of this first internal circuit 69-1 and this second internal circuit 69-2 by this through-silicon-via 58-2.

Another of Fig. 5-1 one embodiment of the invention has the schematic diagram of the integrated circuit 50-1 of element charge mode electrostatic discharge protective.Compared to this integrated circuit 50 shown in Figure 5, this integrated circuit 50-1 does not have this second level stack layer 46-2 and this first order stack layer 46-1 of this stack layer 46.

Another of Fig. 5-2 one embodiment of the invention has the schematic diagram of the integrated circuit 50-2 of element charge mode electrostatic discharge protective.Compared to this integrated circuit 50-1 shown in Fig. 5-1, this through-silicon-via 53-1 of this integrated circuit 50-2 is coupled to VSSIO.Embodiment shown in Fig. 5, Fig. 5-1 and Fig. 5-2 is coupled to an earth terminal and this at least one charge mode electrostatic discharge protective device of at least one earth terminal of this input/output circuitry at least one through-silicon-via.

The schematic diagram of the integrated circuit 60 of a kind of element charge mode electrostatic discharge protective of Fig. 6 one embodiment of the invention.Compared to this integrated circuit 50 shown in Figure 5, the integrated circuit 60 of this element charge mode electrostatic discharge protective comprises the another kind of connected mode of this through-silicon-via 53-2 in addition.

As shown in Figure 6, this through-silicon-via 53-2 is connected in the end of this through-silicon-via 58-1.In an embodiment, this through-silicon-via 53-2 is coupled to the one first end 58a of this through-silicon-via 58-1, and in addition, this first end 58a is near this first internal circuit 59-1.Therefore, this stack layer 561 couples this stack layer 562 and is coupled to this stack layer 661 by this through-silicon-via 53-2 by this through-silicon-via 58-1.

In another embodiment, this through-silicon-via 53-2 is coupled to the one second end points 58b of this through-silicon-via 58-1, and wherein this second end points 58b is near this second element charge mode electrostatic discharge protective device 52.Therefore, this stack layer 561 couples this stack layer 562 and is coupled to this stack layer 661 by this through-silicon-via 58-1 and 53-2 by this through-silicon-via 58-1.

Integrated circuit 70 schematic diagrames of a kind of element charge mode electrostatic discharge protective device of Fig. 7 one embodiment of the invention.As shown in Figure 7, this element charge mode electrostatic discharge protective device 70 comprises one first circuit 71, a second circuit 72 and a tertiary circuit 73.

One first end 71-1 of this first circuit 71 is configured to be coupled to a power supply, one second end 71-2 is configured to be coupled to one first earth terminal, and (example: one first reference voltage), one the 3rd end 71-3 is configured to be coupled to one second earth terminal (example: one second reference voltage).This first earth terminal comprises an earthing potential or an internal circuit of an input/output circuitry.This second earth terminal comprises an earthing potential of another internal circuit.

One first end 72-1 of this second circuit 72 is configured to be coupled to this power supply, and one second end 72-2 is configured to be coupled to this second earth terminal, and one the 3rd end 72-3 is configured to be coupled to this first earth terminal.

One the 3rd end 73-3 of this tertiary circuit 73 is configured to be coupled to this power supply, and one second end 73-2 is configured to be coupled to this second earth terminal, and one first end 73-1 is configured to be coupled to this first earth terminal.

Wherein this tertiary circuit 73 is a turnpike formula circuit, and when these integrated circuit 70 normal manipulation modes, the guiding path with a low resistance is configured the conduction in order to electric current, and wherein the resistance of the guiding path of this low resistance depends on the electric current demand of internal circuit.

For example the electric current demand of internal circuit is 100mA, and the cross-pressure that allows to be consumed in turnpike formula circuit can push away to such an extent that this resistance is 0.1 ohm when being 10mV, can instead push away the component size designed size of turnpike formula circuit whereby, and this is an embodiment, but not as limit.Wherein this first circuit and this second circuit are a closed condition when this integrated circuit normal manipulation mode.And when element charge mode electrostatic discharge event took place, this tertiary circuit 73 had a conducting voltage.This conducting voltage needs less than the grid breakdown voltage of inner member or connects the face breakdown voltage, and when the two ends cross-pressure of this turnpike formula circuit surpassed this conducting voltage, the electrostatic charge that accumulates on internal circuit can see through this turnpike formula circuit and discharge.

When for example the grid breakdown voltage of inner member was 3V, the design maximum of its conducting voltage needed less than 3V voltage, and as if being the element of guiding path with the diode, its conducting voltage is 0.7V, but not as limit.

In this embodiment, this tertiary circuit 73 is that a pair of is to the conducting path of conducting, when the two ends cross-pressure of this second end 73-2 of this first end 73-1 of this tertiary circuit 73 and this tertiary circuit 73 surpassed this conducting voltage, electrostatic charge can see through this tertiary circuit 73 be released into this input/output circuitry or other internal circuits.

In addition, because this tertiary circuit 73 has a conducting voltage, whereby to postpone discharging this stored charge, with the excessive impact that electric current was caused of releiving.

Wherein, in an embodiment, when this integrated circuit component charge mode electrostatic discharge event takes place, this first circuit 71 is a conducting state, this second circuit 72 is a closed condition, be that a closed condition and this second circuit 72 are a conducting state so that this first end 73-1 of this tertiary circuit 73 and the 3rd end 73-3 are equipotential or this first circuit 71, so that this second end 73-2 of this tertiary circuit 73 and the 3rd end 73-3 are equipotential.

The schematic diagram of the integrated circuit 80 of a kind of element charge mode electrostatic discharge protective device of Fig. 8 one embodiment of the invention.As shown in Figure 8, the integrated circuit 80 of this element charge mode electrostatic discharge protective device comprises a first transistor 81, a transistor seconds 82, the 3rd transistor 83-1,83-2 and a resistance 89.

One drain electrode end of this first transistor 81 is coupled to a power supply by this resistance 89, and a gate terminal is coupled to one first earth terminal of an input/output circuitry (not drawing) and one second earth terminal of an internal circuit.

This transistor seconds 82 comprises a drain electrode end, one source pole end and a gate terminal.This drain electrode end is coupled to this power supply by this resistance 89.This source terminal is coupled to this first earth terminal, and this gate terminal is coupled to this second earth terminal.

The 3rd transistor 83-1 comprises a drain electrode end, one source pole end and a gate terminal.This gate terminal is coupled to this power supply by this resistance 89.This drain electrode end is coupled to this first earth terminal, and this source terminal is coupled to this second earth terminal.

Another the 3rd transistor 83-2 comprises a drain electrode end, one source pole end and a gate terminal.This gate terminal is coupled to this power supply by this resistance 89.This source terminal is coupled to this first earth terminal, and this drain electrode end is coupled to this second earth terminal.

Each those

transistor

81,82,83-1 and 83-2 all comprise N-type metal oxide semiconductcor field effect (NMOS) transistor.In addition, each those the 3rd transistor 83-1 and 83-2 respectively comprise a parasitic diode, and wherein this parasitic diode has a conducting voltage, and wherein the voltage range of this conducting voltage is 0.6V ~ 0.7V, but not as limit.

This conducting voltage is less than the grid breakdown voltage of those the 3rd transistor 83-1 and 83-2 or connect the face breakdown voltage.As the 3rd transistor 83-1(83-2) the two ends cross-pressure of this drain electrode (source electrode) end and this source electrode (drain electrode) end when surpassing this conducting voltage, accumulate on internal circuit electrostatic charge can through those the 3rd transistor 83-1 and 83-2 one to discharge.

When normal manipulation mode, this the first transistor 81 and this transistor seconds 82 are closing state, those the 3rd transistor 83-1 and 83-2 are the state of conducting, this moment, this element charge mode electrostatic discharge protective device 80 was one to have the guiding path of low resistance, and it is between this first earth terminal and this second earth terminal.

And when element charge mode electrostatic discharge event took place, those the 3rd transistor 83-1 and 83-2 were all closing state.Therefore, the stored charge of this internal circuit via this parasitic diode of those the 3rd transistor 83-1 and 83-2 to be released into this input/output circuitry.This parasitic diode has a conducting voltage, and wherein the voltage range of this conducting voltage is 0.6V ~ 0.7V, but not as limit.

Therefore, the potential difference between first earth terminal and second earth terminal is equal to or greater than this conducting voltage, and this stored charge will discharge via this parasitic diode.

The schematic diagram of the integrated circuit 90 of a kind of element charge mode electrostatic discharge protective device of Fig. 9 one embodiment of the invention.Compared to Fig. 8, those

transistors

91,92,93-1 and the 93-2 of the integrated circuit 90 of element charge mode electrostatic discharge protective device respectively comprises a P-type mos field and imitates (PMOS) transistor.

This tertiary circuit 73 shown in Figure 7 comprises those the 3rd transistor 83-1 and 83-2 of Fig. 8 example, and in addition, this tertiary circuit 73 shown in Figure 7 also comprises those the 3rd transistor 93-1 and 93-2 of Fig. 9 example.

Above-mentioned those transistors can be adopted the semiconductor structure embodiment of following Figure 10～Figure 18 invention in addition.

The generalized section of the semiconductor structure 101 of a kind of element charge mode electrostatic discharge protective device of Figure 10 one embodiment of the invention.As shown in figure 10, this semiconductor structure 101 comprises a substrate 150, a metal-oxide-semiconductor field effect transistor structure 110 and a heavily doped region 141.

This substrate 150 comprises a silicon substrate, and it has micro-p-type and mixes.

This metal-oxide-semiconductor field effect transistor structure 110 comprises a gate regions 113, one first heavily doped region 111 and one second heavily doped region 112.Each this first heavily doped region 111 has one first type with this second heavily doped region 112 and mixes, and for example is that the n type mixes.

In addition, this first heavily doped region 111 is decided on its power supply that connects with this second heavily doped region 112, can be as source electrode or the drain electrode of this metal-oxide-semiconductor field effect transistor structure 110.

141 of this heavily doped regions have one second type and mix, and for example are that p-type is mixed.(example: shallow trench isolation is electrically isolated from (Shallow trench isolation, STI)) by an isolation structures for this heavily doped region 141.The 2nd n type doped region 112 and this p-type doped region 141 all are electrically connected at an earth terminal, example: a reference voltage of an internal circuit or an earthing potential.The one n type doped region 111 is electrically connected at an earth terminal, example: a reference voltage of an input/output circuitry or an earthing potential.

When element charge mode electrostatic discharge event took place, this input/output circuitry, a n type doped region 111, this substrate 150, the 2nd n type doped region 112 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

In addition, this input/output circuitry, a n type doped region 111, this substrate 150, this p-type doped region 141 and this internal circuit form another electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

The generalized section of the semiconductor structure 102 of a kind of element charge mode electrostatic discharge protective device of Figure 11 one embodiment of the invention, compared to Figure 10, one the one n type doped region 121 of one metal-oxide-semiconductor field effect transistor structure 120 of this semiconductor structure 102 is electrically connected at a p-type doped region 142 and an input/output circuitry, and the 2nd n type doped region 122 then is electrically connected at an internal circuit.

Therefore, when element charge mode electrostatic discharge event took place, this input/output circuitry, a n type doped region 121, this substrate 150, the 2nd n type doped region 122 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

In addition, this input/output circuitry, this p-type doped region 142, this substrate 150, the 2nd n type doped region 122 and this internal circuit form another electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

The generalized section of the semiconductor structure 201 of a kind of element charge mode electrostatic discharge protective device of Figure 12 one embodiment of the invention.As shown in figure 12, this semiconductor structure 201 comprises the semiconductor wellblock, example: a N wellblock 251, this semiconductor wells district is arranged in this substrate 150.One metal-oxide-semiconductor field effect transistor structure 210, it is arranged in this N wellblock 251.

This metal-oxide-semiconductor field effect transistor structure 210 comprises a gate regions 213, one first p-type doped region 211 and one second p-type doped region 212.

This second p-type doped region 212 is electrically connected at this n type doped region 241 and an internal circuit.This first p-type doped region 211 is electrically connected at an input/output circuitry.

Therefore, when element charge mode electrostatic discharge event took place, this input/output circuitry, this first p-type doped region 211, this N wellblock 251, this second p-type doped region 212 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

In addition, this input/output circuitry, this first p-type doped region 211, this N wellblock 251, this n type doped region 241 and this internal circuit form an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

The generalized section of the semiconductor structure 202 of a kind of element charge mode electrostatic discharge protective device of Figure 13 one embodiment of the invention.Compared to Figure 12, in an embodiment of the present invention, this first p-type doped region 221 of one metal-oxide-semiconductor field effect transistor structure 220 of one N wellblock 252 of this semiconductor structure 202 is electrically connected at a n type doped region 242 and an input/output circuitry, in addition, one second p-type doped region 222 is electrically connected at an internal circuit.

Therefore, when element charge mode electrostatic discharge event took place, this input/output circuitry, this first p-type doped region 221, this N wellblock 252, this second p-type doped region 222 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

In addition, this input/output circuitry, this n type doped region 242, this N wellblock 252, this second p-type doped region 222 and this internal circuit form another electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

The generalized section of the semiconductor structure 300 of a kind of element charge mode electrostatic discharge protective device of Figure 14 one embodiment of the invention.

As shown in figure 14, this semiconductor structure 300 comprises structure 301 and a structure 302 for the second time for the first time.Compared to this semiconductor structure 101 shown in Figure 10, this, structure these p-type doped region 141 parts of 301 were formed at one first wellblock, example first time: one first N-type wellblock 351.Similarly, compared to this semiconductor structure 102 shown in Figure 11, this, structure these p-type doped region 142 parts of 302 were formed at one second wellblock, example second time: one second N-type wellblock 352.

Therefore, when element charge mode electrostatic discharge event took place, the 2nd n type doped region 122 of this input/output circuitry, this p-type doped region 142, this substrate 150, this metal-oxide-semiconductor field effect transistor structure 120 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

In addition, a n type doped region 111, this substrate 150, this p-type doped region 141 and this internal circuit of this input/output circuitry, this metal-oxide-semiconductor field effect transistor structure 110 forms another electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

The generalized section of the semiconductor structure 400 of a kind of element charge mode electrostatic discharge protective device of Figure 15 one embodiment of the invention.

As shown in figure 15, this semiconductor structure 400 comprises structure 401 and a structure 402 for the second time for the first time.Compared to this semiconductor structure 101 shown in Figure 10, this, structure 401 comprised one first diode structure 471 first time, and it more comprises one the 3rd n type doped region, 481, the three n type doped regions 481 and is positioned at one first N-type wellblock 451.This, structure 401 comprised a p-type doped region 482 in addition first time, and its part is arranged in this first N-type wellblock 451 and isolates with the 3rd n type doped region 481 from (STI) by shallow trench isolation.

The 3rd n type doped region 481 of this first diode structure 471 is electrically connected at this p-type doped region 141.In addition, this p-type doped region 482 of this first diode structure 471 is electrically connected at the 2nd n type doped region 112 of this metal-oxide-semiconductor field effect transistor structure 110, also is connected in this internal circuit simultaneously.

Compared to this semiconductor structure 102 shown in Figure 11, this, structure 402 comprised one second diode structure 472 second time, and it more comprises one the 3rd n type doped region, 491, the three n type doped regions 491 and is positioned at one second N-type wellblock 452.This, structure 402 comprised a p-type doped region 492 in addition second time, and its part is arranged in this second N-type wellblock 452 and isolates with the 3rd n type doped region 491 from (STI) by shallow trench isolation.

The 3rd n type doped region 491 of this second diode structure 452 is electrically connected at this p-type doped region 142.In addition, this p-type doped region 492 of this second diode structure 472 is electrically connected at a n type doped region 121 of this metal-oxide-semiconductor field effect transistor structure 120, also is connected in this input/output circuitry simultaneously.

Therefore, when element charge mode electrostatic discharge event took place, the 2nd n type doped region 122 of this input/output circuitry, this p-type doped region 492, this second N-type wellblock 452, the 3rd n type doped region 491, this p-type doped region 142, this substrate 150, this metal-oxide-semiconductor field effect transistor structure 120 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

In addition, this input/output circuitry, this metal-oxide-semiconductor field effect transistor structure 110 a n type doped region 111, this substrate 150, this p-type doped region 141, the 3rd n type doped region 481, this first N-type wellblock 451, this p-type doped region 482 and this internal circuit form another electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

The generalized section of semiconductor 500 structures of a kind of element charge mode electrostatic discharge protective device of Figure 16 one embodiment of the invention.

As shown in figure 16, this semiconductor structure 500 comprises structure 501 and a structure 502 for the second time for the first time.This, structure 501 was similar to this semiconductor structure 201 shown in Figure 12 first time.In addition, this, structure 502 was similar to this semiconductor structure 202 shown in Figure 13 second time.

Therefore, when element charge mode electrostatic discharge event took place, this first p-type doped region 211 of this input/output circuitry, this metal-oxide-semiconductor field effect transistor structure 210, this first N-type wellblock 251, this n type doped region 241 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

In addition, this second p-type doped region 222 of this input/output circuitry, this n type doped region 242, this second N-type wellblock 252, this metal-oxide-semiconductor field effect transistor structure 220 and this internal circuit form another electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

The generalized section of the semiconductor structure 601 of a kind of element charge mode electrostatic discharge protective device of Figure 17 one embodiment of the invention.

As shown in figure 17, compared to this metal-oxide-semiconductor field effect transistor structure 210 that is positioned at this N-type wellblock shown in Figure 12, this semiconductor structure 601 comprises one first diode 631 and one second diode 632.

This first diode 631 has an anode and a negative electrode, this anode of this first diode 631 is electrically connected at this first p-type doped region 211 and an input/output circuitry, and this negative electrode of this first diode 631 is electrically connected at this second p-type doped region 212 and an internal circuit.

This second diode 632 also has an anode and a negative electrode, this anode of this second diode 632 is electrically connected at this second p-type doped region 212 and this internal circuit, and this negative electrode of this second diode 632 is electrically connected at this first p-type doped region 211 and this input/output circuitry.

Therefore, when element charge mode electrostatic discharge event took place, this input/output circuitry, this first diode 631 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

In addition, this input/output circuitry, this second diode 632 and this internal circuit form another electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

In this embodiment, each electrical conducting path only has a diode 631 or 632.Yet in other embodiment, the mode that this first diode 631 can the series connection of one or more diode presents.

In addition, the mode that this second diode 632 can also one or more diode series connection presents.

The generalized section of the semiconductor structure 602 of a kind of element charge mode electrostatic discharge protective device of Figure 18 one embodiment of the invention.As shown in figure 18, compared to this metal-oxide-semiconductor field effect transistor structure 110 that is positioned at this N-type wellblock shown in Figure 10, this semiconductor structure 602 comprises one first diode 681 and one second diode 682.

This semiconductor structure 602 more comprises a wellblock, example: a deep N-well district 650, this deep N-well district 650 are positioned at this metal-oxide-semiconductor field effect transistor structure 110, N-type wellblock 651 and 652 and part shallow trench isolation following from (STI).

This first diode 681 has an anode and a negative electrode, this anode of this first diode 681 is electrically connected at a n type doped region 111 and an input/output circuitry, and this negative electrode of this first diode 681 is electrically connected at the 2nd n type doped region 112 and an internal circuit.

This second diode 682 has an anode and a negative electrode, this anode of this second diode 682 is electrically connected at the 2nd n type doped region 112 and this internal circuit, and this negative electrode of this second diode 682 is electrically connected at n type doped region 111 and this input/output circuitry.

Therefore, when element charge mode electrostatic discharge event took place, this input/output circuitry, this first diode 681 and this internal circuit formed an electrical conducting path to allow static discharge current flow to this internal circuit from this input/output circuitry.

In addition, this input/output circuitry, this second diode 682 and this internal circuit form another electrical conducting path to allow static discharge current flow to this input/output circuitry from this internal circuit.

In this embodiment, each electrical conducting path only has a diode 681 or 682.Yet in other embodiment, the mode that this first diode 681 can the series connection of one or more diode presents.

In addition, the mode that this second diode 682 can also one or more diode series connection presents.

Technology contents of the present invention and technical characterstic disclose as above, yet it will be understood by a person skilled in the art that, in not deviating from the spirit and scope of the invention that claims define, and teaching of the present invention and disclose and can do all replacements and modification.For example, above many technologies of Jie Shiing can diverse ways be implemented or are replaced with other technology, perhaps adopt the combination of above-mentioned two kinds of modes.

In addition, composition, device, method or the step of the technology of the interest field of this case specific embodiment that is not limited to above disclose, board, manufacturing, material.It will be understood by a person skilled in the art that, based on teaching of the present invention and disclose composition, device, method or the step of technology, board, manufacturing, material, no matter existed now or developer in the future, it carries out the essence identical functions with this case embodiment announcement person in the identical mode of essence, and reach the identical result of essence, also can be used in the present invention.Therefore, claims are in order to contain composition, device, method or the step in order to this type of technology, board, manufacturing, material.

Claims

1. the integrated circuit with element charge mode electrostatic discharge protective is characterized in that, comprises:

One input/output circuitry; And

At least one electrostatic discharge protective device is configured to be coupled between the earthing potential of at least one earthing potential of this input/output circuitry and at least one internal circuit.

2. integrated circuit as claimed in claim 1 is characterized in that, this at least one electrostatic discharge protective device is coupled between the earthing potential of an earthing potential of this at least one internal circuit and another this at least one internal circuit.

3. integrated circuit as claimed in claim 1 is characterized in that, this at least one electrostatic discharge protective device comprises an element charge mode electrostatic discharge protective device.

4. integrated circuit as claimed in claim 3 is characterized in that, this element charge mode electrostatic discharge protective device comprises a turnpike formula circuit.

5. integrated circuit as claimed in claim 4 is characterized in that, this turnpike formula circuit is one to have the guiding path of low resistance when this integrated circuit normal manipulation mode.

6. integrated circuit as claimed in claim 4 is characterized in that, when this turnpike formula circuit takes place in element charge mode electrostatic discharge event, is one to have the guiding path of two-way admittance characteristic.

7. integrated circuit as claimed in claim 4 is characterized in that, when this turnpike formula circuit took place in element charge mode electrostatic discharge event, this turnpike formula circuit had a conducting voltage.

8. integrated circuit as claimed in claim 1 is characterized in that, more comprises:

The earthing potential that at least one through-silicon-via is coupled to this at least one earthing potential of this input/output circuitry reaches between this at least one electrostatic discharge protective device.

9. integrated circuit as claimed in claim 8 is characterized in that, this at least one through-silicon-via is coupled between the earthing potential and this at least one electrostatic discharge protective device of this at least one internal circuit.

10. integrated circuit as claimed in claim 8 is characterized in that, this at least one through-silicon-via is coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

11. integrated circuit as claimed in claim 10 is characterized in that, this at least one through-silicon-via is coupled between the earthing potential and this at least one electrostatic discharge protective device of this at least one internal circuit.

12. integrated circuit as claimed in claim 10 is characterized in that, this at least one through-silicon-via is coupled to another this at least one through-silicon-via.

13. the integrated circuit with element charge mode electrostatic discharge protective is characterized in that, comprises:

One input/output circuitry;

At least one electrostatic discharge protective device; And

At least one through-silicon-via, and each this at least one through-silicon-via is coupled between the earthing potential and this at least one electrostatic discharge protective device of this input/output circuitry;

Wherein each this at least one electrostatic discharge protective device is configured to be coupled between the earthing potential of this at least one through-silicon-via and this at least one internal circuit.

14. integrated circuit as claimed in claim 13 is characterized in that, this at least one through-silicon-via is configured to be coupled between the earthing potential and this at least one electrostatic discharge protective device of this at least one internal circuit.

15. integrated circuit as claimed in claim 13 is characterized in that, this at least one through-silicon-via is configured to be coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

16. integrated circuit as claimed in claim 15 is characterized in that, this at least one through-silicon-via is configured to be coupled between the earthing potential and this at least one electrostatic discharge protective device of this at least one internal circuit.

17. integrated circuit as claimed in claim 15 is characterized in that, this at least one through-silicon-via is configured to be coupled to another this at least one through-silicon-via.

18. integrated circuit as claimed in claim 13 is characterized in that, this at least one electrostatic discharge protective device comprises an element charge mode electrostatic discharge protective device.

19. integrated circuit as claimed in claim 18 is characterized in that, this element charge mode electrostatic discharge protective device comprises a turnpike formula circuit.

20. integrated circuit as claimed in claim 19 is characterized in that, when this integrated circuit normal manipulation mode, this turnpike formula circuit is one to have the guiding path of low resistance.

21. integrated circuit as claimed in claim 19 is characterized in that, when element charge mode electrostatic discharge event took place, this turnpike formula circuit was one to have the guiding path of two-way admittance characteristic.

22. integrated circuit as claimed in claim 19 is characterized in that, when element charge mode electrostatic discharge event took place, this turnpike formula circuit had a conducting voltage.

23. the integrated circuit with element charge mode electrostatic discharge protective is characterized in that, comprises:

One has first circuit of one first end, one second end and one the 3rd end, wherein this first end of this first circuit is coupled to a power supply, and the 3rd end that this second end of this first circuit is coupled to one first earthing potential of an input/output circuitry or an internal circuit and this first circuit is coupled to one second earthing potential of another internal circuit;

One has the second circuit of one first end, one second end and one the 3rd end, wherein this of this second circuit first end is coupled to this power supply, and the 3rd end that this of this second circuit second end is coupled to this second earthing potential and this second circuit is coupled to this first earthing potential; And

One has the tertiary circuit of one first end, one second end and one the 3rd end, wherein the 3rd end of this tertiary circuit is coupled to this power supply, and this first end that this of this tertiary circuit second end is coupled to this second earthing potential and this tertiary circuit is coupled to this first earthing potential.

24. integrated circuit as claimed in claim 23 is characterized in that, this tertiary circuit comprises a switch.

25. integrated circuit as claimed in claim 23 is characterized in that, this tertiary circuit provides a guiding path with two-way admittance characteristic of low resistance when this integrated circuit normal manipulation mode.

26. integrated circuit as claimed in claim 23 is characterized in that, when this tertiary circuit meets with the generation of element charge mode electrostatic discharge event in this integrated circuit, provides a guiding path with two-way admittance characteristic.

27. integrated circuit as claimed in claim 23 is characterized in that, when element charge mode electrostatic discharge event took place, this tertiary circuit had a conducting voltage.

28. integrated circuit as claimed in claim 23 is characterized in that, when this integrated circuit normal manipulation mode, this first circuit and this second circuit are in closing state.

29. integrated circuit as claimed in claim 23, it is characterized in that, when element charge mode electrostatic discharge event took place, state and this second circuit that this first circuit is in conducting were in closing state, and the 3rd end of this of this tertiary circuit first end and this tertiary circuit is equipotential.

30. integrated circuit as claimed in claim 23, it is characterized in that, when element charge mode electrostatic discharge event took place, state and this first circuit that this second circuit is in conducting were in closing state, and the 3rd end of this of this tertiary circuit second end and this tertiary circuit is equipotential.

31. the integrated circuit with element charge mode electrostatic discharge protective is characterized in that, comprises:

One substrate;

At least one the first transistor, it is arranged in this substrate, wherein this transistor comprises one and has first doped region and that first type mixes and have second doped region that this first type mixes, wherein this have first doped region that this first type mixes and this have one of second doped region that this first type mixes be electrically connected at one first earthing potential of an input/output circuitry or an internal circuit and another this have one second earthing potential that doped region that this first type mixes is electrically connected at another internal circuit;

One has first doped region that second type mixes, and it is arranged in this substrate, and wherein this first doped region with the doping of second type is electrically connected at one of this first earthing potential and this second earthing potential;

Wherein when this integrated circuit normal manipulation mode, this at least one the first transistor is in the state of conducting; And

Wherein when element charge mode electrostatic discharge event takes place, the guiding path that this at least one the first transistor is in closing state and a parasitic two-way admittance is provided is to discharge stored charge.

32. integrated circuit as claimed in claim 31, it is characterized in that, this substrate more comprises a wellblock, and wherein this first doped region, this second doped region with this first type doping and this first doped region with this second type doping with this first type doping is arranged in this wellblock.

33. integrated circuit as claimed in claim 31 is characterized in that, more comprises:

One transistor seconds, it is arranged in this substrate, and wherein this transistor seconds has the structure identical with this at least one the first transistor; And

One has second doped region that this second type mixes, and it is arranged in this substrate, and wherein this second doped region with this second type doping is electrically connected at another of this first earthing potential and this second earthing potential.

34. integrated circuit as claimed in claim 33 is characterized in that, more comprises:

One first wellblock, it is arranged in this substrate, and wherein this of this at least one the first transistor has first doped region that this first type mixes and this and have this first type second doped region that mixes and first doped region that this has this second type doping and be positioned at this first wellblock.

35. integrated circuit as claimed in claim 34 is characterized in that, more comprises:

One second wellblock, it is arranged in this substrate, and wherein this of this transistor seconds has first doped region that this first type mixes and this and has this first type second doped region that mixes and first doped region that this has this second type doping and be positioned at this second wellblock.

36. integrated circuit as claimed in claim 31 is characterized in that, more comprises:

One first diode structure, it comprises one and has the 3rd doped region that this first type mixes and this has first doped region that this second type mixes.

37. integrated circuit as claimed in claim 36 is characterized in that, more comprises:

One first wellblock, wherein this has the 3rd doped region that this first type mixes and is arranged in this first wellblock and this and has first doped region that this second type mixes and partly be arranged in this first wellblock.

38. integrated circuit as claimed in claim 37 is characterized in that, more comprises:

One has the doped region that this second type mixes, and it is electrically connected at this and has the 3rd doped region that this first type mixes.

39. integrated circuit as claimed in claim 36 is characterized in that, more comprises:

One second diode structure, it comprises another the 3rd doped region and one with this first type doping and has second doped region that this second type mixes, and wherein this second doped region with this second type doping is electrically connected at another of this first earthing potential and this second earthing potential.

40. integrated circuit as claimed in claim 39 is characterized in that, more comprises:

One second wellblock, wherein this another have the 3rd doped region that this first type mixes and be arranged in this second wellblock and this and have second doped region that this second type mixes and partly be arranged in this second wellblock.

41. integrated circuit as claimed in claim 40 is characterized in that, more comprises:

One has the doped region that this second type mixes, its be electrically connected at this another have the 3rd doped region that this first type mixes.