CN107622999B - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
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- CN107622999B CN107622999B CN201610561689.4A CN201610561689A CN107622999B CN 107622999 B CN107622999 B CN 107622999B CN 201610561689 A CN201610561689 A CN 201610561689A CN 107622999 B CN107622999 B CN 107622999B
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Abstract
The invention discloses an electrostatic discharge protection circuit, which is connected between a first wafer and a second wafer, wherein the first wafer comprises a through silicon via, and the second wafer comprises an internal chip circuit, and the electrostatic discharge protection circuit comprises: the resistive random access memory comprises a resistive random access memory, an anti-static element and a switch control unit. According to the invention, the electrostatic discharge protection circuit composed of the switch control unit, the anti-static element and the resistive random access memory can well realize the electrostatic discharge process and protect the integrated circuit; and after the electrostatic discharge is finished, the resistive random access memory is controlled to be in a high-resistance state through the switch control unit, so that the electrostatic discharge protection circuit can be completely disconnected from the integrated circuit, the parasitic effect of the electrostatic discharge protection circuit is completely eliminated, and the electrostatic protection capability is improved.
Description
Technical Field
The invention relates to the field of integrated circuit electrostatic protection circuit design, in particular to an electrostatic discharge protection circuit.
Background
As system integrated chips have grown larger in scale, three-dimensional integrated circuits (3 DICs) have become viable alternatives to achieve the requisite integration densities. Through Silicon Vias (TSVs) are widely used in 3 DICs to implement vertical interconnections. However, in the 3DIC manufacturing process, when the metal wires of the wafer with the TSVs in each stack layer and another wafer are connected with each other, the wafer with the TSVs is often subjected to a mechanical thinning process, and corresponding electrostatic charges are generated on the wafer with the TSVs due to factors such as mechanical friction, and then when the stacks are combined, the electrostatic charges accumulated in the stacks flow at the same time to generate a transient large current, thereby forming a discharge behavior with a high current peak and a short discharge time. Due to the high voltage of the Static electricity, ESD (Electro-Static discharge) may have destructive consequences on the 3DIC, resulting in failure of the integrated circuit. Therefore, in order to protect the integrated circuit from ESD, an ESD protection circuit should be designed in the integrated circuit to prevent the integrated circuit from being damaged by ESD.
In the prior art, the corresponding ESD protection circuit is composed of a series of resistors, diodes and a PNP bipolar junction transistor. However, the ESD protection circuit has a delay in discharging and produces parasitic effects, including parasitic capacitance and/or parasitic inductance, which reduce the electrostatic protection capability.
Therefore, in view of the above technical problems, there is a need for an improved esd protection circuit.
Disclosure of Invention
The invention provides an electrostatic discharge protection circuit, which can effectively improve the electrostatic discharge protection capability and eliminate parasitic capacitance and/or parasitic inductance generated by the electrostatic discharge protection circuit.
In order to solve the above technical problem, an esd protection circuit provided by the present invention is connected between a first wafer and a second wafer, wherein the first wafer includes through silicon vias, and the second wafer includes internal chip circuits, and the esd protection circuit includes:
the first unit comprises a first resistive random access memory and a first anti-static element, wherein the first end of the first resistive random access memory is connected with the first end of the first anti-static element;
the second unit comprises a second resistive random access memory and a second anti-static element, wherein the first end of the second resistive random access memory is connected with the first end of the second anti-static element, and the second end of the second anti-static element is grounded;
one end of the switch control unit is connected with the second end of the first anti-static element in the first unit;
and the second end of the first resistive random access memory in the first unit and the second end of the second resistive random access memory in the second unit are both connected with the silicon through hole and the internal chip circuit.
Further, in the electrostatic discharge process of the first wafer, the switch control unit controls the first resistive random access memory and the second resistive random access memory to be in a low-resistance state, and when the first wafer is charged with electrostatic positive charges, the electrostatic positive charges are released through the second unit; when the first wafer is charged with the electrostatic negative charges, the electrostatic negative charges are released through the first unit.
Further, after the electrostatic discharge of the first wafer is completed, the switch control unit controls the first resistive random access memory and the second resistive random access memory to be in a high-resistance state, and the electrostatic discharge protection circuit is disconnected from the first wafer and the second wafer.
Optionally, the first anti-static element is any one of a diode, a grounded-gate NMOS transistor, a bipolar junction transistor, and a thyristor.
Preferably, the first anti-static element is a first diode, a cathode of the first diode is connected to the first end of the first resistive random access memory, and an anode of the first diode is connected to the switch control unit.
Optionally, the second anti-static element is any one of a diode, a grounded-gate NMOS transistor, a bipolar junction transistor, and a thyristor.
Preferably, the second anti-static element is a second diode, an anode of the second diode is connected to the first end of the second resistance random access memory, and a cathode of the second diode is grounded.
Furthermore, the switch control unit comprises a PMOS tube, an NMOS tube, a control voltage end and an external voltage end, wherein the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube and is connected with the control voltage end; the source electrode of the PMOS tube is connected with the source electrode of the NMOS tube and is connected with the first anti-static element; the drain electrode of the PMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the external voltage end.
Further, when the first wafer is charged with positive electrostatic charges, the voltage of the control voltage end of the switch control unit is a low potential, and the positive electrostatic charges are released through the second resistive random access memory and the second anti-static element.
Further, when the first wafer is charged with negative electrostatic charges, the voltage of the control voltage end of the switch control unit is a low potential, and the negative electrostatic charges are released through the first resistive random access memory, the first anti-static element and the PMOS transistor.
Further, after the first wafer electrostatic discharge is completed, the voltage of the control voltage end of the switch control unit is a high potential.
Compared with the prior art, the invention has the following beneficial effects:
in the electrostatic discharge protection circuit of the present invention, the electrostatic discharge protection circuit includes a first unit, a second unit, and a switch control unit, the first unit includes a first resistance change memory and a first anti-static element, and a first end of the first resistance change memory is connected to a first end of the first anti-static element; the second unit comprises a second resistive random access memory and a second anti-static element, wherein the first end of the second resistive random access memory is connected with the first end of the second anti-static element, and the second end of the second anti-static element is grounded; one end of the switch control unit is connected with the second end of the first anti-static element in the first unit; and the second end of the first resistive random access memory in the first unit and the second end of the second resistive random access memory in the second unit are both connected with the silicon through hole and the internal chip circuit. The electrostatic discharge protection circuit comprises the switch control unit, the anti-static element and the resistive random access memory, the resistive random access memory has the characteristics of resistance in a low resistance state and a high resistance state (namely resistance switching characteristics), and the characteristic of high electrostatic discharge voltage is combined, so that in the electrostatic discharge process, the switch control unit controls the resistive random access memory to be in the low resistance state, the electrostatic discharge process can be well realized, and the integrated circuit is protected. And after the electrostatic discharge is finished, the switch control unit controls the resistive random access memory to be in a high-resistance state, so that the electrostatic discharge protection circuit can be completely disconnected from the integrated circuit, the parasitic effect of the electrostatic discharge protection circuit is completely eliminated, and the electrostatic protection capability is improved.
Drawings
FIG. 1 is a schematic diagram of an ESD protection circuit according to an embodiment of the present invention;
FIGS. 2 a-2 b are schematic diagrams illustrating the current flowing during the ESD process of the ESD protection circuit according to the present invention;
fig. 3 a-3 b are schematic structural diagrams of the esd protection circuit according to the present invention after esd is completed.
Detailed Description
The electrostatic discharge protection circuit of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that those skilled in the art can modify the invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The present invention provides an esd protection circuit connected between a first wafer and a second wafer, the first wafer including through silicon vias, the second wafer including internal chip circuits, the esd protection circuit comprising: the first unit comprises a first resistive random access memory and a first anti-static element, wherein the first end of the first resistive random access memory is connected with the first end of the first anti-static element;
the second unit comprises a second resistive random access memory and a second anti-static element, wherein the first end of the second resistive random access memory is connected with the first end of the second anti-static element, and the second end of the second anti-static element is grounded;
one end of the switch control unit is connected with the second end of the first anti-static element in the first unit;
and the second end of the first resistive random access memory in the first unit and the second end of the second resistive random access memory in the second unit are both connected with the silicon through hole and the internal chip circuit.
According to the invention, the switch control unit, the anti-static element and the resistive random access memory are adopted to form the electrostatic discharge protection circuit, the resistive random access memory has the characteristics of resistance in a low resistance state and a high resistance state (namely resistance switching characteristics) and is combined with the characteristic of very high electrostatic discharge voltage, and in the electrostatic discharge process, the switch control unit is used for controlling the resistive random access memory to be in the low resistance state, so that the electrostatic discharge process of the first wafer can be well realized, and the integrated circuit is protected. And after the electrostatic discharge of the first wafer is finished, the switch control unit controls the resistive random access memory to be in a high-resistance state, so that the electrostatic discharge protection circuit can be completely disconnected from the integrated circuit, the parasitic effect of the electrostatic discharge protection circuit is completely eliminated, and the electrostatic protection capability is improved.
The following examples of the esd protection circuit are presented to clearly illustrate the content of the present invention, and it should be understood that the content of the present invention is not limited to the following examples, and other modifications by conventional technical means of those skilled in the art are within the scope of the idea of the present invention.
Referring to fig. 1, a schematic structural diagram of an esd protection circuit according to an embodiment of the present invention is shown, where the esd protection circuit is connected between a first wafer 0 and a second wafer 2, the first wafer 0 includes through silicon vias, and the second wafer 2 includes internal chip circuits, and specifically includes:
the first unit 11, the first unit 11 includes a first resistance random access memory 111 and a first anti-static element, the first anti-static element may be any one of a diode, a grounded-gate NMOS transistor, a bjt and a scr, preferably, in this embodiment, the first anti-static element is a first diode 112, and a first end of the first resistance random access memory 111 is connected to a negative electrode of the first diode 112;
the second unit 12, where the second unit 12 includes a second resistance random access memory 121 and a second anti-static element, the second anti-static element may be any one of a diode, a gate grounded NMOS transistor, a bipolar junction transistor, and a thyristor, and preferably, in this embodiment, the second anti-static element is a second diode 122, a first end of the second resistance random access memory 121 is connected to an anode of the second diode 122, and a cathode of the second diode 122 is grounded;
a switch control unit 13, in this embodiment, the switch control unit 13 includes a PMOS transistor 131, an NMOS transistor 132, a control voltage terminal V and an external voltage terminal VsetThe gate of the PMOS transistor 131 is connected to the gate of the NMOS transistor 132, and is connected to the control voltage terminal V; the source of the PMOS transistor 131 is connected to the source of the NMOS transistor 132, and is connected to the positive electrode of the first diode 112; the drain of the PMOS tube 131 is grounded, and the drain of the NMOS tube 132 is connected with the external voltage end Vset(ii) a A second end of the first resistance random access memory 111 in the first unit 11 and a second end of the second resistance random access memory 121 in the second unit 12 are both connected to the first wafer 0 and the second wafer 2.
The operation of the esd protection circuit of the present invention is further explained below to more clearly illustrate the present invention.
When the first wafer 0 is in the electrostatic discharge process:
referring to fig. 2a, when the first wafer 0 is charged with positive electrostatic charges, the discharge voltage of the positive electrostatic charges is very high (up to kilovolt), and the voltage of the control voltage terminal V of the switch control unit 13 is controlled to be a low potential VlowWhen the PMOS transistor 131 is turned on and the NMOS transistor 132 is turned off, the second resistance random access memory 121 is in a low resistance state (e.g., a resistance of about several tens or several hundreds ohms) under an electrostatic high voltage, and a current flow direction as shown by a dotted arrow in the figure is formed in the electrostatic discharge protection circuit, that is, the electrostatic positive charge is completely discharged through the second resistance random access memory 121 and the second diode 122;
as shown in fig. 2b, when the first wafer 0 is negatively charged, the voltage of the control voltage terminal V of the switch control unit 13 is controlled to be a low potential VlowThat is, the PMOS tube 131 is conductedIf the NMOS tube 132 is not turned on, the first resistance random access memory 111 is in a resistance low resistance state under the electrostatic high voltage, so that the electrostatic negative charges are completely released through the first resistance random access memory 111, the first diode 112 and the PMOS tube 131, and the electrostatic discharge process is shown by a dotted arrow in the figure.
Therefore, when the first wafer 0 is in the process of electrostatic discharge, the discharge voltage of the electrostatic charge is very high, and the voltage of the control voltage terminal V of the switch control unit 13 is controlled to be a low potential VlowThat is, when the PMOS transistor 131 is turned on and the NMOS transistor 132 is turned off, the first resistive random access memory 111 or the second resistive random access memory 121 is in a low resistance state, and the electrostatic charge is completely discharged through the electrostatic discharge protection circuit. Therefore, the electrostatic discharge protection circuit formed by the switch control unit 13, the anti-static element and the resistive random access memory can well realize the electrostatic discharge process and protect the integrated circuit.
After the electrostatic discharge of the first wafer 0 is completed:
the first wafer 0 and the second wafer 2 are combined, and as shown in fig. 3a, the voltage of the control voltage terminal V of the switch control unit 13 is controlled to be a high potential VhighThat is, the PMOS transistor 131 is not turned on, and the NMOS transistor 132 is turned on, at this time, since there is an external voltage terminal VsetThere is a transient current (the current flow is shown by a dotted arrow in the figure) from the NMOS tube 132 to flow through the first diode 112, the first resistance random access memory 111, the second resistance random access memory 121 and the second diode 122. However, by controlling the external voltage terminal V of the switch control unit 13setThe first resistance random access memory 111 and the second resistance random access memory 121 can be in a resistance high state (for example, the resistance exceeds several tens of mega ohms), and the esd protection circuit is completely disconnected from the first wafer 0 and the second wafer 2, as shown in fig. 3 b.
Therefore, after the electrostatic discharge of the first wafer 0 is completed, the process of changing the first resistive random access memory 111 and the second resistive random access memory 121 from the low-resistance state to the high-resistance state can be realized through the switch control unit 13 of the electrostatic discharge protection circuit, and finally, the electrostatic discharge protection circuit is completely disconnected from the first wafer 0 and the second wafer 2, so that the parasitic effect of the electrostatic discharge protection circuit is completely eliminated, and the electrostatic protection capability is improved.
In addition, when the electrostatic discharge protection circuit is required to perform electrostatic discharge protection on the integrated circuit again, the electrostatic discharge protection circuit can realize the process of the resistive random access memory returning from the high resistance state to the low resistance state by controlling the voltage of the external voltage end of the switch control unit. The implementation of the process is based on the characteristics of the resistive random access memory, and can be understood by those skilled in the art, which is not described herein.
In summary, in the esd protection circuit of the present invention, the esd protection circuit includes a first unit, a second unit and a switch control unit, the first unit includes a first resistance random access memory and a first anti-static element, and a first end of the first resistance random access memory is connected to a first end of the first anti-static element; the second unit comprises a second resistive random access memory and a second anti-static element, wherein the first end of the second resistive random access memory is connected with the first end of the second anti-static element, and the second end of the second anti-static element is grounded; one end of the switch control unit is connected with the second end of the first anti-static element in the first unit; and the second end of the first resistive random access memory in the first unit and the second end of the second resistive random access memory in the second unit are both connected with the silicon through hole and the internal chip circuit. The electrostatic discharge protection circuit is formed by the switch control unit, the anti-static element and the resistive random access memory, the resistive random access memory is controlled to be in a low-resistance state by the switch control unit in the electrostatic discharge process by utilizing the characteristic that the resistive random access memory has a low-resistance state and a high-resistance state (namely the resistance switch characteristic) and combining the characteristic that the electrostatic discharge voltage is very high, and the electrostatic discharge process of the first wafer can be well realized to protect the integrated circuit. And after the electrostatic discharge of the first wafer is finished, the switch control unit controls the resistive random access memory to be in a high-resistance state, so that the electrostatic discharge protection circuit can be completely disconnected from the integrated circuit, the parasitic effect of the electrostatic discharge protection circuit is completely eliminated, and the electrostatic protection capability is improved.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (10)
1. An ESD protection circuit connected between a first wafer and a second wafer, the first wafer including through-silicon vias and the second wafer including internal chip circuitry, comprising:
the first unit comprises a first resistive random access memory and a first anti-static element, wherein the first end of the first resistive random access memory is connected with the first end of the first anti-static element;
the second unit comprises a second resistive random access memory and a second anti-static element, wherein the first end of the second resistive random access memory is connected with the first end of the second anti-static element, and the second end of the second anti-static element is grounded;
one end of the switch control unit is connected with the second end of the first anti-static element in the first unit, the switch control unit comprises a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube, a control voltage end and an external voltage end, and the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube and is connected with the control voltage end; the source electrode of the PMOS tube is connected with the source electrode of the NMOS tube and is connected with the first anti-static element; the drain electrode of the PMOS tube is grounded, and the drain electrode of the NMOS tube is connected with the external voltage end;
and the second end of the first resistive random access memory in the first unit and the second end of the second resistive random access memory in the second unit are both connected with the silicon through hole and the internal chip circuit.
2. The esd protection circuit of claim 1, wherein: in the electrostatic discharge process of the first wafer, the switch control unit controls the first resistive random access memory and the second resistive random access memory to be in a low-resistance state, and when the first wafer is charged with electrostatic positive charges, the electrostatic positive charges are released through the second unit; when the first wafer is charged with the electrostatic negative charges, the electrostatic negative charges are released through the first unit.
3. The esd protection circuit of claim 1, wherein: after the electrostatic discharge of the first wafer is completed, the switch control unit controls the first resistive random access memory and the second resistive random access memory to be in a high-resistance state, and the electrostatic discharge protection circuit is disconnected with the first wafer and the second wafer.
4. The electrostatic discharge protection circuit of any of claims 1-3, wherein: the first anti-static element is any one of a diode, a grid grounding NMOS tube, a bipolar junction transistor and a controllable silicon.
5. The esd protection circuit of claim 4, wherein: the first anti-static element is a first diode, the negative electrode of the first diode is connected with the first end of the first resistive random access memory, and the positive electrode of the first diode is connected with the switch control unit.
6. The electrostatic discharge protection circuit of any of claims 1-3, wherein: the second anti-static element is any one of a diode, a grid grounding NMOS tube, a bipolar junction transistor and a controllable silicon.
7. The esd protection circuit of claim 6, wherein: the second anti-static element is a second diode, the anode of the second diode is connected with the first end of the second resistive random access memory, and the cathode of the second diode is grounded.
8. The esd protection circuit of claim 1, wherein: when the first wafer is charged with the static positive charges, the voltage of the control voltage end of the switch control unit is low potential, and the static positive charges are released through the second resistive random access memory and the second anti-static element.
9. The esd protection circuit of claim 1, wherein: when the first wafer is charged with the electrostatic negative charges, the voltage of the control voltage end of the switch control unit is low potential, and the electrostatic negative charges are released through the first resistive random access memory, the first anti-static element and the PMOS tube.
10. The esd protection circuit of claim 1, wherein: after the first wafer electrostatic discharge is completed, the voltage of the control voltage end of the switch control unit is high potential.
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| CN201610561689.4A CN107622999B (en) | 2016-07-15 | 2016-07-15 | Electrostatic discharge protection circuit |
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| CN201610561689.4A CN107622999B (en) | 2016-07-15 | 2016-07-15 | Electrostatic discharge protection circuit |
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| CN107622999B true CN107622999B (en) | 2020-06-02 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187416A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Integrated circuit with element charging mode electrostatic discharge protection |
| CN104218552A (en) * | 2013-05-31 | 2014-12-17 | 中国科学院微电子研究所 | Overvoltage and overcurrent protection element and overvoltage and overcurrent protection circuit |
| CN104737288A (en) * | 2012-10-05 | 2015-06-24 | 高通股份有限公司 | Electrostatic protection for stacked multi-chip integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050088794A1 (en) * | 2003-10-23 | 2005-04-28 | International Business Machines Corporation | Removeable ESD for improving I/O pin bandwidth |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187416A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Integrated circuit with element charging mode electrostatic discharge protection |
| CN104737288A (en) * | 2012-10-05 | 2015-06-24 | 高通股份有限公司 | Electrostatic protection for stacked multi-chip integrated circuits |
| CN104218552A (en) * | 2013-05-31 | 2014-12-17 | 中国科学院微电子研究所 | Overvoltage and overcurrent protection element and overvoltage and overcurrent protection circuit |
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