CN103187416B

CN103187416B - Integrated circuit with element charging mode electrostatic discharge protection

Info

Publication number: CN103187416B
Application number: CN201210587481.1A
Authority: CN
Inventors: 叶致廷; 梁咏智
Original assignee: Industrial Technology Research Institute ITRI
Current assignee: Industrial Technology Research Institute ITRI
Priority date: 2011-12-30
Filing date: 2012-12-28
Publication date: 2015-09-30
Anticipated expiration: 2032-12-28
Also published as: CN103187416A

Abstract

An integrated circuit with device charge mode electrostatic discharge (CDM ESD) protection includes an input/output circuit, at least one device charge mode electrostatic discharge (CDM ESD) protection device, and an internal circuit. The internal circuit further includes at least one through-silicon via (TSV) configured to be coupled between a ground of at least one ground of the input/output circuit and the at least one device charge mode esd protection device, wherein each of the at least one device charge mode esd protection device is coupled between the at least one TSV and a ground of the at least one internal circuit.

Description

There is the integrated circuit of element charge mode electrostatic discharge protective

Technical field

The present invention is about a kind of integrated circuit with element charge mode electrostatic discharge protective.

Background technology

In three-dimensional stacked chip, by the plain conductor of each suprabasil circuit so that each stacking substrate is interconnected, therefore, when this stacked chips is subjected to element charge mode electrostatic discharge event, the stored charge of each stack layer substrate can be confluxed and discharge by the fast strikethrough plain conductor that connects each suprabasil circuit.

But when element charge mode electrostatic discharge event occurs, the electric charge accumulating on each stack layer produces big current in a flash by flowing simultaneously.

As shown in Figure 1, wave mode 11 is the discharging current wave mode of the stored charge of an internal circuit, wave mode 13 is the summation of the discharging current wave mode that the stored charge of the internal circuit of each stack layer discharged in the same time, its element charge mode static discharge current will conflux and concentrate on certain time point, form high current peak and short electric discharge behavior release time.

In order to reduce this instantaneous large-current for the injury of the element in input/output circuitry by element charge mode static discharge, in three-dimensional stacked chip, wish there is a kind of protection mechanism reducing this instantaneous large-current above-mentioned injury.

Summary of the invention

One embodiment of the invention disclose a kind of integrated circuit with element charge mode electrostatic discharge protective, comprise an input/output circuitry and at least one electrostatic discharge protective device, be configured to be coupled between at least one earthing potential of this input/output circuitry and an earthing potential of at least one internal circuit.

Above-mentioned integrated circuit, wherein this at least one electrostatic discharge protective device is coupled between an earthing potential of this at least one internal circuit and an earthing potential of another this at least one internal circuit.

Above-mentioned integrated circuit, wherein this at least one electrostatic discharge protective device comprises an element charge mode electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this element charge mode electrostatic discharge protective device comprises a turnpike formula circuit.

Above-mentioned integrated circuit, wherein this turnpike formula circuit is when this integrated circuit normal manipulation mode, is a guiding path with low resistance.

Above-mentioned integrated circuit, wherein this turnpike formula circuit is when element charge mode electrostatic discharge event occurs, is a guiding path with two-way admittance characteristic.

Above-mentioned integrated circuit, wherein this turnpike formula circuit is when element charge mode electrostatic discharge event occurs, and this turnpike formula circuit has a conducting voltage.

Above-mentioned integrated circuit, wherein more comprises: between the earthing potential that at least one through-silicon-via is coupled to this at least one earthing potential of this input/output circuitry and this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein between this at least one through-silicon-via earthing potential of being coupled to this at least one internal circuit and this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is coupled to another this at least one through-silicon-via.

Another embodiment of the present invention discloses a kind of integrated circuit with element charge mode electrostatic discharge protective, comprises an input/output circuitry, at least one electrostatic discharge protective device and at least one through-silicon-via.Wherein between each this at least one through-silicon-via earth terminal of being coupled to this input/output circuitry and this at least one electrostatic discharge protective device, each this at least one electrostatic discharge protective device is configured to be coupled between this at least one through-silicon-via and an earth terminal of this at least one internal circuit.

Above-mentioned integrated circuit, wherein between this at least one through-silicon-via earthing potential of being configured to be coupled to this at least one internal circuit and this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is configured to be coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

Above-mentioned integrated circuit, wherein this at least one through-silicon-via is configured to be coupled to another this at least one through-silicon-via.

Above-mentioned integrated circuit, wherein when this integrated circuit normal manipulation mode, this turnpike formula circuit is a guiding path with low resistance.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event occurs, this turnpike formula circuit is a guiding path with two-way admittance characteristic.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event occurs, this turnpike formula circuit has a conducting voltage.

One more embodiment of the present invention discloses a kind of integrated circuit of element charge mode electrostatic discharge protective device, comprise one and there is a first end, first circuit of one second end and one the 3rd end, wherein this first end of this first circuit is coupled to a power supply, 3rd end of one first earthing potential or an internal circuit and this first circuit that this second end of this first circuit is coupled to an input/output circuitry is coupled to one second earthing potential of another internal circuit, one has a first end, the second circuit of one second end and one the 3rd end, wherein this first end of this second circuit is coupled to this power supply, the 3rd end that this second end of this second circuit is coupled to this second earthing potential and this second circuit is coupled to this first earthing potential and one and has a first end, the tertiary circuit of one second end and one the 3rd end, wherein the 3rd end of this tertiary circuit is coupled to this power supply, this first end that this second end of this tertiary circuit is coupled to this second earthing potential and this tertiary circuit is coupled to this first earthing potential.

Above-mentioned integrated circuit, wherein this tertiary circuit comprises a switch.

Above-mentioned integrated circuit, wherein this tertiary circuit is when this integrated circuit normal manipulation mode, provides the guiding path that has a two-way admittance characteristic of low resistance.

Above-mentioned integrated circuit, wherein this tertiary circuit in this integrated circuit meet with element charge mode electrostatic discharge event occur time, the guiding path that has a two-way admittance characteristic is provided.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event occurs, this tertiary circuit has a conducting voltage.

Above-mentioned integrated circuit, wherein when this integrated circuit normal manipulation mode, this first circuit and this second circuit are in the state of closedown.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event occurs, this first circuit is in the state that the state of conducting and this second circuit are in closedown, and this first end of this tertiary circuit and the 3rd end of this tertiary circuit are equipotential.

Above-mentioned integrated circuit, wherein when element charge mode electrostatic discharge event occurs, this second circuit is in the state that the state of conducting and this first circuit are in closedown, and this second end of this tertiary circuit and the 3rd end of this tertiary circuit are equipotential.

One more embodiment of the present invention discloses a kind of integrated circuit of element charge mode electrostatic discharge protective device, comprise a substrate, at least one the first transistor and have Second-Type doping the first doped region.This at least one the first transistor is arranged in this substrate, wherein this transistor comprises the second doped region that first doped region and with the first type doping has the doping of this first type, and wherein this has the first doped region of the first type doping and this has one of the second doped region of this first type doping and is electrically connected at one second earth terminal that the first doped region that one first earth terminal of an input/output circuitry or an internal circuit and another have a doping of this first type is electrically connected at another internal circuit.This has the first doped region of Second-Type doping, and it is arranged in this substrate, and wherein this first doped region with Second-Type doping is electrically connected at one of this first earth terminal or this second earth terminal.Wherein when this integrated circuit normal manipulation mode, this at least one the first transistor be in conducting state and wherein when element charge mode electrostatic discharge event occurs, this at least one the first transistor is in the state of closedown and provides the conducting path of a parasitic two-way admittance to discharge stored charge.

Above-mentioned integrated circuit, wherein this substrate more comprises a well region, wherein this have this first type doping the first doped region, this have this first type doping the second doped region and this have this Second-Type doping the first doped region be arranged in this well region.

Above-mentioned integrated circuit, wherein more comprises: a transistor seconds, and it is arranged in this substrate, and wherein this transistor seconds has the identical structure of the first transistor at least one with this; And the second doped region that has a doping of this Second-Type, it is arranged in this substrate, and wherein this second doped region with the doping of this Second-Type is electrically connected at another of this first earthing potential and this second earthing potential.

Above-mentioned integrated circuit, wherein more comprise: one first well region, it is arranged in this substrate, and this of wherein this at least one the first transistor has the first doped region of this first type doping and this has the second doped region of this first type doping and this has the first doped region that this Second-Type adulterates and is positioned at this first well region.

Above-mentioned integrated circuit, wherein more comprise: one second well region, it is arranged in this substrate, and this of wherein this transistor seconds has the first doped region of this first type doping and this has the second doped region of this first type doping and this has the first doped region that this Second-Type adulterates and is positioned at this second well region.

Above-mentioned integrated circuit, wherein more comprises: one first diode structure, its comprise one have this first type doping the 3rd doped region and this have this Second-Type doping the first doped region.

Above-mentioned integrated circuit, wherein more comprises: one first well region, wherein this have this first type doping the 3rd doped region be arranged in this first well region and this have this Second-Type doping the first doped region part be arranged in this first well region.

Above-mentioned integrated circuit, wherein more comprises: one have this Second-Type doping doped region, its be electrically connected at this have this first type doping the 3rd doped region.

Above-mentioned integrated circuit, wherein more comprises: a transistor seconds, and it is arranged in this substrate, and wherein this transistor seconds has the identical structure of the first transistor at least one with this; And one second diode structure, it comprises the second doped region that another the 3rd doped region and one with the doping of this first type has the doping of this Second-Type, and wherein this second doped region with the doping of this Second-Type is electrically connected at another of this first earthing potential and this second earthing potential.

Above-mentioned integrated circuit, wherein more comprises: one second well region, wherein this another have this first type doping the 3rd doped region be arranged in this second well region and this have this Second-Type doping the second doped region part be arranged in this second well region.

Above-mentioned integrated circuit, wherein more comprises: one have this Second-Type doping doped region, its be electrically connected at this another have this first type doping the 3rd doped region.

Use protection mechanism of the present invention, instantaneous large-current can be reduced for the injury of the element in input/output circuitry by element charge mode static discharge.

Those skilled in the art should understand, and the concept hereafter disclosed and specific embodiment can be used as basis and revised or design other structure or technique quite easily and realize the object identical with the present invention.Those skilled in the art also should understand, and the construction of this kind of equivalence also cannot depart from the spirit and scope of the present invention that claims propose.

Accompanying drawing explanation

Fig. 1 is the wave mode schematic diagram of the high current peak of element charge mode static discharge;

Fig. 2 is the static discharge current wave mode schematic diagram that one of one embodiment of the invention has the integrated circuit of element charge mode electrostatic discharge protective device;

One of Fig. 3 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

One of Fig. 4 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

One of Fig. 5 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

One of Fig. 5-1 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective;

Another of Fig. 5-2 one embodiment of the invention has the schematic diagram of the integrated circuit of element charge mode electrostatic discharge protective

The schematic diagram of the integrated circuit of a kind of element charge mode electrostatic discharge protective of Fig. 6 one embodiment of the invention;

The integrated circuit schematic of a kind of element charge mode electrostatic discharge protective device of Fig. 7 one embodiment of the invention;

The schematic diagram of the integrated circuit of a kind of element charge mode electrostatic discharge protective device of Fig. 8 one embodiment of the invention;

The schematic diagram of the integrated circuit of a kind of element charge mode electrostatic discharge protective device of Fig. 9 another embodiment of the present invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 10 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 11 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 12 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 13 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 14 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 15 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 16 one embodiment of the invention;

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 17 one embodiment of the invention; And

The generalized section of the semiconductor structure of a kind of element charge mode electrostatic discharge protective device of Figure 18 one embodiment of the invention.

Wherein, Reference numeral:

Resd resistance

Mp1 P-type crystal pipe

Mn1 N-type transistor

11 wave modes

13 wave modes

21 wave modes

30 integrated circuits with element charge mode electrostatic discharge protective

31 element charge mode electrostatic discharge protective devices

38 input/output circuitries

39 internal circuits

31 element charge mode electrostatic discharge protective devices

40 integrated circuits with element charge mode electrostatic discharge protective

41 element charge mode electrostatic discharge protective devices

42 element charge mode electrostatic discharge protective devices

46 stack layers

46-1 first order stack layer

46-2 second level stack layer

49-1 first internal circuit

49-2 second internal circuit

50 integrated circuits with element charge mode electrostatic discharge protective

50-1 has the integrated circuit of element charge mode electrostatic discharge protective

50-2 has the integrated circuit of element charge mode electrostatic discharge protective

51 element charge mode electrostatic discharge protective devices

52 element charge mode electrostatic discharge protective devices

53-1 through-silicon-via

53-2 through-silicon-via

561 stack layers

56-1 level stack layer

562 stack layers

56-2 level stack layer

58-1 through-silicon-via

58-2 through-silicon-via

59-1 first internal circuit

59-2 second internal circuit

The integrated circuit of 60 element charge mode electrostatic discharge protectives

61 element charge mode electrostatic discharge protective devices

62 element charge mode electrostatic discharge protective devices

661 stack layers

66-1 level stack layer

662 stack layers

66-2 level stack layer

69-1 first internal circuit

69-2 second internal circuit

The integrated circuit of 70 element charge mode electrostatic discharge protective devices

71 first circuit

The first end of 71-1 first circuit

Second end of 71-2 first circuit

3rd end of 71-3 first circuit

72 second circuits

The first end of 72-1 second circuit

Second end of 72-2 second circuit

3rd end of 72-3 second circuit

73 tertiary circuits

The first end of 73-1 tertiary circuit

Second end of 73-2 tertiary circuit

3rd end of 73-3 tertiary circuit

The integrated circuit of 80 element charge mode electrostatic discharge protective devices

81 the first transistors

82 1 transistor secondses

83-1 third transistor

83-2 third transistor

89 resistance

The integrated circuit of 90 element charge mode electrostatic discharge protective devices

91 transistors

92 transistors

93-1 transistor

93-2 transistor

The semiconductor structure of 101 element charge mode electrostatic discharge protective devices

The semiconductor structure of 102 element charge mode electrostatic discharge protective devices

110 metal-oxide-semiconductor field effect transistor structures

111 first heavily doped regions

112 second heavily doped regions

113 gate regions

120 metal-oxide-semiconductor field effect transistor structures

121 first N-shaped doped regions

122 second N-shaped doped regions

123 gate regions

141 p-type doped regions

142 p-type doped regions

150 substrates

The semiconductor structure of 201 element charge mode electrostatic discharge protective devices

The semiconductor structure of 202 element charge mode electrostatic discharge protective devices

210 metal-oxide-semiconductor field effect transistor structures

211 first p-type doped regions

212 second p-type doped regions

213 gate regions

220 metal-oxide-semiconductor field effect transistor structures

221 first p-type doped regions

222 second p-type doped regions

223 gate regions

241 N-shaped doped regions

242 N-shaped doped regions

251 N well regions

252 N well regions

The semiconductor structure of 300 element charge mode electrostatic discharge protective devices

301 first time structure

302 second time structures

351 first N-type well region

352 second N-type well region

The semiconductor structure of 400 element charge mode electrostatic discharge protective devices

401 first time structure

402 second time structures

451 first N-type well region

452 second N-type well region

471 second diode structures

472 second N-type well region

481 the 3rd N-shaped doped regions

482 p-type doped regions

491 the 3rd N-shaped doped regions

492 p-type doped regions

The semiconductor of 500 element charge mode electrostatic discharge protective devices

501 first time structure

502 second time structures

The semiconductor structure of 601 element charge mode electrostatic discharge protective devices

The semiconductor structure of 602 element charge mode electrostatic discharge protective devices

631 first diodes

632 second diodes

650 deep-well region

651 N-type well region

652 N-type well region

681 first diodes

682 second diodes

Embodiment

The invention provides a kind of integrated circuit with element charge mode electrostatic discharge protective stored charge to be discharged step by step.

Fig. 2 is the static discharge current wave mode schematic diagram that one of one embodiment of the invention has the integrated circuit of element charge mode electrostatic discharge protective.

As shown in Figure 2, wave mode 11 is respectively the discharging current wave mode of the stored charge of an internal circuit, wave mode 13 is the summation of the discharging current wave mode that the stored charge of each internal circuit discharged in the same time, and wave mode 21 is then for having the static discharge current wave mode of the integrated circuit of element charge mode electrostatic discharge protective.

As shown in wave mode 21, this integrated circuit with element charge mode electrostatic discharge protective is when element charge mode electrostatic discharge event occurs, the peak value of discharging current can be reduced and extend release time, to avoid excessive electric current, one input/output circuitry being damaged.

One of Fig. 3 one embodiment of the invention has the schematic diagram of the integrated circuit 30 of element charge mode electrostatic discharge protective.As shown in Figure 3, this integrated circuit 30 with element charge mode electrostatic discharge protective comprises input/output circuitry 38, element charge mode electrostatic discharge protective device (or claiming CDM Gating) 31 and an internal circuit 39.This input/output circuitry 38 in order to transmit a pad (Pad) and this integrated circuit 30 an internal circuit between signal, and ESD (Electrostatic Discharge) clamp circuit (sign) can be comprised to suppress the static discharge of this integrated circuit 30.

This input/output circuitry 38 can other forms to present and not by embodiments of the invention are limit.This element charge mode electrostatic discharge protective device 31 is coupled between one first earth terminal (example: one first reference voltage or earthing potential VSS or VSSIO) of this input/output circuitry 38 and one second earth terminal (example a: earthing potential of the second reference voltage or this internal circuit 39).

This element charge mode electrostatic discharge protective device 31 comprises a turnpike formula circuit, and wherein this turnpike formula circuit is when this integrated circuit 30 normal manipulation mode, is a guiding path with low resistance.The resistance of this guiding path depends on the current needs of internal circuit.

The current needs of such as internal circuit is 100mA, and when the cross-pressure allowing to be consumed in turnpike formula circuit is 10mV, can be derived from this resistance is 0.1 ohm, and instead can push away the component size designed size of turnpike formula circuit whereby, this is an embodiment, but not as limit.

And when element charge mode electrostatic discharge event occurs, this turnpike formula circuit has a conducting voltage.This turn-on voltage need be less than grid breakdown voltage or the junction breakdown voltage of inner member, and when the two ends cross-pressure of this turnpike formula circuit exceedes this conducting voltage, the electrostatic charge accumulating on internal circuit can discharge through this turnpike formula circuit.

Such as, when the grid breakdown voltage of inner member is 3V, the design maximum of its conducting voltage need be less than 3V voltage, if with diode be Dao Tong Lu ? element, its conducting voltage is 0.7V, but not as limit.

Now, this element charge mode electrostatic discharge protective device 31 is the charge-conduction path of a two-way admittance, be configured to the stored charge of this internal circuit 39 to be released into this input/output circuitry 38 step by step, to reduce when stored charge flows out this internal circuit 39 in a large number, excessive rush of current caused for this input/output circuitry 38.

Polarity due to the accumulation electrostatic charge of this element charge mode comprises positive or negative polarity, and the conducting path through two-way admittance all can discharge step by step.This element charge mode electrostatic discharge protective device 31 will be specified in the paragraph of Fig. 7 to Fig. 9.

One of Fig. 4 one embodiment of the invention has the schematic diagram of the integrated circuit 40 of element charge mode electrostatic discharge protective.As shown in Figure 4, this integrated circuit 40 with element charge mode electrostatic discharge protective comprises one first internal circuit 49-1, one first element charge mode electrostatic discharge protective device (CDMGating) 41,1 second internal circuit 49-2, at least one second element charge mode electrostatic discharge protective device 42 and this input/output circuitry 38.

Wherein this first element charge mode electrostatic discharge protective device 41, this element charge mode electrostatic discharge protective device 31 is as shown in Figure 3 coupled between one first earth terminal (example: one first reference voltage or earthing potential VSS or VSSIO) of this input/output circuitry 38 and one second earth terminal (example a: earthing potential of the second reference voltage or this first internal circuit 49-1).

Separately, this second element charge mode electrostatic discharge protective device 42 is coupled to this earthing potential of this first internal circuit 49-1 and an earthing potential of this second internal circuit 49-2.

Separately, each this first element charge mode electrostatic discharge protective device 41 and this second element charge mode electrostatic discharge protective device 42 are similar to this element charge mode electrostatic discharge protective device 31 shown in Fig. 3.

This first element charge mode electrostatic discharge protective device 41 and this second element charge mode electrostatic discharge protective device 42 respectively comprise a turnpike formula circuit, this turnpike formula circuit is when this integrated circuit 40 normal manipulation mode, it is a guiding path with low resistance, in order to the conduction of electric current, wherein the resistance of the guiding path of this low resistance depends on the current needs of internal circuit.

Now, this the first element charge mode electrostatic discharge protective device 41 and this second element charge mode electrostatic discharge protective device 42 are the charge-conduction path of a two-way admittance, be configured to the stored charge of this internal circuit to be released into this input/output circuitry 38 step by step, to reduce when stored charge flows out this internal circuit 49-1 and this internal circuit 49-2 in a large number, excessive rush of current caused for this input/output circuitry 38.

Polarity due to the accumulation electrostatic charge of this element charge mode comprises positive or negative polarity, and the conducting path through two-way admittance all can discharge step by step.

One of Fig. 5 one embodiment of the invention has the schematic diagram of the integrated circuit 50 of element charge mode electrostatic discharge protective.In other stack layers, other element charge mode electrostatic discharge protective device and internal circuit is separately comprised compared to this integrated circuit 50 shown in this integrated circuit 40, Fig. 5 shown in Fig. 4.

Specifically, this integrated circuit 50 comprises several stack layer 46,561,562,661 and 662, and this integrated circuit 50 separately comprises several through-silicon-via, and each through-silicon-via is coupled between two stack layers be connected.

In the present embodiment, with five stack layers and four through-silicon-vias for example.But those stack layers and those through-silicon-vias are only example, in other embodiments, the quantity of stack layer and through-silicon-via can greater or less than this example.

Separately, explain the present embodiment for convenience, be vertically coupled to the through-silicon-via 58-1 between this stack layer 561 and 562 and be vertically coupled to through-silicon-via 58-2 between this stack layer 661 and 662 laterally to represent.

Each stack layer 46,561,562,661 and 662 comprises at least one-level stack layer.In the present embodiment, this stack layer 46 comprises first order stack layer 46-1 and second level stack layer 46-2.This first order stack layer 46-1 more comprises this first element charge mode electrostatic discharge protective device 41 and this first internal circuit 49-1, and this second level stack layer 46-2 separately comprises this second element charge mode electrostatic discharge protective device 42 and this second internal circuit 49-2.

Separately, this stack layer 561 comprises one-level stack layer 56-1 and this stack layer 562 comprises one-level stack layer 56-2.This grade of stack layer 56-1 more comprises one first element charge mode electrostatic discharge protective device 51 and one first internal circuit 59-1, and this grade of stack layer 56-2 more comprises one second element charge mode electrostatic discharge protective device 52 and one second internal circuit 59-2.

This first element charge mode electrostatic discharge protective device 51 of this grade of stack layer 56-1 of this stack layer 561 is coupled between one first earth terminal (example: one first reference voltage or earthing potential VSS or VSSIO) of this input/output circuitry 38 and an earth terminal (example a: earthing potential of the second reference voltage or this first internal circuit 59-1) of this first internal circuit 59-1 by a through-silicon-via 53-1.

Separately, this second element charge mode electrostatic discharge protective device 52 of this grade of stack layer 56-2 of this stack layer 562 is coupled between this earthing potential of this first internal circuit 59-1 and an earthing potential of this second internal circuit 59-2 by this through-silicon-via 58-1.

Similarly, this stack layer 661 comprises one-level stack layer 66-1 and this stack layer 662 comprises one-level stack layer 66-2.This grade of stack layer 66-1 more comprises one first element charge mode electrostatic discharge protective device 61 and one first internal circuit 69-1, and this grade of stack layer 66-2 more comprises one second element charge mode electrostatic discharge protective device 62 and one second internal circuit 69-2.

This first element charge mode electrostatic discharge protective device 61 of this grade of stack layer 66-1 of this stack layer 661 is coupled between one first earth terminal (example: one first reference voltage or earthing potential VSS or VSSIO) of this input/output circuitry 38 and an earth terminal (example a: earthing potential of the second reference voltage or this first internal circuit 69-1) of this first internal circuit 69-1 by a through-silicon-via 53-2

Separately, this second element charge mode electrostatic discharge protective device 62 of this grade of stack layer 66-2 of this stack layer 662 is coupled between this earthing potential of this first internal circuit 69-1 and an earthing potential of this second internal circuit 69-2 by this through-silicon-via 58-2.

Another of Fig. 5-1 one embodiment of the invention has the schematic diagram of the integrated circuit 50-1 of element charge mode electrostatic discharge protective.Compared to this integrated circuit 50 shown in Fig. 5, this integrated circuit 50-1 does not have this second level stack layer 46-2 and this first order stack layer 46-1 of this stack layer 46.

Another of Fig. 5-2 one embodiment of the invention has the schematic diagram of the integrated circuit 50-2 of element charge mode electrostatic discharge protective.This through-silicon-via 53-1 compared to this integrated circuit 50-1 shown in Fig. 5-1, this integrated circuit 50-2 is coupled to VSSIO.Embodiment shown in Fig. 5, Fig. 5-1 and Fig. 5-2 is an earth terminal and this at least one charge mode electrostatic discharge protective device that at least one through-silicon-via is coupled at least one earth terminal of this input/output circuitry.

The schematic diagram of the integrated circuit 60 of a kind of element charge mode electrostatic discharge protective of Fig. 6 one embodiment of the invention.Compared to this integrated circuit 50 shown in Fig. 5, the integrated circuit 60 of this element charge mode electrostatic discharge protective separately comprises the another kind of connected mode of this through-silicon-via 53-2.

As shown in Figure 6, this through-silicon-via 53-2 is connected to one end of this through-silicon-via 58-1.In an embodiment, this through-silicon-via 53-2 is coupled to a first end 58a of this through-silicon-via 58-1, and separately, this first end 58a is near this first internal circuit 59-1.Therefore, this stack layer 561 couples this stack layer 562 by this through-silicon-via 58-1 and is coupled to this stack layer 661 by this through-silicon-via 53-2.

In another embodiment, this through-silicon-via 53-2 is coupled to the one second end points 58b of this through-silicon-via 58-1, and wherein this second end points 58b is near this second element charge mode electrostatic discharge protective device 52.Therefore, this stack layer 561 couples this stack layer 562 by this through-silicon-via 58-1 and is coupled to this stack layer 661 by this through-silicon-via 58-1 and 53-2.

Integrated circuit 70 schematic diagram of a kind of element charge mode electrostatic discharge protective device of Fig. 7 one embodiment of the invention.As shown in Figure 7, this element charge mode electrostatic discharge protective device 70 comprises one first circuit 71, second circuit 72 and a tertiary circuit 73.

One first end 71-1 of this first circuit 71 is configured to be coupled to a power supply, one second end 71-2 is configured to be coupled to one first earth terminal (example: one first reference voltage), and one the 3rd end 71-3 is configured to be coupled to one second earth terminal (example: one second reference voltage).This first earth terminal comprises an earthing potential or an internal circuit of an input/output circuitry.This second earth terminal comprises an earthing potential of another internal circuit.

One first end 72-1 of this second circuit 72 is configured to be coupled to this power supply, and one second end 72-2 is configured to be coupled to this second earth terminal, and one the 3rd end 72-3 is configured to be coupled to this first earth terminal.

One the 3rd end 73-3 of this tertiary circuit 73 is configured to be coupled to this power supply, and one second end 73-2 is configured to be coupled to this second earth terminal, and a first end 73-1 is configured to be coupled to this first earth terminal.

Wherein this tertiary circuit 73 is a turnpike formula circuit, and when this integrated circuit 70 normal manipulation mode, have the guiding path of a low resistance, be configured the conduction in order to electric current, wherein the resistance of the guiding path of this low resistance depends on the current needs of internal circuit.

The current needs of such as internal circuit is 100mA, and when the cross-pressure allowing to be consumed in turnpike formula circuit is 10mV, can be derived from this resistance is 0.1 ohm, and instead can push away the component size designed size of turnpike formula circuit whereby, this is an embodiment, but not as limit.Wherein this first circuit and this second circuit are when this integrated circuit normal manipulation mode, are a closed condition.And when element charge mode electrostatic discharge event occurs, this tertiary circuit 73 has a conducting voltage.This conducting voltage need be less than grid breakdown voltage or the junction breakdown voltage of inner member, and when the two ends cross-pressure of this turnpike formula circuit exceedes this conducting voltage, the electrostatic charge accumulating on internal circuit can discharge through this turnpike formula circuit.

Such as, when the grid breakdown voltage of inner member is 3V, the design maximum of its conducting voltage need be less than 3V voltage, if be the element of guiding path with diode, its conducting voltage is 0.7V, but not as limit.

In this embodiment, this tertiary circuit 73 is the conducting path of a two-way admittance, when the two ends cross-pressure of this first end 73-1 of this tertiary circuit 73 and this second end 73-2 of this tertiary circuit 73 exceedes this conducting voltage, electrostatic charge can carry out being released into this input/output circuitry or other internal circuits through this tertiary circuit 73.

Separately, because this tertiary circuit 73 has a conducting voltage, whereby with this stored charge of delayed release, the impact caused with excessive electric current of releiving.

Wherein, in an embodiment, when this integrated circuit component charge mode electrostatic discharge event occurs, this first circuit 71 is a conducting state, this second circuit 72 is a closed condition, to make this first end 73-1 of this tertiary circuit 73 and the 3rd end 73-3 be a conducting state for equipotential or this first circuit 71 are a closed condition and this second circuit 72, to make this second end 73-2 of this tertiary circuit 73 and the 3rd end 73-3 for equipotential.

The schematic diagram of the integrated circuit 80 of a kind of element charge mode electrostatic discharge protective device of Fig. 8 one embodiment of the invention.As shown in Figure 8, the integrated circuit 80 of this element charge mode electrostatic discharge protective device comprises the first transistor 81, transistor seconds 82, third transistor 83-1,83-2 and a resistance 89.

One drain electrode end of this first transistor 81 is coupled to a power supply by this resistance 89, and a gate terminal is coupled to one first earth terminal of an input/output circuitry (not drawing) and one second earth terminal of an internal circuit.

This transistor seconds 82 comprises a drain electrode end, one source pole end and a gate terminal.This drain electrode end is coupled to this power supply by this resistance 89.This source terminal is coupled to this first earth terminal, and this gate terminal is coupled to this second earth terminal.

This third transistor 83-1 comprises a drain electrode end, one source pole end and a gate terminal.This gate terminal is coupled to this power supply by this resistance 89.This drain electrode end is coupled to this first earth terminal, and this source terminal is coupled to this second earth terminal.

Another third transistor 83-2 comprises a drain electrode end, one source pole end and a gate terminal.This gate terminal is coupled to this power supply by this resistance 89.This source terminal is coupled to this first earth terminal, and this drain electrode end is coupled to this second earth terminal.

Each those transistor 81,82,83-1 and 83-2 all comprise N-type metal oxide semiconductcor field effect (NMOS) transistor.Separately, each those third transistor 83-1 and 83-2 respectively comprises a parasitic diode, and wherein this parasitic diode has a conducting voltage, and wherein the voltage range of this conducting voltage is 0.6V ~ 0.7V, but not as limit.

This conducting voltage is less than grid breakdown voltage or the junction breakdown voltage of those third transistor 83-1 and 83-2.When the two ends cross-pressure that this drain electrode (source electrode) end and this source electrode (drain electrode) of this third transistor 83-1 (83-2) are held exceedes this conducting voltage, the electrostatic charge accumulating on internal circuit can through of those third transistor 83-1 and 83-2 to discharge.

When normal manipulation mode, this the first transistor 81 and this transistor seconds 82 are the state of closing, those third transistor 83-1 and 83-2 are the state of conducting, now this element charge mode electrostatic discharge protective device 80 is a guiding path with low resistance, and it is between this first earth terminal and this second earth terminal.

And when element charge mode electrostatic discharge event occurs, those third transistor 83-1 and 83-2 are all the state of closedown.Therefore, the stored charge of this internal circuit via this parasitic diode of those third transistor 83-1 and 83-2 to be released into this input/output circuitry.This parasitic diode has a conducting voltage, and wherein the voltage range of this conducting voltage is 0.6V ~ 0.7V, but not as limit.

Therefore, the potential difference between the first earth terminal and the second earth terminal is equal to or is greater than this conducting voltage, and this stored charge will discharge via this parasitic diode.

The schematic diagram of the integrated circuit 90 of a kind of element charge mode electrostatic discharge protective device of Fig. 9 one embodiment of the invention.Compared to Fig. 8, those transistors of the integrated circuit 90 of element charge mode electrostatic discharge protective device 91,92,93-1 and 93-2 respectively comprise P-type mos field effect (PMOS) transistor.

This tertiary circuit 73 shown in Fig. 7 comprises those third transistor 83-1 and the 83-2 of Fig. 8 example, and separately, this tertiary circuit 73 shown in Fig. 7 also comprises those third transistor 93-1 and the 93-2 of Fig. 9 example.

Those transistors above-mentioned separately can adopt the semiconductor structure embodiment that following Figure 10 ~ Figure 18 invents.

The generalized section of the semiconductor structure 101 of a kind of element charge mode electrostatic discharge protective device of Figure 10 one embodiment of the invention.As shown in Figure 10, this semiconductor structure 101 comprises substrate 150, metal-oxide-semiconductor field effect transistor structure 110 and a heavily doped region 141.

This substrate 150 comprises a silicon substrate, and it has the doping of micro-p-type.

This metal-oxide-semiconductor field effect transistor structure 110 comprises heavily doped region, gate regions 113,1 first 111 and one second heavily doped region 112.Each this first heavily doped region 111 has one first type with this second heavily doped region 112 and adulterates, such as, be N-shaped doping.

Separately, this first heavily doped region 111 and this second heavily doped region 112, can as the source electrode of this metal-oxide-semiconductor field effect transistor structure 110 or drain electrodes depending on its power supply that connects.

141, this heavily doped region has a Second-Type doping, such as, be p-type doping.This heavily doped region 141 is electrically completely cut off by an isolation structures (example: shallow trench isolation is from (Shallow trench isolation, STI)).This second N-shaped doped region 112 and this p-type doped region 141 are all electrically connected at an earth terminal, example a: reference voltage of an internal circuit or an earthing potential.This first N-shaped doped region 111 is electrically connected at an earth terminal, example a: reference voltage of an input/output circuitry or an earthing potential.

When element charge mode electrostatic discharge event occurs, this input/output circuitry, this first N-shaped doped region 111, this substrate 150, this second N-shaped doped region 112 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

Separately, this input/output circuitry, this first N-shaped doped region 111, this substrate 150, this p-type doped region 141 and this internal circuit form another electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

The generalized section of the semiconductor structure 102 of a kind of element charge mode electrostatic discharge protective device of Figure 11 one embodiment of the invention, compared to Figure 10, one first N-shaped doped region 121 of one metal-oxide-semiconductor field effect transistor structure 120 of this semiconductor structure 102 is electrically connected at p-type doped region 142 and an input/output circuitry, and this second N-shaped doped region 122 is then electrically connected at an internal circuit.

Therefore, when element charge mode electrostatic discharge event occurs, this input/output circuitry, this first N-shaped doped region 121, this substrate 150, this second N-shaped doped region 122 and this internal circuit form an electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

Separately, this input/output circuitry, this p-type doped region 142, this substrate 150, this second N-shaped doped region 122 and this internal circuit form another electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

The generalized section of the semiconductor structure 201 of a kind of element charge mode electrostatic discharge protective device of Figure 12 one embodiment of the invention.As shown in figure 12, this semiconductor structure 201 comprises semiconductor well region, example: a N well region 251, this semiconductor well district is arranged in this substrate 150.One metal-oxide-semiconductor field effect transistor structure 210, it is arranged in this N well region 251.

This metal-oxide-semiconductor field effect transistor structure 210 comprises p-type doped region, gate regions 213,1 first 211 and an one second p-type doped region 212.

This second p-type doped region 212 is electrically connected at this N-shaped doped region 241 and internal circuit.This first p-type doped region 211 is electrically connected at an input/output circuitry.

Therefore, when element charge mode electrostatic discharge event occurs, this input/output circuitry, this first p-type doped region 211, this N well region 251, this second p-type doped region 212 and this internal circuit form an electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

Separately, this input/output circuitry, this first p-type doped region 211, this N well region 251, this N-shaped doped region 241 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

The generalized section of the semiconductor structure 202 of a kind of element charge mode electrostatic discharge protective device of Figure 13 one embodiment of the invention.Compared to Figure 12, in an embodiment of the present invention, this the first p-type doped region 221 of one metal-oxide-semiconductor field effect transistor structure 220 of one N well region 252 of this semiconductor structure 202 is electrically connected at N-shaped doped region 242 and an input/output circuitry, separately, one second p-type doped region 222 is electrically connected at an internal circuit.

Therefore, when element charge mode electrostatic discharge event occurs, this input/output circuitry, this first p-type doped region 221, this N well region 252, this second p-type doped region 222 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

Separately, this input/output circuitry, this N-shaped doped region 242, this N well region 252, this second p-type doped region 222 and this internal circuit form another electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

The generalized section of the semiconductor structure 300 of a kind of element charge mode electrostatic discharge protective device of Figure 14 one embodiment of the invention.

As shown in figure 14, this semiconductor structure 300 comprise one first time a structure 301 and second time structure 302.Compared to this semiconductor structure 101 shown in Figure 10, this first time this p-type doped region 141 part of structure 301 be formed at one first well region, example: one first N-type well region 351.Similarly, compared to this semiconductor structure 102 shown in Figure 11, this p-type doped region 142 part of this second time structure 302 is formed at one second well region, example: one second N-type well region 352.

Therefore, when element charge mode electrostatic discharge event occurs, this second N-shaped doped region 122 of this input/output circuitry, this p-type doped region 142, this substrate 150, this metal-oxide-semiconductor field effect transistor structure 120 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

Separately, this first N-shaped doped region 111 of this input/output circuitry, this metal-oxide-semiconductor field effect transistor structure 110, this substrate 150, this p-type doped region 141 and this internal circuit form another electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

The generalized section of the semiconductor structure 400 of a kind of element charge mode electrostatic discharge protective device of Figure 15 one embodiment of the invention.

As shown in figure 15, this semiconductor structure 400 comprise one first time a structure 401 and second time structure 402.Compared to this semiconductor structure 101 shown in Figure 10, this first time structure 401 comprise one first diode structure 471, it more comprises one the 3rd N-shaped doped region 481, N-shaped doped region the 481, three and is positioned at one first N-type well region 451.This, structure 401 separately comprised a p-type doped region 482 first time, and its part is arranged in this first N-type well region 451 and is isolated with the 3rd N-shaped doped region 481 from (STI) by shallow trench isolation.

3rd N-shaped doped region 481 of this first diode structure 471 is electrically connected at this p-type doped region 141.Separately, this p-type doped region 482 of this first diode structure 471 is electrically connected at this second N-shaped doped region 112 of this metal-oxide-semiconductor field effect transistor structure 110, is also connected to this internal circuit simultaneously.

Compared to this semiconductor structure 102 shown in Figure 11, this second time structure 402 comprises one second diode structure 472, and it more comprises one the 3rd N-shaped doped region 491, N-shaped doped region the 491, three and is positioned at one second N-type well region 452.This second time structure 402 separately comprises a p-type doped region 492, and its part is arranged in this second N-type well region 452 and is isolated with the 3rd N-shaped doped region 491 from (STI) by shallow trench isolation.

3rd N-shaped doped region 491 of this second diode structure 452 is electrically connected at this p-type doped region 142.Separately, this p-type doped region 492 of this second diode structure 472 is electrically connected at this first N-shaped doped region 121 of this metal-oxide-semiconductor field effect transistor structure 120, is also connected to this input/output circuitry simultaneously.

Therefore, when element charge mode electrostatic discharge event occurs, this second N-shaped doped region 122 of this input/output circuitry, this p-type doped region 492, this second N-type well region 452, the 3rd N-shaped doped region 491, this p-type doped region 142, this substrate 150, this metal-oxide-semiconductor field effect transistor structure 120 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

Separately, this input/output circuitry, this metal-oxide-semiconductor field effect transistor structure 110 this first N-shaped doped region 111, this substrate 150, this p-type doped region 141, the 3rd N-shaped doped region 481, this first N-type well region 451, this p-type doped region 482 and this internal circuit form another electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

The generalized section of semiconductor 500 structure of a kind of element charge mode electrostatic discharge protective device of Figure 16 one embodiment of the invention.

As shown in figure 16, this semiconductor structure 500 comprise one first time a structure 501 and second time structure 502.This, structure 501 was similar to this semiconductor structure 201 shown in Figure 12 first time.Separately, this second time structure 502 is similar to this semiconductor structure 202 shown in Figure 13.

Therefore, when element charge mode electrostatic discharge event occurs, this first p-type doped region 211 of this input/output circuitry, this metal-oxide-semiconductor field effect transistor structure 210, this first N-type well region 251, this N-shaped doped region 241 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

Separately, this second p-type doped region 222 of this input/output circuitry, this N-shaped doped region 242, this second N-type well region 252, this metal-oxide-semiconductor field effect transistor structure 220 and this internal circuit form another electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

The generalized section of the semiconductor structure 601 of a kind of element charge mode electrostatic discharge protective device of Figure 17 one embodiment of the invention.

As shown in figure 17, compared to this metal-oxide-semiconductor field effect transistor structure 210 being positioned at this N-type well region shown in Figure 12, this semiconductor structure 601 comprises one first diode 631 and one second diode 632.

This first diode 631 has an anode and a negative electrode, this anode of this first diode 631 is electrically connected at this first p-type doped region 211 and input/output circuitry, and this negative electrode of this first diode 631 is electrically connected at this second p-type doped region 212 and internal circuit.

This second diode 632 also has an anode and a negative electrode, this anode of this second diode 632 is electrically connected at this second p-type doped region 212 and this internal circuit, and this negative electrode of this second diode 632 is electrically connected at this first p-type doped region 211 and this input/output circuitry.

Therefore, when element charge mode electrostatic discharge event occurs, this input/output circuitry, this first diode 631 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

Separately, this input/output circuitry, this second diode 632 and this internal circuit form another electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

In this embodiment, each electrical conductivity path only has a diode 631 or 632.But in other embodiments, this first diode 631 can the mode of one or more Diode series present.

Separately, this second diode 632 can also the mode of one or more Diode series present.

The generalized section of the semiconductor structure 602 of a kind of element charge mode electrostatic discharge protective device of Figure 18 one embodiment of the invention.As shown in figure 18, compared to this metal-oxide-semiconductor field effect transistor structure 110 being positioned at this N-type well region shown in Figure 10, this semiconductor structure 602 comprises one first diode 681 and one second diode 682.

This semiconductor structure 602 more comprises a well region, example: a deep n-type well region 650, this deep n-type well region 650 is positioned at this metal-oxide-semiconductor field effect transistor structure 110, N-type well region 651 and 652 and part shallow trench isolation under (STI).

This first diode 681 has an anode and a negative electrode, this anode of this first diode 681 is electrically connected at this first N-shaped doped region 111 and input/output circuitry, and this negative electrode of this first diode 681 is electrically connected at this second N-shaped doped region 112 and internal circuit.

This second diode 682 has an anode and a negative electrode, this anode of this second diode 682 is electrically connected at this second N-shaped doped region 112 and this internal circuit, and this negative electrode of this second diode 682 is electrically connected at this first N-shaped doped region 111 and this input/output circuitry.

Therefore, when element charge mode electrostatic discharge event occurs, this input/output circuitry, this first diode 681 and this internal circuit form an electrical conductivity path and flow to this internal circuit to allow static discharge current from this input/output circuitry.

Separately, this input/output circuitry, this second diode 682 and this internal circuit form another electrical conductivity path and flow to this input/output circuitry to allow static discharge current from this internal circuit.

In this embodiment, each electrical conductivity path only has a diode 681 or 682.But in other embodiments, this first diode 681 can the mode of one or more Diode series present.

Separately, this second diode 682 can also the mode of one or more Diode series present.

Technology contents of the present invention and technical characterstic disclose as above, but it will be understood by a person skilled in the art that, not deviating from the spirit and scope of the invention that claims define, and teaching of the present invention and disclose and can do all replacements and modification.Such as, the many techniques disclosed above can be implemented or are replaced with other technique in a variety of ways, or adopt the combination of above-mentioned two kinds of modes.

In addition, the interest field of this case is not limited to the technique of the specific embodiment disclosed, board, manufacture, the composition of material, device, method or step above.It will be understood by a person skilled in the art that, based on teaching of the present invention and disclose technique, board, manufacture, the composition of material, device, method or step, no matter exist now or developer in the future, it performs the identical function of essence with this case embodiment announcement person in the mode that essence is identical, and reach the identical result of essence, also can be used in the present invention.Therefore, claims are in order to contain in order to the composition of this type of technique, board, manufacture, material, device, method or step.

Claims

1. there is an integrated circuit for element charge mode electrostatic discharge protective, it is characterized in that, comprise:

One input/output circuitry; And

At least one electrostatic discharge protective device, is configured to be coupled between at least one earthing potential of this input/output circuitry and an earthing potential of at least one internal circuit; Wherein this at least one electrostatic discharge protective device comprises an element charge mode electrostatic discharge protective device, this element charge mode electrostatic discharge protective device comprises a turnpike formula circuit, and this turnpike formula circuit is when this integrated circuit normal manipulation mode, it is a guiding path with low resistance, and this turnpike formula circuit is when element charge mode electrostatic discharge event occurs, there is a conducting voltage.

2. integrated circuit as claimed in claim 1, is characterized in that, this at least one electrostatic discharge protective device is coupled between an earthing potential of this at least one internal circuit and an earthing potential of another this at least one internal circuit.

3. integrated circuit as claimed in claim 1, it is characterized in that, this turnpike formula circuit, when element charge mode electrostatic discharge event occurs, is a guiding path with two-way admittance characteristic.

4. integrated circuit as claimed in claim 1, is characterized in that, more comprise:

Between the earthing potential that at least one through-silicon-via is coupled to this at least one earthing potential of this input/output circuitry and this at least one electrostatic discharge protective device.

5. integrated circuit as claimed in claim 4, is characterized in that, between the earthing potential that this at least one through-silicon-via is coupled to this at least one internal circuit and this at least one electrostatic discharge protective device.

6. integrated circuit as claimed in claim 4, is characterized in that, this at least one through-silicon-via is coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

7. integrated circuit as claimed in claim 6, is characterized in that, between the earthing potential that this at least one through-silicon-via is coupled to this at least one internal circuit and this at least one electrostatic discharge protective device.

8. integrated circuit as claimed in claim 6, is characterized in that, this at least one through-silicon-via is coupled to another this at least one through-silicon-via.

9. there is an integrated circuit for element charge mode electrostatic discharge protective, it is characterized in that, comprise:

One input/output circuitry;

At least one electrostatic discharge protective device; And

At least one through-silicon-via, and between each this at least one through-silicon-via earthing potential of being coupled to this input/output circuitry and this at least one electrostatic discharge protective device;

Wherein each this at least one electrostatic discharge protective device is configured to be coupled between this at least one through-silicon-via and an earthing potential of this at least one internal circuit, this at least one electrostatic discharge protective device comprises an element charge mode electrostatic discharge protective device, this element charge mode electrostatic discharge protective device comprises a turnpike formula circuit, and when this integrated circuit normal manipulation mode, this turnpike formula circuit is a guiding path with low resistance, and this turnpike formula circuit is when element charge mode electrostatic discharge event occurs, this turnpike formula circuit has a conducting voltage.

10. integrated circuit as claimed in claim 9, is characterized in that, between the earthing potential that this at least one through-silicon-via is configured to be coupled to this at least one internal circuit and this at least one electrostatic discharge protective device.

11. integrated circuits as claimed in claim 9, is characterized in that, this at least one through-silicon-via is configured to be coupled between another this at least one through-silicon-via and this at least one electrostatic discharge protective device.

12. integrated circuits as claimed in claim 11, is characterized in that, between the earthing potential that this at least one through-silicon-via is configured to be coupled to this at least one internal circuit and this at least one electrostatic discharge protective device.

13. integrated circuits as claimed in claim 11, is characterized in that, this at least one through-silicon-via is configured to be coupled to another this at least one through-silicon-via.

14. integrated circuits as claimed in claim 9, is characterized in that, when element charge mode electrostatic discharge event occurs, this turnpike formula circuit is a guiding path with two-way admittance characteristic.

15. 1 kinds of integrated circuits with element charge mode electrostatic discharge protective, is characterized in that, comprise:

One first circuit with a first end, one second end and one the 3rd end, wherein this first end of this first circuit is coupled to a power supply, and the 3rd end of one first earthing potential and this first circuit that this second end of this first circuit is coupled to an input/output circuitry or an internal circuit is coupled to one second earthing potential of another internal circuit;

One second circuit with a first end, one second end and one the 3rd end, wherein this first end of this second circuit is coupled to this power supply, and the 3rd end that this second end of this second circuit is coupled to this second earthing potential and this second circuit is coupled to this first earthing potential; And

One tertiary circuit with a first end, one second end and one the 3rd end, wherein the 3rd end of this tertiary circuit is coupled to this power supply, and this first end that this second end of this tertiary circuit is coupled to this second earthing potential and this tertiary circuit is coupled to this first earthing potential;

Wherein this tertiary circuit comprises a switch, and this tertiary circuit is when this integrated circuit normal manipulation mode, and provide the guiding path that has a low resistance, when element charge mode electrostatic discharge event occurs, this tertiary circuit has a conducting voltage.

16. integrated circuits as claimed in claim 15, is characterized in that, this tertiary circuit in this integrated circuit meet with this element charge mode electrostatic discharge event occur time, the guiding path that has a two-way admittance characteristic is provided.

17. integrated circuits as claimed in claim 15, is characterized in that, when this integrated circuit normal manipulation mode, this first circuit and this second circuit are in the state of closedown.

18. integrated circuits as claimed in claim 15, it is characterized in that, when this element charge mode electrostatic discharge event occurs, this first circuit is in the state that the state of conducting and this second circuit are in closedown, and this first end of this tertiary circuit and the 3rd end of this tertiary circuit are equipotential.

19. integrated circuits as claimed in claim 15, it is characterized in that, when this element charge mode electrostatic discharge event occurs, this second circuit is in the state that the state of conducting and this first circuit are in closedown, and this second end of this tertiary circuit and the 3rd end of this tertiary circuit are equipotential.

20. 1 kinds of integrated circuits with element charge mode electrostatic discharge protective, is characterized in that, comprise:

One substrate;

At least one the first transistor, it is arranged in this substrate, wherein this transistor comprises the second doped region that first doped region and with the first type doping has the doping of this first type, wherein this have the first doped region of this first type doping and this one of second doped region with the doping of this first type be electrically connected at an input/output circuitry or an internal circuit one first earthing potential and another this there is the doping of this first type doped region be electrically connected at one second earthing potential of another internal circuit;

One first doped region with Second-Type doping, it is arranged in this substrate, wherein this first doped region with the doping of this Second-Type be electrically connected at this first earthing potential and this both the second earthing potential one of them;

Wherein when this integrated circuit normal manipulation mode, the state that this at least one the first transistor is in conducting is to form a turnpike formula circuit and the guiding path providing to have a low resistance; And

Wherein when element charge mode electrostatic discharge event occurs, this at least one the first transistor is in the state of closedown and provides one to have the guiding path of the parasitic two-way admittance of a conducting voltage to discharge stored charge.

21. integrated circuits as claimed in claim 20, it is characterized in that, this substrate more comprises a well region, wherein this have this first type doping the first doped region, this have this first type doping the second doped region and this have this Second-Type doping the first doped region be arranged in this well region.

22. integrated circuits as claimed in claim 20, is characterized in that, more comprise:

One transistor seconds, it is arranged in this substrate, and wherein this transistor seconds has the identical structure of the first transistor at least one with this; And

One have this Second-Type doping the second doped region, it is arranged in this substrate, wherein this have this Second-Type doping second doped region be electrically connected at this first earthing potential and this both the second earthing potential another one wherein.

23. integrated circuits as claimed in claim 22, is characterized in that, more comprise:

One first well region, it is arranged in this substrate, and this of wherein this at least one the first transistor has the first doped region of this first type doping and this has the second doped region of this first type doping and this has the first doped region that this Second-Type adulterates and is positioned at this first well region.

24. integrated circuits as claimed in claim 23, is characterized in that, more comprise:

One second well region, it is arranged in this substrate, and this of wherein this transistor seconds has the first doped region of this first type doping and this has the second doped region of this first type doping and this has the second doped region that this Second-Type adulterates and is positioned at this second well region.

25. integrated circuits as claimed in claim 20, is characterized in that, more comprise:

One first diode structure, its comprise one have this first type doping the 3rd doped region and this have this Second-Type doping the first doped region.

26. integrated circuits as claimed in claim 25, is characterized in that, more comprise:

One first well region, wherein this have this first type doping the 3rd doped region be arranged in this first well region and this have this Second-Type doping the first doped region part be arranged in this first well region.

27. integrated circuits as claimed in claim 26, is characterized in that, more comprise:

One have this Second-Type doping doped region, its be electrically connected at this have this first type doping the 3rd doped region.

28. integrated circuits as claimed in claim 25, is characterized in that, more comprise:

One second diode structure, it comprises the second doped region that another the 3rd doped region and one with the doping of this first type has the doping of this Second-Type, and wherein this second doped region with the doping of this Second-Type is electrically connected at this first earthing potential and this both the second earthing potential another one wherein.

29. integrated circuits as claimed in claim 28, is characterized in that, more comprise:

One second well region, wherein this another have this first type doping the 3rd doped region be arranged in this second well region and this have this Second-Type doping the second doped region part be arranged in this second well region.

30. integrated circuits as claimed in claim 29, is characterized in that, more comprise:

One have this Second-Type doping doped region, its be electrically connected at this another have this first type doping the 3rd doped region.