CN1362742A - Electrostatic discharge preventing method and device and integrated circuit - Google Patents
Electrostatic discharge preventing method and device and integrated circuit Download PDFInfo
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- CN1362742A CN1362742A CN01144053A CN01144053A CN1362742A CN 1362742 A CN1362742 A CN 1362742A CN 01144053 A CN01144053 A CN 01144053A CN 01144053 A CN01144053 A CN 01144053A CN 1362742 A CN1362742 A CN 1362742A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/701—Integrated with dissimilar structures on a common substrate
- Y10S977/723—On an electrically insulating substrate
Abstract
The integrated circuit including static discharging protection circuit comprises at least one group of bidirectional silicon diodes containing a first silicon diode and a second silicon diode, in which an n-type zone of first silicon diode is electrically coupled with a p-type zone of second silicon diode, and a p-type zone of first silicon diode is electrically coupled with a n-type zone of second silicon diode, in which its at least one group of bidirectional silicon diodes is reacted with positive static discharge or negative static discharge signal to provide static discharge protection.
Description
Invention field
The present invention relates to a kind of semiconductor integrated circuit, specifically, the integrated circuit that utilizes two-way silicon wafer diode to carry out the method and apparatus of electrostatic discharge protective and have electrostatic discharge protective.
Background of invention
Easily producing in the environment of static, semiconductor integrated circuit (Integrated Circuit is hereinafter to be referred as IC) suffers the injury of static discharge through regular meeting, causes IC to produce electric leakage or damage.Static discharge (Electrostatic Discharge is hereinafter to be referred as ESD) is a kind of buildup of static electricity, a kind of phenomenon that electrostatic charge shifts between different objects.Time when static discharge takes place is very short, is nanosecond (nano-second) grade, and can produce the very high electric Chinese in the so short time, usually can be high to several amperes, and the high like this electric current semiconductor integrated circuit of in a single day flowing through can make it impaired usually.Static discharge may occur between any two pins (pin) of IC, between the pin and VSS pin (ground signalling is provided) as following several situations (a) IC, (b) between IC pin and the VDD pin (electric energy is provided), (c) between different IC pins, and (d) between VDD pin and the VSS pin, as Fig. 1 (a) to shown in Fig. 1 (d).The accumulation source of common electrostatic charge comprises human body and manufacturing process machine.Well known elements can be represented with three kinds of patterns formulating in industrial standard by the situation of static discharge at present, Human Body Model (Human Body Model, be abbreviated as HBM), machine pattern (Machine Model, be abbreviated as MM), with charge member pattern (Charged Device Model is abbreviated as CDM).Though these static discharge patterns are the generation situation of real simulation static discharge absolutely, also enough be used for setting up the benchmark of static discharge tolerance level data.
In ESDA (ESD Association) standard, in the development projects of static discharge control formula, a standard A NSI/ESD-S20.20-1999 (on August 4th, 1999) is arranged, its mention motor electronic part, assembling, with the protection of equipment, and provide the tolerance level test of aforementioned three kinds of static discharge patterns.On behalf of static, the human body electro static discharge pattern be delivered to the lead of an element from the finger tip of a human body of standing.Fig. 2 has illustrated the equivalent electric circuit of Human Body Model's electrostatic discharge testing, and wherein 100pF electric capacity is represented human body equivalence discharge capacity, and 1500 Ohmic resistances are represented human body equivalence discharge resistance.Electric charge is stored in human body equivalence discharge capacity earlier, discharges into element under test via human body equivalence discharge resistance again.This human body static discharge discharge waveform is that a rise time is the double-exponential function waveform of 2 to 10 nanoseconds, and its pulse duration was about for 150 nanoseconds.Wherein, when discharge voltage was 2000 volts, its discharging current was about 1.33 amperes.Similar test parameter also is found in other industrial standard, (March 22 as MIL-STD-883E method 3015.7,1989) with JEDEC Standard for Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), JESD22, A114-B (June 2000).
The static discharge of machine pattern is represented from the very low path repid discharge of resistance, for example from a metal cable, and the conductor arm of an automatic test machine device.The equivalent discharge capacity of this pattern is 200pF, an equivalence discharge inductance 500nH is arranged, and its equivalent discharge resistance approximates 0.Its discharge waveform is a sinusoidal waveform in the decay, and its rise time was about for 5 to 8 nanoseconds, and its cycle was about for 80 nanoseconds, and its maximum discharge current can reach more than 8 amperes usually.This machine pattern is also at industrial standard EIA/JEDECStandard, Test Method A115-A for Electrostatic Discharge (ESD) SensitivityTesting Machine Model (MM), EIA/JESD22-A115-A (October 1997) mentions.
The static discharge of charge member pattern is with element very big dependence to be arranged, the phenomenon of this pattern description is as follows: an element has been accumulated electrostatic charge in element itself in advance because of friction, electric field induction or other factors, touch this element as an earthing device or the device that has than electronegative potential, and the static discharge phenomenon of potential balance takes place.Different element materials, size can be accumulated the static of different amounts under identical situation, so the static discharge of charge member pattern and element have very big dependence.The rise time of its discharge waveform is usually less than 200pS (picoseconds, picosecond), and whole discharge waveform is approximately less than 2 nanoseconds, and maximum discharge current usually can be high to tens of amperes.This charge member pattern can be with reference to industrial standard JEDEC Standard, Field-Induced Charged-DeviceModel Test Method for Electrostatic-Discharge-Withstand Thresholds ofMicroelectronic Components, JESD22-C101-A (June2000).
In general commercial applications, the static discharge ability to bear of an element is wanted to reach positive and negative 2000 volts of Human Body Model, and positive and negative 200 volts of machine pattern is with 1000 volts of charge member patterns.Fig. 3 drawn Human Body Model, machine pattern, with the static discharge oscillogram of charge member pattern.With reference to figure 3, the maximum discharge current of charge member pattern static discharge can be up to about 15 amperes in the time less than a nanosecond, and whole discharge process was finished in about 10 nanoseconds.
At present existing many methods or design are used to the protection integrated circuit and make it avoid the static discharge injury or promote its electro-static discharge protective ability.A common protection design is to use and parasitizes n type metal oxide semiconductor (metal-oxide semiconductor, MOS) transistor of element carries out electrostatic discharge protective, weld pad (Pad) is received in the drain electrode of this n type metal oxide semiconductor element, and source-coupled is to ground (Ground) or VSS power line.The transistorized design of diode or diode-coupled then is applied in radio frequency, and (Radio Frequency is RF) in the electrostatic storage deflection (ESD) protection circuit of integrated circuit.In RF IC; the electrostatic storage deflection (ESD) protection circuit of (on-chip) must have following properties on wafer: strong electro-static discharge protective ability; will present minimum input parasitic capacitance when being applied in input protection (input protection), and the correlation of this parasitic capacitance and voltage is low more good more.There is being shallow trench to completely cut off (Shallow-Trench Isolation, hereinafter to be referred as STI) deep-sub-micrometer CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal-Oxide Semiconductor, hereinafter to be referred as CMOS) in the manufacturing process technology, diode is used in the electrostatic discharge protective design circuit, this diode is formed by contiguous high concentration n type diffusion region (n+diffusion region) and high concentration p type diffusion region (p+diffusionregion) usually, and above-mentioned two diffusion regions all are positioned at semiconductor " substrate " (substrate), with reference to figure 4A, a p+ diffusion region is surrounded and uses this p+ diffusion region scope of definition by STI, therefore should be called as the diode that STI limits by the formed diode of STI.The diode that this STI limits has presented the bottom capacitor Cbottom of a parasitism.This kind diode is found serious leakage current, and this leakage current comes from the metal silicified layer (not being drawn on the figure) on the p+ diffusion region and surrounds the interface of the STI of p+ diffusion region.
Fig. 4 B has illustrated the profile of another existing diode electrostatic discharge protection structure, and this diode is called as the diode that polysilicon limits.The definition of the p+ diffusion region scope of the diode that polysilicon limits is different with the diode that STI limits, the p+ diffusion region scope of the diode that polysilicon limits is to define by polysilicon, so the p+ diffusion region the interface that contacts with STI, does not therefore have the problem of leakage current.Yet total parasitic capacitance of the diode that this polysilicon limits is bigger than the diode that STI limits.This is because many side capacitor C sidewall cause.
Fig. 5 has illustrated an existing electrostatic storage deflection (ESD) protection circuit figure who utilizes the double diode structure.With reference to figure 5; by combining of ESD (Electrostatic Discharge) clamp circuit (VDD-to-VSS ESDclamp circuit) between double diode structure and power line; provide static discharge current a discharge path 2; make the static discharge current internal circuit of can not flowing through, just the electrostatic storage deflection (ESD) protection circuit of this be combined into has protected internal circuit not injured by static discharge.This circuit operation situation is summarized as follows: when static discharge betides weld pad Pad1 and weld pad Pad2 and is ground connection, static discharge current can be via the VDD power line that arrives low-resistance value along inclined to one side diode Dp1, again via ESD (Electrostatic Discharge) clamp circuit between power line with the static discharge current conducting to another low-resistance value VSS power line, at last, static discharge current will be by another along inclined to one side diode Dn2, arrive weld pad Pad2, flow out outside this circuit.In this circuit, the input capacitance of entire circuit mainly is that the junction capacitance by diode is influenced.The input capacitance Cin that sees into from weld pad Pad1 can be expressed as
Cin＝Cp1+Cn1
Wherein, Cp1 is the equivalent parasitic capacitances of diode Dp1, and Cn1 is the equivalent parasitic capacitances of diode Dn1.
At the circuit among Fig. 5, illustrated the graph of a relation of weld pad voltage and capacitance among Fig. 6.With reference to figure 6, when weld pad voltage rose, the equivalent parasitic capacitances of diode Dp1 rose, and the equivalent parasitic capacitances of diode Dn1 descends.Therefore, total input capacitance Cin is close to constant value not have change.This characteristic is very important to the application of radio frequency integrated circuit.
Summary of the invention
According to the present invention, a kind of electrostatic charge protection method is provided, comprise at least one group of two-way silicon wafer diode that comprises one first silicon wafer diode and one first silicon wafer diode, the wherein p type zone electric coupling of a n type of the first silicon wafer diode zone and the second silicon wafer diode, the one n type zone electric coupling of one p type of first silicon wafer diode zone and the second silicon wafer diode, the wherein static discharge that aligns of this at least one group two-way silicon wafer diode or negative static discharge signal reaction.
In one aspect of the invention, this at least one group two-way silicon wafer diode comprises the two-way silicon wafer diode that one or more serial connections are coupled.
According to the present invention, a kind of electrostatic discharge protective device also is provided, the two-way silicon wafer diode that comprises the silicon wafer diode of silicon at least one group of silicon wafer diode that comprises silicon on one first insulating barrier and one second insulating barrier, the wherein p type zone electric coupling of the silicon wafer diode of silicon on a n type of the silicon wafer diode of the silicon zone and second insulating barrier on first insulating barrier, the n type zone electric coupling of the silicon wafer diode of silicon on a p type of the silicon wafer diode of silicon zone and second insulating barrier on first insulating barrier, the wherein static discharge that aligns of this at least one group two-way silicon wafer diode or negative static discharge signal reaction.
According to the present invention, a kind of integrated circuit also is provided, comprise a signal weld pad, one first voltage source, with first ESD (Electrostatic Discharge) clamp circuit that is coupled to first voltage source, this first ESD (Electrostatic Discharge) clamp circuit has at least one group of two-way silicon wafer diode, this two-way silicon wafer diode comprises one first silicon wafer diode and one second silicon wafer diode, the wherein p type zone electric coupling of a n type of the first silicon wafer diode zone and the second silicon wafer diode, the one n type zone electric coupling of one p type of first silicon wafer diode zone and the second silicon wafer diode, and the wherein static discharge that aligns of this at least one group two-way silicon wafer diode or negative static discharge signal reaction.
In one aspect of the invention, this first voltage source is VDD, and first ESD (Electrostatic Discharge) clamp circuit is coupled to the signal weld pad, with the protection of static discharge that Human Body Model, charge member pattern or machine pattern are provided.
In another aspect of the present invention, further comprise one second ESD (Electrostatic Discharge) clamp circuit, have at least one group of two-way silicon wafer diode, this two-way silicon wafer diode comprises one the 3rd silicon wafer diode and one the 4th silicon wafer diode, the wherein p type zone electric coupling of a n type of the 3rd silicon wafer diode zone and the 4th silicon wafer diode, the one p type zone of the 3rd silicon wafer diode and the n type zone electric coupling of the 4th silicon wafer diode, and, wherein second ESD (Electrostatic Discharge) clamp circuit is electrically coupled to the matrix and the grid of a first transistor, so that the first transistor protection of the static discharge of charge member pattern at least to be provided.
Aspect another, this first voltage source is VSS of the present invention, and first ESD (Electrostatic Discharge) clamp circuit is coupled to the signal weld pad, with the protection of static discharge that at least a Human Body Model, charge member pattern or machine pattern are provided.
Again aspect another, this first voltage source is VDD of the present invention, and first ESD (Electrostatic Discharge) clamp circuit is coupled to the matrix and the grid of a first transistor, so that the first transistor protection of the static discharge of charge member pattern at least to be provided.
Aspect another, comprise further that one is coupled to second voltage source of first ESD (Electrostatic Discharge) clamp circuit of the present invention again, wherein first voltage source is VDD, and second voltage source is VSS, so that electrostatic discharge protective to be provided.
It must be appreciated that aforesaid general introduction and detailed description afterwards are exemplary and illustrative, the scope of the claim of advocating with further explanation the present invention.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
What Figure 1A illustrated to 1D is in integrated circuit, the contingent several situations of static discharge;
What Fig. 2 illustrated is Human Body Model's static discharge equivalent circuit diagram;
Fig. 3 illustrates be Human Body Model, machine pattern, with the static discharge oscillogram of charge member pattern;
What Fig. 4 A illustrated is an existing diode profile that is made in the integrated circuit;
What Fig. 4 B illustrated is another existing diode profile that is made in the integrated circuit;
That Fig. 5 illustrates is an existing electrostatic storage deflection (ESD) protection circuit figure;
What Fig. 6 illustrated is in Fig. 5, and weld pad voltage is to the graph of a relation of input parasitic capacitance;
What Fig. 7 illustrated is the profile of the silicon wafer diode of spirit according to the present invention;
What Fig. 8 illustrated is the profile of another silicon wafer diode of spirit according to the present invention;
What Fig. 9 illustrated is the profile of the silicon wafer diode that is made in silicon wafer on the insulating barrier of spirit according to the present invention;
What Figure 10 illustrated is the vertical view of the silicon wafer diode that is made in silicon wafer on the insulating barrier of spirit according to the present invention;
What Figure 11 A illustrated to 11H is the silicon wafer diode making process with n type zone line of the spirit according to the present invention;
What Figure 12 A illustrated to 12H is a kind of manufacture method of the silicon wafer diode with p type zone line of spirit according to the present invention;
What Figure 13 illustrated is the circuit symbol of corresponding silicon wafer diode of the present invention;
What Figure 14 illustrated is that the spirit according to the present invention is utilized two designed electrostatic storage deflection (ESD) protection circuit figure of silicon wafer diode element;
What Figure 15 A illustrated is the capacitance graph of a relation of the weld pad voltage among Figure 14 and indivedual silicon wafer diodes;
What Figure 15 B illustrated is the capacitance graph of a relation of the weld pad voltage among Figure 14 and total silicon wafer diode;
What Figure 16 A illustrated is that the spirit according to the present invention is utilized the designed electrostatic storage deflection (ESD) protection circuit figure of silicon layer diode element;
What Figure 16 B illustrated is that the spirit according to the present invention is utilized and piled up the designed electrostatic storage deflection (ESD) protection circuit figure of silicon layer diode element;
What Figure 16 C illustrated is that the spirit according to the present invention is utilized the designed electrostatic storage deflection (ESD) protection circuit figure of series connection silicon layer diode element;
What Figure 17 illustrated is, the spirit according to the present invention is utilized the designed electrostatic storage deflection (ESD) protection circuit figure of two silicon wafer diode elements of bias voltage;
What Figure 18 illustrated is, the voltage-current characteristic figure of indivedual silicon wafer diodes and the silicon wafer diode of connecting;
What Figure 19 illustrated is that the spirit according to the present invention is utilized the designed electrostatic storage deflection (ESD) protection circuit figure of two-way silicon wafer diode;
What Figure 20 illustrated is that the spirit according to the present invention is utilized designed another electrostatic storage deflection (ESD) protection circuit figure of two-way silicon wafer diode;
What Figure 21 illustrated is that the spirit according to the present invention is utilized the designed another electrostatic storage deflection (ESD) protection circuit figure of two-way silicon wafer diode; And
What Figure 22 illustrated is that the spirit according to the present invention is utilized the designed high voltage withstanding electrostatic storage deflection (ESD) protection circuit figure of two-way silicon wafer diode.
The drawing reference numeral explanation
10,200,34,300: integrated circuit
12,202,36,112: the semiconductor-based end
14,114: the wellblock
14A: part wellblock
16,42,44,116: isolation structures
18,20: the diffusion region
22,158: dielectric layer
24,208,50:p type part
26,210,48:n type part
28,212: mid portion
32,206,132: silicon layer
204,38: insulating barrier
40: the first silicon layers
52: the second silicon layers
46: part first silicon layer
54,30,130: contact hole
56,64,66,156,168,170,172: photoresist
58: dielectric layer
62,162: abutment wall
25,124: first
120,125,126: part
4: static discharge current
6: ESD (Electrostatic Discharge) clamp circuit between power line
302: the signal weld pad
304-1,304-2,306-1,306-2,312-1: electrostatic storage deflection (ESD) protection circuit
308：PMOS
310：NMOS
308-1,310-1: matrix
308-2,310-2: grid
308-3,310-4: source electrode
308-4,310-3: drain electrode
Embodiment
According to spirit of the present invention, provide a kind of two-way silicon wafer diode with design comprise positive and negative to the protection circuit of static discharge.This two-way silicon wafer diode comprises the silicon wafer diode of at least one pair of antipolar phase coupling, that is the n type of silicon wafer diode zone and the regional electric coupling of the p type of another silicon wafer diode, and vice versa.Different with existing diode is that the silicon wafer diode does not have the bottom junction capacitance, so its parasitic capacitance is less relatively.In addition,, do not have the matrix leakage current, can not take silicon area yet, can save cost because the silicon wafer diode is to place on the STI at the semiconductor-based end.In addition, silicon wafer diode of the present invention also can additionally increase function, and design flexibility can more be arranged in the application of RF IC.
What Fig. 7 illustrated is the oblique top view of a kind of silicon layer diode of spirit according to the present invention.With reference to figure 7, integrated circuit 10 comprises the semiconductor-based end 12 and wellblock 14, one isolation structures, the 16 circle segment wellblock 14A that are made at semiconductor-based the end 12.Isolation structures can be STI or field oxide (Field Oxide).Integrated circuit 10 comprises that also one is adjacent to the diffusion region 20 of isolation structures 16.The impurity of homotype can mix for diffusion region 20 and wellblock 14.Integrated circuit 10 may comprise also that one is adjacent to the diffusion region 18 of isolation structures 16.In a preferred embodiment, the semiconductor-based end 12 is the substrate of a p type, and wellblock 14 is n type wellblock, and diffusion region 20 is a n type diffusion region.Presumable diffusion region 18 is a p type diffusion region.
One dielectric layer 22 places on the wellblock 14, and this dielectric layer 22 still is covered in isolation structures 16 and a part of wellblock 14A.In a preferred embodiment, dielectric layer 22 is an oxide layer.One deck silicon layer 32 places on the dielectric layer 22, and next this silicon layer 32 can become the silicon wafer diode.In a preferred embodiment, silicon layer 32 is a polysilicon layer.In another preferred embodiment, silicon layer 32 is a monocrystalline silicon layer.Silicon layer 32 has comprised a p type part 24, a n type part 26 and the mid portion 28 between p type part 24 and n type part 26.P type part 24 is positioned at isolation structures 16 tops with n type part 26, and mid portion 28 is positioned at part wellblock 14A top.In a preferred embodiment, part 28 is a Doped n-type impurity between silicon layer 32, and its concentration is light than the n type impurity concentration of n type part 26.In another preferred embodiment, the mid portion 28 of silicon layer 32 is a doped p type impurity, and its concentration is light than the p type impurity concentration of p type part 24.In another preferred embodiment again, the mid portion 28 of silicon layer 32 is a non-impurity-doped.A plurality of contact holes (contact) 30 place diffusion region 20, p type part 24, with n type part 26 on.
In operating aspect, the silicon wafer diode can react the static discharge signal, and electro-static discharge protection function is provided.Further, wellblock 14 can biasedly be used for controlling the silicon wafer diode.In a preferred embodiment, diffusion region 20 can be transmitted signal and be given wellblock 14, provides electro-static discharge protection function with control silicon wafer diode.
Fig. 8 has illustrated according to the present invention the profile of another silicon wafer diode of spirit.With reference to figure 8, one integrated circuits 200 comprised a semiconductor-based end 202, an insulating barrier 204, with a silicon layer 206 that is positioned at insulating barrier 204 tops.In a preferred embodiment, insulating barrier 204 is a sti structure.In another preferred embodiment, insulating barrier 204 is a field oxide structure.Silicon layer 206 comprises a p type part 208 and the n type part 210 that is adjacent to p type part 208.In a preferred embodiment, integrated circuit 200 comprises that further a dielectric layer places between silicon layer 206 and the insulating barrier 204 (not drawing).Silicon layer 206 may also comprise a mid portion 212 between p type part 208 and n type part 210.In a preferred embodiment, the mid portion 212 of silicon layer 206 is a Doped n-type impurity, and its concentration is light than the n type impurity concentration of n type part 210.In another preferred embodiment, the mid portion 212 of silicon layer 206 is a doped p type impurity, and its concentration is light than the p type impurity concentration of p type part 208.In another preferred embodiment again, the mid portion 212 of silicon layer 206 is a non-impurity-doped.This silicon wafer diode places on the STI at the semiconductor-based end 202, so do not connect face with the semiconductor-based end 202, so there is not substrate leakage current (substrate leakage), also can suppress ground noise (substrate noise).
What Fig. 9 illustrated is the profile of the silicon wafer diode that is made in SOI (Silicon-On-Insulator) wafer of spirit according to the present invention.With reference to figure 9, integrated circuit 34 comprises soi semiconductor substrate 36, an insulating barrier 38, one first silicon layer 40 and one second silicon layer 52.Wherein insulating barrier 38 places top, the semiconductor-based ends 36, and isolation structures 42 is made in first silicon layer 40 with isolation structures 44 and surrounds part first silicon layer 46, and this part first silicon layer 46 is to be matrix (Base) part.In a preferred embodiment, the semiconductor-based end 36 is the substrate of p type, and isolation structures 42 is a sti structure with isolation structures 44, and second silicon layer 52 is a polysilicon layer.
One dielectric layer (not drawing) places between first silicon layer 40 and one second silicon layer 52.Second silicon layer 52 comprises a n type part 48 and a p type part 50.N type part 48 is positioned at isolation structures 42 tops, and p type part 50 is positioned at isolation structures 44 tops.Second silicon layer 52 can further comprise a mid portion (not drawing) between n type part 48 and p type part 50, and this mid portion is positioned at the top of body portion 46.Integrated circuit 34 can further comprise a diffusion region (not drawing) be adjacent to isolation structures 42 and isolation structures 44 one of them, and be positioned within first silicon layer 40.Integrated circuit 34 still comprises a plurality of contact holes 54.
In operating aspect, the silicon wafer diode that is made in the SOI wafer can react the static discharge signal, and electro-static discharge protection function is provided.38 of insulating barriers in the SOI integrated circuit 34 provide element isolated function.Body portion 46 can biasedly be used for controlling the silicon layer diode so that electro-static discharge protection function to be provided.Therefore, this embodiment can be suitable is named as SOI silicon wafer diode.Figure 10 has illustrated the corresponding vertical view with Fig. 9.Fig. 9 is the profile of Figure 10 along A-A ' direction.
Figure 11 A is to utilize profile to show the method for making silicon wafer diode of the present invention to what Figure 11 H illustrated.With reference to figure 11A, provide semiconductor substrate 12.In a preferred embodiment, the semiconductor-based end 12 is the substrate of p type.Next, Figure 11 B has illustrated isolation structures 16 and has been formed at at semiconductor-based the end 12.Usually, isolation structures 16 is a sti structure, is to define it in the position at the semiconductor-based end via a photoetching corrosion manufacture craft, etches a shallow trench via etching process again, inserts Si oxide again or other materials with insulating properties form.
Figure 11 C is that wellblock 14 is formed at at semiconductor-based the end 12, via photoetching corrosion manufacture craft definition 14 positions, wellblock, the position that is not wellblock 14 is then stopped by photoresist 56, cooperates ion to inject (ion implantation) manufacture craft, forms wellblock 14.And then with photoresist 56 removals.In a preferred embodiment, the wellblock is a n type wellblock.The order of Figure 11 B and Figure 11 C can be exchanged, and still can form same structure.
Figure 11 D illustrates the beginning that forms the silicon layer diode.With reference to figure 11D, a dielectric layer 58 is formed on the wellblock on 14, and then forms a silicon layer 32 on dielectric layer 58.Define the pattern (pattern) of silicon layer again via the photoetching corrosion manufacture craft, usually, the traditional manufacturing technique step can form an abutment wall (spacer) 62 and be adjacent to silicon layer 32.Abutment wall 62 may have the material of insulating properties for Si oxide or other usually.
With reference to figure 11E, utilize the photoetching corrosion manufacture craft to define first injection region 20 on the silicon layer 32 first 25 and the semiconductor-based end 12.First 25 will have part can become the mid portion of silicon wafer diode.First injection region 20 is positioned within the wellblock 14.Carry out first ion then and inject manufacture craft, shown in Figure 11 E, and then with photoresist 64 removals.In a preferred embodiment, first ion injects the lightly doped drain that manufacture craft is the n type (Lightly-Doped Drain is called for short LDD) manufacture craft, and this step can be made the n type mid portion of silicon wafer diode.
With reference to figure 11F, utilize the photoetching corrosion manufacture craft to define a part 26 on the silicon layer 32 and the part 20 of wellblock 14 again, carry out second ion then and inject manufacture craft.And then with photoresist 65 removals.In a preferred embodiment, second ion injection manufacture craft is that N type drain-source is injected manufacture craft.This step can provide the signal binding with wellblock 14, and finishes the mid portion 28 of n type part with the n type of silicon wafer diode.
With reference to figure 11G, utilize the photoetching corrosion manufacture craft to define the 3rd an injection region part 24 on the silicon layer 32 again.Carry out the 3rd ion then and inject manufacture craft.And with photoresist 66 removals.In a preferred embodiment, the 3rd ion injection manufacture craft is that p type drain-source ion injects (p-typeDrain/Source implantation) manufacture craft.This step can be finished the p type part of silicon wafer diode.Usually, next traditional manufacturing technique can form a plurality of contact holes 30, shown in Figure 11 H, to finish the electrical ties to the silicon wafer diode element.Same, similar above-mentioned Figure 11 A utilizes profile to show the method for making silicon wafer diode of the present invention to Figure 11 H, and it is the manufacture method of the silicon wafer diode of p type part that Figure 12 A has illustrated mid portion to Figure 12 H.With reference to figure 12A, semiconductor substrate 112 is provided, in a preferred embodiment, the semiconductor-based end 112 is the substrate of p type.Next, Figure 12 B has illustrated isolation structures 116 and has been formed at at semiconductor-based the end 112.Usually, isolation structures 116 is a sti structure, is to define it in the position at the semiconductor-based end 112 via a photoetching corrosion manufacture craft, etches a shallow trench via etching process again, inserts Si oxide again or other materials with insulating properties form.Figure 12 C wellblock 114 is formed at at semiconductor-based the end 112, via photoetching corrosion manufacture craft definition 114 positions, wellblock, the position of non-wellblock 114 is then stopped by photoresist 156, cooperates ion to inject manufacture craft, form wellblock 114, and then photoresist 156 is removed.In a preferred embodiment, wellblock 114 is a n type wellblock.The order of Figure 12 B and Figure 12 C can be exchanged, and still can form same structure.
Figure 12 D illustrates the beginning that forms the silicon wafer diode, with reference to figure 12D, one dielectric layer 158 is formed on the substrate 112, and then form a silicon layer 132 on dielectric layer 158, define the pattern of silicon layer again via the photoetching corrosion manufacture craft, carry out etching process again, stay silicon layer 132 parts among the figure.Usually, the traditional manufacturing technique step can form an abutment wall 162 that is adjacent to silicon layer 132 again.Abutment wall 162 may have the material of insulating properties for Si oxide or other usually.Which kind of material whether forms abutment wall 162 or abutment wall uses do not influence silicon wafer diode of the present invention.
With reference to figure 12E, utilize the photoetching corrosion manufacture craft to define first 124 at silicon layer 132 and the semiconductor-based end 112.The mid portion that some will become the silicon wafer diode is understood by this first 124.Carry out the 4th ion then and inject manufacture craft, shown in Figure 12 E, and then with photoresist 168 removals.In a preferred embodiment, the 4th ion injection manufacture craft is the lightly doped drain manufacture craft of p type.With reference to figure 12F, utilize the photoetching corrosion manufacture craft to define the some 126 on the silicon layer 132 and the part 120 of wellblock 114 again, carry out the 5th ion then and inject manufacturing process.And then with photoresist 170 removals.In a preferred embodiment, the 5th ion injection manufacturing process is a N type drain-source manufacturing process.This step can provide the signal binding with wellblock 114, and finishes the mid portion 128 of n type part with the p type of silicon wafer diode.
With reference to figure 12G, utilize the photoetching corrosion manufacturing process to define the 6th an injection region part 125 on the silicon layer 132 again.Carry out the 6th ion then and inject manufacturing process.And with photoresist 172 removals.In a preferred embodiment, the 6th ion injection manufacturing process is that p type drain-source ion injects manufacturing process.This step can be finished the p type part of silicon wafer diode.Usually, next conventional fabrication processes can form a plurality of contact holes 130, shown in Figure 12 H, to finish the electrical ties to the silicon wafer diode element.
For using the SOI wafer technologies to make silicon wafer diode of the present invention, above-mentioned manufacture method must be revised to some extent, yet the step that needs to revise is those some steps irrelevant with forming the silicon layer diode.The step that needs to revise is contemplated to above-mentioned formation wellblock step before, so still can finish the silicon layer diode.
What Figure 13 illustrated is the circuit symbol schematic diagram of the silicon wafer diode of the spirit according to the present invention.This symbol is to be example with the silicon wafer diode that provides the substrate bias function, and in fact, in follow-up inventive embodiments, the silicon wafer diode (as shown in Figure 8) of no substrate bias function also all is suitable for.
With reference to Figure 14, be the two designed electrostatic storage deflection (ESD) protection circuit of silicon wafer diode of utilization among the figure.This pair silicon wafer diode circuit provides the discharge path of static discharge current, has protected internal circuit to make it not be subjected to the injury of static discharge.When static discharge betides weld pad 1 and weld pad 2 for ground connection, static discharge current 4 can flow to the VDD power line through the silicon wafer diode SD1 between VDD power line and the weld pad 1, pass through ESD (Electrostatic Discharge) clamp circuit between power line (VDD-TO-VSS ESDCLAMP CIRCUIT) 6 again and flow to the VSS power line, the silicon wafer diode SD4 between last process VSS power line again and the weld pad 2 flows to weld pad 2 and discharges outside the integrated circuits.In this circuit, the silicon wafer diode and the silicon wafer diode of substrate bias all can reach similar safeguard function.
So spirit of the present invention comprises that also the protection integrated circuit avoids the method for static discharge injury.This method comprises provides a kind of signal to integrated circuit component, and this integrated circuit component comprises that a minimum silicon wafer diode comes this signal is done reaction, so that electro-static discharge protection function to be provided, makes integrated circuit avoid suffering static discharge to injure.Similarly same, the present invention comprises that also protection SOI integrated circuit avoids the method for static discharge injury.This method has comprised provides a kind of signal to the SOI integrated circuit component, and this SOI integrated circuit component comprises that a minimum SOI silicon wafer diode comes this signal is done reaction, so that electro-static discharge protection function to be provided, makes the SOI integrated circuit avoid suffering static discharge to injure.
What Figure 15 A illustrated is weld pad voltage and individual diode element parasitic capacitance graph of a relation.Wherein have diode in Dp1 and the Dn1 representative graph 5 now, and SD1 and SD2 are the silicon wafer diode among Figure 14.To compare existing diode low owing to do not have side electric capacity and bottom capacitor according to the silicon wafer diode of spirit of the present invention, and diode characteristic is also similar, thus among the figure class of a curve seemingly, but capacitance is lower.Figure 15 B is total input capacitance and the weld pad voltage relationship figure in the electrostatic storage deflection (ESD) protection circuit.Because the existing diode of the capacitance of single silicon wafer diode is low, therefore total input capacitance is also relatively low, has approximately reduced the capacitance of half.
This total input capacitance or title input parasitic capacitance can further utilize the capacitances in series effect further to reduce.Figure 16 A is spirit according to the present invention, utilizes the designed electrostatic storage deflection (ESD) protection circuit figure of silicon wafer diode element.The parasitic capacitance value of supposing each silicon wafer diode is C, and then the value of the input parasitic capacitance of this circuit (symbol is Cin among the figure) is 2C.Figure 16 B is spirit according to the present invention, utilizes and piles up the designed electrostatic storage deflection (ESD) protection circuit figure of silicon wafer diode element.According to capacitances in series and basic physical characteristic in parallel, the value of the input parasitic capacitance of this circuit is C, is half value of Figure 16 A circuit.Further, with reference to figure 16C, the spirit according to the present invention is utilized the designed electrostatic storage deflection (ESD) protection circuit figure of series connection silicon wafer diode element.This circuit is at weld pad n the silicon wafer diode of all having connected up and down, and therefore, the value of the input parasitic capacitance of this circuit is 2C/n, and wherein n is the number of silicon wafer diode.In foregoing circuit, the silicon wafer diode of substrate bias all can reach to connect with the silicon wafer diode and reduce the effect of electric capacity.
The spirit according to the present invention, foregoing circuit further comprise a detecting-bias circuit.With reference to Figure 17, this detecting-bias circuit 85 comprises that a resistance R and a capacitor C place between power line VDD and the power line VSS, also have a PMOS Mp and a NMOS Mn to place between power line VDD and the power line VSS, wherein the drain electrode of PMOS and NMOS interconnects and signal can be provided, nmos source meets power line VSS, pmos source meets power line VDD, and PMOS links to each other with the grid of NMOS and links to each other with resistance capacitance.When static discharge took place, this detecting-bias circuit can provide the silicon wafer diode of a bias voltage signal to substrate bias, and to quicken the silicon wafer diode current flow of substrate bias, the protection internal circuit is not injured by static discharge.
The spirit according to the present invention, two-way silicon wafer diode comprises a pair of silicon wafer diode, the wherein regional electric coupling of the first silicon wafer diode regional p type of n type with the second silicon wafer diode, a n type zone electric coupling of p type zone of the first silicon wafer diode and the second silicon wafer diode makes static discharge that this two-way silicon wafer diode aligns or negative static discharge signal reaction.In addition two-way silicon wafer diode can comprise that n is cascaded to the silicon wafer diode of identical coupled modes.Wherein, n is an integer, between 1 between the infinity.Even, needn't be equal to the number of the silicon wafer diode of another direction series connection in the number of the silicon wafer diode of same direction series connection.In other words, perhaps two-way silicon wafer diode comprises that 1 silicon wafer diode is coupled in parallel to 2 serial connection silicon wafer diodes in addition.
Figure 18 has illustrated the part range of voltages current characteristics figure of indivedual silicon wafer diodes and the silicon wafer diode of connecting.This is to utilize polysilicon to make the embodiment of silicon wafer diode.Can obtain the trigger voltage of two-way silicon wafer diode from transverse axis, the longitudinal axis has then shown electric current.As can see from Figure 18, four each and every one other polysilicon diode PD1, PD2, PD3, with the suitable bias-voltage current characteristics of PD4, and, the suitable bias-voltage current characteristics that these four polysilicon diodes are serially connected.Can see that the conducting voltage addition can directly addition be and undistorted, She Ji two-way silicon wafer diode can effectively be controlled conducting voltage according to this, only need control the number of serial connection silicon wafer diode.
What Figure 19 illustrated is that spirit embodiment according to the present invention utilizes the designed electrostatic storage deflection (ESD) protection circuit figure of two-way silicon wafer diode.With reference to Figure 19, integrated circuit 300 has comprised a signal weld pad 302, four electrostatic storage deflection (ESD) protection circuit 304-1,304-2,306-1,306-2, a PMOS 308 and a NMOS 310.PMOS 308 has comprised a matrix 308-1, grid 308-2, a drain electrode 308-4 who is coupled to the source electrode 308-3 in vdd voltage source and is coupled to internal circuit.NMOS 310 has comprised a matrix 310-1, grid 310-2, a drain electrode 310-3 who is coupled to the source electrode 310-4 of VSS voltage source and is coupled to drain electrode 308-4.Electrostatic storage deflection (ESD) protection circuit 304-1 is coupled to signal weld pad 302 and VDD power line.Electrostatic storage deflection (ESD) protection circuit 304-2 is coupled to signal weld pad 302 and VSS power line.Electrostatic storage deflection (ESD) protection circuit 306-1 is coupled to grid 308-2 and the matrix 308-1 of PMOS 308.Electrostatic storage deflection (ESD) protection circuit 306-2 is coupled to grid 310-2 and the matrix 310-1 of NMOS 310.Signal weld pad 302 can be that input weld pad, output weld pad, power supply weld pad or other can touch the weld pad of Human Body Model, machine pattern or charge member pattern static discharge.When electrostatic storage deflection (ESD) protection circuit 304-1,304-2,306-1,306-2 were triggered by static discharge, the arrow among Figure 19 had represented that possible static discharge current flows to.
In operating aspect, when the static discharge of Human Body Model or machine pattern betided signal weld pad 302, electrostatic storage deflection (ESD) protection circuit 304-1,304-2 were ESD (Electrostatic Discharge) clamp circuit, avoided the static discharge injury in order to protection integrated circuit 300.When charge member pattern static discharge took place, electrostatic storage deflection (ESD) protection circuit 306-1,306-2 then avoided the static discharge injury in order to protection PMOS 308 and NMOS 310.Each electrostatic storage deflection (ESD) protection circuit 304-1,304-2,306-1,306-2 have comprised at least one group according to two-way silicon wafer diode of the present invention.When implementing, this electrostatic storage deflection (ESD) protection circuit can protect integrated circuit 300 to avoid external static discharge injury, as Human Body Model or machine pattern static discharge, and can avoid from inside to outside static discharge injury, as charge member pattern static discharge.
In one embodiment, each electrostatic storage deflection (ESD) protection circuit has comprised that series connection is a plurality of according to two-way silicon wafer diode of the present invention.The number of its series connection is to determine according to circuit required isolated voltage signal when the non-static discharge situation.For instance, if when operate as normal, the signal weld pad can receive 3 volts signal, and the signal that then needs to completely cut off then will be higher than 3 volts.Supposing to need isolated signal is 4.5 volts and the conducting voltage of each silicon wafer diode is 0.6 volt, then 8 along series connection silicon wafer diode partially altogether 4.8 volts of conducting voltage can use at this circuit and then only need 1 or 2 series connection get final product at the silicon wafer diode of contrary work partially because can be higher than 4.5 volts against inclined to one side breakdown voltage.
With reference to Figure 14, ESD (Electrostatic Discharge) clamp circuit also can use two-way silicon wafer diode of the present invention between this power line, and cooperates the circuit of Figure 19 (or Figure 20, Figure 21 and Figure 22), more to promote electro-static discharge protective ability.
What Figure 20 illustrated is that the spirit according to the present invention is utilized designed another electrostatic storage deflection (ESD) protection circuit figure of two-way silicon wafer diode, is applied in the application of multi-group power.In the application of multi-group power, regular meeting is isolated mutually between power supply, in order to eliminate the coupling of noise.But this also makes static discharge current get rid of via power line simultaneously, makes it cause the IC interior injury easily.According to spirit of the present invention, two-way silicon wafer diode can be used for connecting two isolated power lines, can rebuild current paths for ESD stress currents.The series connection number of two-way silicon wafer diode can need isolated noise grade in order to control.With reference to Figure 20, vdd voltage source VDD I/O and inner vdd voltage source VDD Internal (inside) are gone in the electrostatic storage deflection (ESD) protection circuit 312-1 output that has been coupled, and electrostatic storage deflection (ESD) protection circuit 312-2 has been coupled and one exports VSS voltage source V SS I/O and inner VSS voltage source V SS Internal.Electrostatic storage deflection (ESD) protection circuit 314 then provides the charge member pattern electro-static discharge protection function of electrostatic storage deflection (ESD) protection circuit 306-1 and 306-2 among similar Figure 19.
In like manner, two-way silicon wafer diode of the present invention can be applicable to analog circuit so that electrostatic discharge protective to be provided, as shown in figure 21, and, two-way silicon wafer diode of the present invention also can be applicable to high voltage withstanding output/input circuit (high-voltage tolerant I/O circuit), as shown in figure 22.This high voltage withstanding output/input circuit is that available circuit can be with reference to following document: Sanchez et al, " Aersatile 3.3/2.5/1.8-VCMOS I/O Driver Built in a 0.2-μ m; 3.5-nm Tox; 1.8-V CMOS Technology; " IEEE Journal of Solid-State Circuits, vol.34, no.11, pp.1501-1511. and Singhet al., " High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process, " IEEE Journal of Solid-State Circuits, vol.34, no.11, pp.1512-1525.This two document has been included in this file for your guidance.
In sum; though the present invention discloses as above in conjunction with a preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can make various changes and retouching, so protection scope of the present invention should be defined by the accompanying Claim scope.
Claims (28)
1. electrostatic charge protection method comprises:
At least one group of two-way silicon wafer diode that comprises one first silicon wafer diode and one second silicon wafer diode, the wherein p type zone electric coupling of a n type of this first silicon wafer diode zone and this second silicon wafer diode, the one p type zone of this first silicon wafer diode and the n type zone electric coupling of this second silicon wafer diode
The wherein static discharge that aligns of this at least one group two-way silicon wafer diode or negative static discharge signal reaction.
2. electrostatic charge protection method as claimed in claim 1, wherein this at least one group two-way silicon wafer diode comprises the two-way silicon wafer diode that one or more serial connections are coupled.
3. electrostatic charge protection method as claimed in claim 1, wherein this first silicon wafer diode comprises a central silicon area, this central authorities' silicon area places between this first silicon wafer diode n type zone and the p type zone, and adjacent with this n type zone and this p type zone.
4. electrostatic charge protection method as claimed in claim 1, wherein this second silicon wafer diode comprises a central silicon area, this central authorities' silicon area places between this second silicon wafer diode n type zone and the p type zone, and adjacent with this n type zone and this p type zone.
5. electrostatic charge protection method as claimed in claim 1 further comprises:
One first isolation structures; And
One and first isolation structures is second isolation structures of direct neighbor not;
Wherein the p type of this first silicon wafer diode zone is overlapping with this first isolation structures, and the n type of this first silicon wafer diode zone is overlapping with this second isolation structures.
6. electrostatic charge protection method as claimed in claim 5, comprise that further one is positioned at the diffusion zone of wellblock, one of them is adjacent for this diffusion zone and this first isolation structures or this second isolation structures, and wherein, the impurity that mixes in this diffusion zone and this wellblock is same form.
7. electrostatic charge protection method as claimed in claim 1 further comprises:
One the 3rd isolation structures; And
The one and the 3rd isolation structures is the 4th isolation structures of direct neighbor not;
Wherein the p type of this second silicon wafer diode zone is overlapping with the 3rd isolation structures, and the n type of this second silicon wafer diode zone is overlapping with the 4th isolation structures.
8. electrostatic charge protection method as claimed in claim 7, comprise that also one is positioned at the diffusion zone of wellblock, one of them is adjacent for this diffusion zone and the 3rd isolation structures or the 4th isolation structures, and wherein, the impurity that mixes in this diffusion zone and this wellblock is same form.
9. electrostatic charge protection method as claimed in claim 1, wherein this first silicon wafer diode comprises n series coupled silicon wafer diode, and this second silicon wafer diode comprises m series coupled silicon wafer diode, wherein n and m are to infinitely-great integer between 1.
10. electrostatic charge protection method as claimed in claim 9, wherein n is not equal to m.
11. electrostatic charge protection method as claimed in claim 1, further comprise one first voltage source and one second voltage source, this end of organizing two-way silicon wafer diode is coupled to this first voltage source, and the other end is coupled to this second voltage source, wherein, this first voltage source is VDD, and this second voltage source is VSS.
12. an electrostatic discharge protective device comprises:
The two-way silicon wafer diode of the silicon wafer diode of silicon at least one group of silicon wafer diode that comprises silicon on one first insulating barrier and one second insulating barrier, the wherein p type zone electric coupling of the silicon wafer diode of silicon on a n type of the silicon wafer diode of silicon zone and this second insulating barrier on this first insulating barrier, the n type zone electric coupling of the silicon wafer diode of silicon on a p type of the silicon wafer diode of silicon zone and this second insulating barrier on this first insulating barrier
The wherein static discharge that aligns of this at least one group two-way silicon wafer diode or negative static discharge signal reaction.
13. as the electrostatic discharge protective device of claim 12, wherein this at least one group two-way silicon wafer diode comprises the two-way silicon wafer diode that one or more serial connections are coupled.
14. an integrated circuit comprises:
One signal weld pad;
One first voltage source; And
One is coupled to first ESD (Electrostatic Discharge) clamp circuit of this first voltage source, have at least one group of two-way silicon wafer diode, this two-way silicon wafer diode comprises one first silicon wafer diode and one second silicon wafer diode, the wherein p type zone electric coupling of a n type of this first silicon wafer diode zone and this second silicon wafer diode, the one n type zone electric coupling of one p type of this first silicon wafer diode zone and this second silicon wafer diode, and the wherein static discharge that aligns of this at least one group two-way silicon wafer diode or negative static discharge signal reaction.
15. as the integrated circuit of claim 14, wherein this at least one group two-way silicon wafer diode comprises the two-way silicon wafer diode that one or more serial connections are coupled.
16. as the integrated circuit of claim 14, wherein this first voltage source is VDD, and this first ESD (Electrostatic Discharge) clamp circuit is coupled to this signal weld pad, with the protection of static discharge that Human Body Model, charge member pattern or machine pattern are provided.
17. the integrated circuit as claim 16 also comprises:
One second ESD (Electrostatic Discharge) clamp circuit, have at least one group of two-way silicon wafer diode, this two-way silicon wafer diode comprises one the 3rd silicon wafer diode and one the 4th silicon wafer diode, the wherein p type zone electric coupling of a n type of the 3rd silicon wafer diode zone and the 4th silicon wafer diode, the one p type zone of the 3rd silicon wafer diode and the n type zone electric coupling of the 4th silicon wafer diode, and wherein this second ESD (Electrostatic Discharge) clamp circuit is electrically coupled to a matrix and a grid of a first transistor, so that the protection of the static discharge of charge member pattern at least of this first transistor to be provided.
18. the integrated circuit as claim 16 further comprises:
One second ESD (Electrostatic Discharge) clamp circuit, have at least one group of two-way silicon wafer diode, this two-way silicon wafer diode comprises one the 3rd silicon wafer diode and one the 4th silicon wafer diode, the wherein p type zone electric coupling of a n type of the 3rd silicon wafer diode zone and the 4th silicon wafer diode, the one p type zone of the 3rd silicon wafer diode and the n type zone electric coupling of the 4th silicon wafer diode, and
Wherein this second ESD (Electrostatic Discharge) clamp circuit, one end is coupled to VDD, and the other end is coupled to this first ESD (Electrostatic Discharge) clamp circuit.
19. as the integrated circuit of claim 14, wherein this first voltage source is VSS, and this first ESD (Electrostatic Discharge) clamp circuit is coupled to this signal weld pad, with the protection of static discharge that at least a Human Body Model, charge member pattern or machine pattern are provided.
20. as the integrated circuit of claim 14, wherein this first voltage source is VDD, and first ESD (Electrostatic Discharge) clamp circuit is coupled to a matrix and a grid of a first transistor, so that the protection of the static discharge of charge member pattern at least of this first transistor to be provided.
21. the integrated circuit as claim 20 further comprises:
One second ESD (Electrostatic Discharge) clamp circuit, have at least one group of two-way silicon wafer diode, this two-way silicon wafer diode comprises one the 3rd silicon wafer diode and one the 4th silicon wafer diode, the wherein p type zone electric coupling of a n type of the 3rd silicon wafer diode zone and the 4th silicon wafer diode, the one p type zone of the 3rd silicon wafer diode and the n type zone electric coupling of the 4th silicon wafer diode, and
Wherein this second ESD (Electrostatic Discharge) clamp circuit, one end is coupled to VDD, and the other end is coupled to the signal weld pad, with the protection of static discharge that at least a Human Body Model or machine pattern are provided.
22. integrated circuit as claim 14, wherein this first voltage source is VSS, and this first ESD (Electrostatic Discharge) clamp circuit, one end is coupled to a matrix and this first voltage source of a transistor seconds, the other end is coupled to a grid of a transistor seconds, so that the protection of the static discharge of charge member pattern at least of this transistor seconds to be provided.
23. the integrated circuit as claim 22 further comprises:
One second ESD (Electrostatic Discharge) clamp circuit, have at least one group of two-way silicon wafer diode, this two-way silicon wafer diode comprises one the 3rd silicon wafer diode and one the 4th silicon wafer diode, the wherein p type zone electric coupling of a n type of the 3rd silicon wafer diode zone and the 4th silicon wafer diode, the one p type zone of the 3rd silicon wafer diode and the n type zone electric coupling of the 4th silicon wafer diode, and wherein this second ESD (Electrostatic Discharge) clamp circuit, one end is coupled to this matrix of VDD and this first transistor, and the other end is coupled to this grid of this first transistor.
24. as the integrated circuit of claim 23, wherein this gate coupled of this first transistor is to this grid of this transistor seconds.
25. as the integrated circuit of claim 14, comprise that further one is coupled to one second voltage source of this first ESD (Electrostatic Discharge) clamp circuit, wherein this first voltage source is VDD, this second voltage source is VSS, so that electrostatic discharge protective to be provided.
26. as the integrated circuit of claim 14, comprise that further one is coupled to a tertiary voltage source of this first ESD (Electrostatic Discharge) clamp circuit, wherein the voltage that provided of this tertiary voltage source is different from the voltage that this first voltage source is provided.
27. as the integrated circuit of claim 26, wherein this tertiary voltage source provides the VDD power supply to an output/input circuit, and this first voltage source provides the VDD power supply to an internal circuit.
28. as the integrated circuit of claim 26, wherein this tertiary voltage source provides the VSS power supply to an output/input circuit, and this first voltage source provides the VSS power supply to an internal circuit.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/749,377 | 2000-12-28 | ||
| US09/749,377 US6690065B2 (en) | 2000-12-28 | 2000-12-28 | Substrate-biased silicon diode for electrostatic discharge protection and fabrication method |
| US09/973,745 | 2001-10-11 | ||
| US09/973,745 US6617649B2 (en) | 2000-12-28 | 2001-10-11 | Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes |
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| Publication Number | Publication Date |
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| CN1362742A true CN1362742A (en) | 2002-08-07 |
| CN1226788C CN1226788C (en) | 2005-11-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011440538A Expired - Lifetime CN1226788C (en) | 2000-12-28 | 2001-12-28 | Electrostatic discharge preventing method and device and integrated circuit |
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| Country | Link |
|---|---|
| US (1) | US6617649B2 (en) |
| CN (1) | CN1226788C (en) |
| TW (1) | TW533591B (en) |
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-
2001
- 2001-10-11 US US09/973,745 patent/US6617649B2/en not_active Expired - Lifetime
- 2001-12-21 TW TW090131885A patent/TW533591B/en not_active IP Right Cessation
- 2001-12-28 CN CNB011440538A patent/CN1226788C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437558A (en) * | 2011-11-29 | 2012-05-02 | 上海宏力半导体制造有限公司 | ESD (electrostatic discharge) protection circuit |
| CN102437558B (en) * | 2011-11-29 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | Esd protection circuit |
| US9019668B2 (en) | 2011-12-30 | 2015-04-28 | Industrial Technology Research Institute | Integrated circuit having a charged-device model electrostatic discharge protection mechanism |
| CN103187416B (en) * | 2011-12-30 | 2015-09-30 | 财团法人工业技术研究院 | Integrated circuit with element charging mode electrostatic discharge protection |
Also Published As
| Publication number | Publication date |
|---|---|
| US6617649B2 (en) | 2003-09-09 |
| TW533591B (en) | 2003-05-21 |
| CN1226788C (en) | 2005-11-09 |
| US20020064007A1 (en) | 2002-05-30 |
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