CN1317763C - Electrostatic discharge protecting circuit - Google Patents
Electrostatic discharge protecting circuit Download PDFInfo
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- CN1317763C CN1317763C CNB2004100445514A CN200410044551A CN1317763C CN 1317763 C CN1317763 C CN 1317763C CN B2004100445514 A CNB2004100445514 A CN B2004100445514A CN 200410044551 A CN200410044551 A CN 200410044551A CN 1317763 C CN1317763 C CN 1317763C
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Abstract
The present invention provides an electrostatic discharge protection circuit. The electrostatic discharge protection circuit comprises a semiconductor substrate, a first P-shaped well, a second P-shaped well and a third P-shaped well, wherein the first P-shaped well, the second P-shaped well and the third P-shaped well are arranged on the semiconductor substrate, a first P<+> doping region and a first N<+> doping region which are arranged on the first P-shaped well are grounded; a second P<+> doping region and a second N<+> doping region which are arranged on the second P-shaped well are connected with electric source supplying voltage V<DD>; a third N<+> doping region, a third P<+> doping region and a fourth N<+> doping region are arranged on the third P-shaped well, and are used for outputting and inputting signals.
Description
Technical field
The present invention is relevant to a kind of ESD protection circuit, refers in particular to the ESD protection circuit of a kind of PS of comprising (Positive toVSS), NS (Negative to VSS), PD (Positive to VDD), ND (Negative to VDD) and DS five kinds of test patterns such as (VDD to VSS).
Background technology
In recent years, the improvement of integrated circuit fabrication process technology, feasible integrated circuit (the integrated circuit that is constituted as CMOS (Complementary Metal Oxide Semiconductor) field effect (CMOS) transistor etc., IC) size can be contracted to deep-sub-micrometer (deep-submicro) further from inferior micron (submicron), to reduce manufacturing cost and to promote operation efficiency.Yet (electrostaticdischarge, protective capacities ESD) can weaken along with dwindling of size integrated circuit for static discharge.For instance, when a channel width (channel width) of exporting buffer stage (output buffer) element is set to 300 microns, the NMOS element of 2 microns traditional integrated circuit fabrication process manufacturings can bear up to 3,000 volt electrostatic potential, yet the integrated circuit of 1 micron LDD (lightly-doped drain) manufacturing process manufacturing but only can bear 2,000 volts electrostatic potential.In addition; because the static in the residing environment of integrated circuit can't dwindle because of the size of integrated circuit any change is arranged; therefore; compare with the large scale integrated circuit; small size (Advanced Manufacturing Technology) integrated circuit is more vulnerable to the influence of static discharge and damages; therefore, be used for protecting integrated circuit to avoid the ESD protection circuit of damage of electrostatic discharge (ESDprotection circuit) and also just become more important along with improving of integrated circuit fabrication process.
Generally speaking, static discharge can be divided into human body discharge mode (human-body model generally, HBM), machine discharge mode (machine model, MM), element charge mode (charged-device model, CDM), (field-induced model FIM) waits four kinds of patterns to reach the electric field induction pattern.With the human body discharge mode is example, the people knows from experience and produces static because of walking about, when the human body of having accumulated some static touches integrated circuit, the static of being accumulated on the human body just can flow in the integrated circuit via the pin (pin) of integrated circuit, flow to earth point (ground) again via the discharge of integrated circuit.Above-mentioned static discharge process can be in a short time (hundreds of nanoseconds, nano-second) the interior several amperes of electric currents that spark that are enough to burn integrated circuit that produce.
See also Fig. 1, Fig. 1 protects an integrated circuit (IC) chip 16 for a known human body discharge mode 10 and being used for and avoids the equivalent circuit diagram of the ESD protection circuit 15 of the damage of electrostatic discharge that human body produces.ESD protection circuit 15 comprises an equivalent resistance 17 and an equivalent electric capacity 19, and (equivalent capacity 19 hypothesis have 1C
ESDCapacitance).The static that human body produces because of walking about can be accumulate to an equivalent electric capacity (100pF) 12; and when human body touches integrated circuit (IC) chip 16 (in the equivalence; one switch 18 transfers to point to terminal B by pointing to terminal A); the static that accumulates on the human body can be in regular turn via behind the equivalent resistance 17 and equivalent capacity 19 in an equivalent resistance 14 (1.5K Ω), the ESD protection circuit 15; flow to earth point; and can not be flowed directly to integrated circuit (IC) chip 16, avoid damage with protection integrated circuit (IC) chip 16 because of the formed static discharge current of static discharge.
Generally speaking, testing integrated circuits for the ability to bear of static discharge in respect of five kinds of test patterns such as PS, NS, PD, ND and DS.See also Fig. 2, Fig. 2 is the schematic diagram of integrated circuit (IC) chip 16 shown in the known PS test pattern resolution chart 1.The V of integrated circuit (IC) chip 16
SS Pin 24 ground connection, the pin to be measured of integrated circuit (IC) chip 16, pin 22 as shown in Figure 2 is connected to a positive test voltage 20, and comprises V in the integrated circuit (IC) chip 16
DDAll the other pins of pin 26 all suspension joint.
In the PS test pattern, positive test voltage 20 applies (zap) predetermined positive voltage to pin 22 to be measured (being generally three times) for several times, damages to test the predetermined positive voltage whether pin to be measured 22 applied because of test voltage 20 (static discharge) just.If pin 22 to be measured is still as excellent as before, then positive test voltage 20 increases this predetermined positive voltage, and again applies this predetermined positive voltage that increased in pin to be measured 22 3 times.Carry out so repeatedly, till the predetermined positive voltage that pin 22 to be measured is applied because of positive test voltage 20 was damaged, the predetermined positive voltage of this moment was that a static discharge is damaged threshold voltage (ESD failurethreshold).And whether the pin to be measured 22 of judging integrated circuit (IC) chip 16 is damaged in respect of absolute leakage current method, I-V drift method, and three kinds of methods such as function observation method relatively because of static discharge.
Before address, testing integrated circuits for the ability to bear of static discharge in respect of five kinds of test patterns such as PS, NS, PD, ND and DS, and Fig. 2 only is presented under the PS test pattern, and the static discharge of pin 22 to be measured is damaged threshold voltage (that is static discharge ability to bear).Yet identical pin to be measured 22 has different static discharges and damages threshold voltage under different test patterns.In addition, under same test pattern, the static discharge of wantonly two pins that comprised in the integrated circuit (IC) chip 16 is damaged threshold voltage and also is not quite similar.Because the damage of arbitrary pin all can cause the afunction of integrated circuit (IC) chip 16 in the integrated circuit (IC) chip 16, therefore, under all test patterns, the static discharge of all pins is damaged the other tool meaning of reckling ability in the threshold voltage in the integrated circuit (IC) chip 16, and this minimum static discharge is damaged the static discharge damage threshold voltage that threshold voltage also is only integrated circuit (IC) chip 16.
Because uncertain integrated circuit (IC) chip 16 is under which kind of test pattern; the static discharge of each pin is damaged threshold voltage and is only this minimum static discharge damage threshold voltage; therefore, avoiding surpassing this minimum static discharge in order to protection integrated circuit (IC) chip 16 damages the ESD protection circuit 30 of threshold voltage infringement and must protect static discharge under above-mentioned five kinds of different test patterns for all pins of integrated circuit (IC) chip 16.See also Fig. 3, Fig. 3 is the schematic diagram of the shown integrated circuit (IC) chip of Fig. 2 16.As previously mentioned; each pin all must comprise five kinds of electrostatic discharge (ESD) protection patterns in the integrated circuit (IC) chip 16; can be example as an input solder joint (pad) 22 and an output solder joint 28 simultaneously, integrated circuit (IC) chip 16 comprises an internal circuit 30 that is connected in pin 22, reaches five groups respectively at the ESD protection circuit 32,34,36,38 and 40 that is used for protecting internal circuit 30 in PS, NS, PD, ND and the DS test pattern.When ESD protection circuit 32 to 40 only acted on static discharge and betides integrated circuit (IC) chip 16, in other words, when integrated circuit (IC) chip 16 does not meet with any static discharge and during operate as normal, static discharge protected that circuit 32 to 40 is failure to actuate.
Course of work when integrated circuit (IC) chip 16 meets static discharge outlines as follows: with the ND test pattern is example, and electric current can be earlier from a V
DDPin 26 flows to esd protection circuit 36 and flows to esd protection circuit 26 more again along V
SSPin 24 flows to esd protection circuit 34 and input solder joint 22 arrives negative testing voltage 42 at last again.Therefore, integrated circuit (IC) chip 16 just can be avoided the infringement of negative testing voltage 42.
In the CMOS integrated circuit; can be as the element of ESD protection circuit nothing more than resistance (Diffusion or poly resistor), diode (p-n junction), metal-oxide semiconductor (MOS) (MOS) element, thick oxide layer element (Field-oxide device), parasitic bipolar junction transistor element (Bipolar junction transistor) and parasitic silicon controlled rectifier element (SCRdevice; p-n-p-n structure), these elements characteristic and endurance against electrostatic discharge of having nothing in common with each other.
For instance; because the operating voltage (approximately-13 to-15 volt) of the operating voltage (about 0.8 to 1.2 volt) of diode when forward bias during much smaller than reverse biased in other words; when the static discharge current of identical size during through a diode; the heat that the heat that this diode is produced when forward bias can be produced much smaller than in reverse biased the time; therefore; have under the prerequisite of same size; the static discharge voltage value that the static discharge voltage value that diode when working in forward bias can bear can the diode when working in reverse biased can bear, and only act on forward bias usually as the diode of ESD protection circuit.But also just because the diode in the ESD protection circuit only acts on forward bias usually, so, this ESD protection circuit additional other element of still needing extraly as resistance etc.Otherwise, because the operating voltage of SCR element during no matter in forward bias or in reverse biased all is about 1 volt, so, only need less area just can bear higher static discharge voltage as the SCR element of ESD protection circuit.Under identical manufacturing process, the SCR element can be higher than the anti-electrostatic potential ability of all the other elements on unit are in the anti-electrostatic potential ability on the unit are.
Said elements can be used to be combined into various ESD protection circuit.See also Fig. 4 and Fig. 5; Fig. 4 and Fig. 5 are the two or more ESD protection circuit 50 of element formation and 60 the circuit diagrams stated; ESD protection circuit 50 and 60 all is connected between pin 22 and the internal circuit 30, avoids the infringement of static discharge in order to protection internal circuit 30.Shown ESD protection circuit 50 comprises a resistance 52 and two diodes 54 and 56 among Fig. 4, and shown ESD protection circuit 60 then comprises two resistance 62 and 64, one a SCR element 66 and an oxide layer element 68 among Fig. 5.The ability of the anti-static discharge of the ESD protection circuit 50 that Fig. 5 is shown is better than the ability of the anti-static discharge of the shown ESD protection circuit of Fig. 4 40.
As previously mentioned; one ESD protection circuit can have different endurance against electrostatic discharge because of the difference of the element that comprised in it; yet the improvement of each different elements also can be promoted the endurance against electrostatic discharge of the ESD protection circuit at this element place indirectly.With the cmos element is example, improves the endurance against electrostatic discharge of cmos element and can set about from manufacturing process, element itself and three stages of circuit design.
With regard to manufacturing process with regard to the stage, in the CMOS manufacturing process, add the LDD structure no matter be, go up use Silicided diffusion at the diffusion layer (diffusion) of MOS element, use Polycide with the spuious series resistance on the grid that reduces the MOS element, or in manufacturing process, make Silicideddiffusion and Polycide manufacturing process simultaneously, though all can increase the arithmetic speed and the integrated level of the internal circuit of MOS significantly, damaged by static discharge but the CMOS chip that is come out by these Advanced Manufacturing Technology manufacturings is easier, that is, the non-constant of the endurance against electrostatic discharge of this CMOS chip.And anti-electrostatic-discharge injects manufacturing process (ESD-implant process) and metal silicide diffusion layer and separates manufacturing process (silicided-diffusion blocking process) and just be two kinds and improve one's methods in order to the manufacturing process stage of improving above-mentioned shortcoming.Anti-electrostatic-discharge injects manufacturing process in same CMOS manufacturing process, covering original LDD zone, and makes the CURRENT DISTRIBUTION of drain region average at the many one ion injecting programs of drain electrode end, promotes the ESD holding capacity.The metal silicide diffusion layer is separated drain electrode and the steady resistance between grid (Ballasting Resistor) that manufacturing process can be controlled the MOS element effectively, and and then promotes the arithmetic speed of MOS element.
With regard to the element stage itself, be example with the SCR element, comparatively famous have low-voltage trigger silicon controlled rectifier (low-voltage triggering SCR, LVTSCR).LVTSCR comprises P
+Diffusion, N-well, P-substrate and N
+Four-layer structures such as diffusion.Owing to have quite high junction breakdown voltage (junction breakdown threshold, about 30 to 50 volts), so LVTSCR must add a clamp circuit (clamp circuit) extraly.When because of the effect conducting of static discharge, the low clamping voltage that LVTSCR produced (clamping voltage) can be clamped on a low-voltage position standard with static discharge voltage, to protect the internal circuit of its desire protection.
With regard to circuit design stage, more famous having is applied to gate coupled (gate-coupled) grounded-grid (gate-grounded) base drive (substrate-triggered) technology of NMOS.Because large-size components big city is become finger-shaped (finger type) by layout, yet these fingers that are connected in parallel not necessarily conducting simultaneously with the mediation static discharge current, this just why the endurance against electrostatic discharge of element may not be certain the cause that can amplify synchronously along with the increase of component size, therefore, the control (capacitance coupling effect) of base voltage of base drive technology facility, each finger of conducting equably is to increase the endurance against electrostatic discharge of large-size components.And the grounded-grid technology is connected to a pin and earth point respectively with drain electrode and the grid of a MOS, and the parasitic bipolar two-carrier transistor npn npn (BJT) by this MOS inside of conducting, to release static discharge current; Gate coupled then adopts capacitive coupling control gate electrode potential, to help the conducting of parasitic BJT.Before address because the test pattern of five kinds of testing integrated circuits for the ability to bear of static discharge arranged, and a MOS only can finish two kinds of test patterns at the most, so known ESD protection circuit needs three MOS to finish at least.
Generally speaking, known ESD protection circuit has following shortcoming:
1. ESD protection circuit causes load effect to its internal circuit, influences overall efficiency;
2. the leakage current of ESD protection circuit own is excessive, increases power dissipation;
3. the threshold voltage of ESD protection circuit is too high, the static discharge current of can't releasing in time, and reach protective action;
4. the static discharge voltage deficiency that can bear of ESD protection circuit itself reduces the ability of ESD protection circuit protection internal circuit;
5. static discharge current can't flow through ESD protection circuit equably, so that, even increase the area of ESD protection circuit, also can't guarantee correspondingly to improve the protective benefits of static discharge;
6. for to reach comprehensive electrostatic discharge protective purpose, ESD protection circuit needs three electric static discharge protectors at least, causes area to increase;
7. ESD protection circuit uses extra manufacturing process to finish sometimes, and for example ESDimplant (injection) increases the cost expenditure; And
At present on the market ESD protection circuit and be not suitable for the wide band radio-frequency circuit.
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of ESD protection circuit, to solve the problem of known technology.
According to claim of the present invention; the present invention discloses a kind of ESD protection circuit that comprises five kinds of test patterns; it comprises semi-conductive substrate, three and is arranged at first, second and third P type trap on this Semiconductor substrate, and a P type trap is provided with one the one P
+Ooze Za Qu and one the one N
+Ooze assorted district, a P
+Ooze an assorted district and a N
+Ooze assorted district ground connection, the 2nd P type trap is provided with one the 2nd P
+Ooze Za Qu and one the 2nd N
+Ooze assorted district, the 2nd P
+Ooze assorted district and the 2nd N
+Ooze assorted district and be connected in input voltage, the 3rd P type trap is provided with one the 3rd N
+Ooze Za Qu, one the 3rd P
+Ooze assorted district, reach one the 4th N
+Ooze assorted district, the 3rd N
+Ooze assorted district, the 3rd P
+Ooze assorted district and the 4th N
+Ooze assorted the district and be used for exporting signal.
In preferred embodiment of the present invention, this Semiconductor substrate is a N type semiconductor substrate, and this a plurality of oozing in the assorted district deposits silicide.
Because ESD protection circuit of the present invention can independently be finished all test patterns, therefore do not need extra clamp circuit.In addition, be deposited on the endurance against electrostatic discharge that these a plurality of silicides that ooze in the assorted district can be strengthened this ESD protection circuit.
Description of drawings
Fig. 1 is the equivalent circuit diagram of a known human body discharge mode and an ESD protection circuit.
Fig. 2 is the schematic diagram of integrated circuit (IC) chip shown in the known PS test pattern resolution chart 1.
Fig. 3 is the schematic diagram of the shown integrated circuit (IC) chip of Fig. 2.
Fig. 4 and Fig. 5 are the two or more circuit diagrams of stating the ESD protection circuit of element formation.
Fig. 6 is the profile of an ESD protection circuit in the preferred embodiment of the present invention.
Fig. 7 is the profile of an ESD protection circuit in the second embodiment of the present invention.
Fig. 8 is the profile of an ESD protection circuit in the third embodiment of the present invention.
Fig. 9 is the layout of the shown ESD protection circuit of Fig. 6.
Figure 10 is for being applied to the layout of the secondary ESD protection circuit of wide band radio-frequency circuit in the fourth embodiment of the present invention.
Figure 11 is for being applied to the layout of the level Four ESD protection circuit of wide band radio-frequency circuit in the fifth embodiment of the present invention.
Figure 12 is for being applied to the layout of the level Four ESD protection circuit of ultra-wide band radio-frequency circuit in the sixth embodiment of the present invention.
Figure 13 is for being applied to the layout of the dual path ESD protection circuit of ultra-wide band radio-frequency circuit in the seventh embodiment of the present invention.
Figure 14 and Figure 15 are shown in one the one P in the ESD protection circuit 100 of Fig. 6
+Ooze the enlarged drawing in assorted district.
The reference numeral explanation
10 human body discharge modes, 12,19,306 equivalent capacitys
14,17 equivalent resistances 15,32,34, electrostatic discharge (ESD) protection
36,38,40, road
50、60、700
16 integrated circuit (IC) chip, 18 switches
20 positive test voltage 22 input pins
24 V
SSPin 26 V
DDPin
30 internal circuits, 42 negative testing voltages
52,62,64 resistance, 54,56 diodes
66 silicon controlled rectifiers unit, 68 oxide layer elements
Part
100,200, electrostatic discharge (ESD) protection electricity 102 N type semiconductor substrates
300,400, road
500、600
104 the one P type traps 106 the 2nd P type trap
108 the 3rd P type traps 110 P
+Ooze assorted district
112 the one N
+Ooze assorted district 114 the 2nd P
+Ooze assorted district
116 the 2nd N
+Ooze assorted district 118 the 3rd N
+Ooze assorted district
120 the 3rd P
+Ooze assorted district 122 the 4th N
+Ooze assorted district
190 silicon shape things, 202 P type semiconductor substrates
252 dark N type trap 254 first shallow isolating trough layers
256 first shallow isolating trough layers 302,610, electrostatic discharge (ESD) protection list
612, unit
304 co-planar waveguides (transmission 402,502, first order protected location
Line) 602,702
404,504, second level protected location 506,706,712 third level protected locations
704、710
508,604, fourth stage protected location 714 level V protected locations
606、608、
708
28 output solder joints
Embodiment
See also Fig. 6, Fig. 6 is the profile of an ESD protection circuit 100 in the preferred embodiment of the present invention.ESD protection circuit 100 comprise a N type semiconductor substrate (N-substrate) 102, one the one P type trap (P-well) 104, one the 2nd P type trap 106, and one the 3rd P type trap, 108, the one P type traps 104, the 2nd P type trap 106 and the 3rd P type trap 108 all be arranged on the Semiconductor substrate 102.The one P type trap 104 is provided with one the one P
+Ooze assorted district (P
+Region) 110 and 1 the one N
+Ooze assorted district (N
+Region) 112, all be used for being electrically connected on ground connection pin (GND pad) GND of an integrated circuit (IC) chip, the 2nd P type trap 106 is provided with one the 2nd P
+Ooze assorted district 114 and 1 the 2nd N
+Ooze assorted district 116, all be used for being electrically connected on power pin (VDD pad) VDD of this integrated circuit (IC) chip, and the 3rd P type trap 108 is provided with one the 3rd N
+Ooze assorted district 118,1 the 3rd P
+Ooze assorted district 120, reach one the 4th N
+Ooze assorted district 122, all be used for being electrically connected on I/O pin (I/O pad) I/O of this integrated circuit (IC) chip.
In the equivalence, five layers of the N-P-N-P-N of left side one side of something of ESD protection circuit 100, that is a N
+Ooze assorted district 112-the one P type trap 104-N N-type semiconductor N substrate 102-the 3rd P type trap 108-the 3rd N
+Ooze assorted district 118, can be considered the bipolar transistor B of three serial connections
1, B
2And B
3, or can be considered two silicon controlled rectifier element SCR
1(bipolar transistor B
2-B
1) and SCR
2(bipolar transistor B
2-B
3).Therefore, the working mechanism of ESD protection circuit 100 is similar to the working mechanism of known silicon controlled rectifier element.
The course of work of ESD protection circuit 100 is described as follows: when the electrostatic potential (PS test pattern) of forward in ground produces and reach a predetermined reverse voltage; knot meeting that a N type semiconductor substrate 102 and a P type trap are 104 thereby puncture; therefore, just can be corresponding to the static discharge current of this static discharge via the P in the P type trap 104
+Ooze the ground connection pin GND that assorted district 110 flow to this integrated circuit (IC) chip, avoid the infringement of this static discharge current, in other words, be equivalent to silicon controlled rectifier element SCR to protect this internal circuit
1In work; Relatively, when the electrostatic potential of negative sense in ground produces (NS test pattern) and reaches this predetermined reverse voltage, knot meeting that N type semiconductor substrate 102 and the 3rd P type trap are 108 thereby puncture, therefore, just can be corresponding to the static discharge current of this static discharge via the 3rd P in the 3rd P type trap 108
+Ooze the I/O pin I/O that assorted district 120 flow to this integrated circuit (IC) chip, in other words, be equivalent to silicon controlled rectifier element SCR
2In work.In like manner, right half of structure-the 2nd N of ESD protection circuit 100
+Ooze assorted district 116-the 2nd P type trap 106-N N-type semiconductor N substrate 102-the 3rd P type trap 108-the 4th N
+Oozing assorted district 122-can release forward in VDD (PD test pattern) and negative sense in the static discharge current of VDD (ND test pattern), no longer repeat.Compare with known pair of SCR ESD protection circuit and need additionally comprise this clamp circuit; to finish the DS test pattern, the P type trap 104 in the electrostatic discharge protective circuit 100 of the present invention, N type semiconductor substrate 102 and the 2nd P type trap 106 form another parasitical bipolar transistor B
7, can be used to release is flow to the static discharge current (DS test pattern) of GND by VDD.
In order more effectively to control the threshold voltage V of ESD protection circuit 100
T, in the N type semiconductor substrate 102 of ESD protection circuit 100,, injecting one deck MOS manufacturing process V commonly used between a P type trap 104 and the 3rd P type trap 108 and between the 3rd P type trap 108 and the 2nd P type trap 106 according to known technology
TInject (Implant), therefore, in a N of a P type trap 104
+Ooze the 3rd N of assorted district the 112 and the 3rd P type trap 108
+Ooze assorted district 118 (the 4th N of the 3rd P type trap 108
+Ooze the 2nd N of assorted district the 122 and the 2nd P type trap 106
+Oozing assorted district 116 also with) between formed false MOS (pseudo MOS) structure can Yin Qinei coupling capacitance (coupling capacitor) and slightly conducting, moreover, the high voltage of static discharge can reduce the 3rd N in the 3rd P type trap 108
+Ooze assorted district 118 (and the 4th N
+Oozing assorted district 122) potential barrier (barrier), should vacation MOS structure with further conducting, slightly the false MOS structure of conducting helps to reduce the threshold voltage V of ESD protection circuit 100
T
As shown in Figure 1, in the equivalence, known ESD protection circuit 15 can be reduced to equivalent resistance 17 and equivalent capacity 19.For the static discharge current that can release and cause because of static discharge apace, generally speaking, the equivalent capacity 19 in the circuit 15 must have the capacitance of 300fF at least.Equivalent capacity 19 with high capacity like this not only can make the area of circuit 15 increase; what is worse, the equivalent capacity 19 formed load effects (load effect) with high capacity can reduce the circuit of 15 desire protections of ESD protection circuit (as the load R among the integrated circuit (IC) chip among Fig. 1 16 and Fig. 8
Load) usefulness.And ESD protection circuit of the present invention optionally uses the notion of the distributing amplifier (distributed amplifier) in the microwave, to solve the above problems.
See also Fig. 8, Fig. 8 is the equivalent circuit diagram of an ESD protection circuit 300 in the third embodiment of the present invention, and ESD protection circuit 300 utilizes the notion of distributing amplifier to form.With the ESD protection circuit 15 shown in Fig. 1 only comprise single equivalent capacity 19 and single equivalent resistance 17 different be; the electrostatic discharge (ESD) protection unit 302 that ESD protection circuit 300 comprises multistage (showing four among Fig. 8) is connected in series mutually; each protected location 302 all comprises altogether ground roll and leads (coplanarwave-guide; CPW) 304 (or transmission line (transmission line) 304) and equivalent electric capacity 306; wherein co-planar waveguide (and transmission line) 304 utilizes the metal level in the semiconductor fabrication process made; with the guiding device (guiding structure) as each protected location 302, and equivalent capacity 306 hypothesis in each protected location 302 all have 0.25C
ESDCapacitance.
Because 306 capacitances that have jointly of all equivalent capacitys in the ESD protection circuit 300 of the present invention (capacitance of shunt capacitance equal respective capacitances capacitance and) equal the capacitance that the equivalent capacity 19 in the known ESD protection circuit 15 is had in the equivalence; so the ability of the area of ESD protection circuit 300 and the static discharge current of releasing is equal to the ability of the area of ESD protection circuit 15 and the static discharge current of releasing.Yet; because for this radio circuit; the capacitance of ESD protection circuit 300 (capacitance of protected location 302 shown in dotted lines in Figure 8) only reach ESD protection circuit 15 capacitance 1/4th; so, ESD protection circuit 300 for load effect that this radio circuit caused much smaller than ESD protection circuit 15 for load effect that this radio circuit caused.In other words; under identical load effect; the area of ESD protection circuit 300 not only can be much smaller than the area of ESD protection circuit 15; and ESD protection circuit 300 is released the ability of static discharge current also can be far above the release ability of static discharge current of ESD protection circuit 15.
Utilize in the ESD protection circuit 300 in made co-planar waveguide 304 equivalences of metal level in the semiconductor fabrication process and can be considered an inductance 304; under the effect of inductance compensation effect (inductancecompensation effect); can do 50 ohms impedance match in broadband, its equivalent capacity 306 can be done the esd protection in broadband.
Except having above-mentioned advantage; utilizing the quantity of the protected location 302 that the formed ESD protection circuit 300 of the notion of distributing amplifier can comprise by changing in it in addition to be matched with various radio circuits with different frequency ranges, for example similarly is arrowband (narrow band) radio circuit, broadband (broadband) and even radio circuit ultra broadband (ultra-broad band) radio circuit.Because threshold frequency (corner frequency) ω of the formed ESD protection circuit of notion of utilization distributing amplifier
cRelevant with the quantity n of the protected location that is comprised in this ESD protection circuit, that is
Therefore, the quantity of the ESD protection circuit of the present invention protected location that can change in it along with the difference of the frequency range of the radio circuit of its desire protection to be comprised.For instance, if the radio circuit of ESD protection circuit of the present invention institute desire protection is a narrow radio frequency circuit, then this ESD protection circuit can only comprise a protected location.Generally speaking, comprise four mutually the ESD protection circuits of the protected location of serial connection (level Four) just to be enough to protect frequency range be the radio circuit of 10GHz.
Because the solder joint (pad) of all pins of integrated circuit (IC) chip all is octangle for the cause that reduces electric capacity; so; ESD protection circuit of the present invention also presents octangle on layout; being in the layout of the below of corresponding pin solder joint in this integrated circuit (IC) chip as much as possible, and save the area of this integrated circuit (IC) chip.See also Fig. 9, Fig. 9 is the shown ESD protection circuit of Fig. 6 100 (C in the shown ESD protection circuit 300 of Fig. 8 in arbitrary protected location
ESD306) layout.First and second P type trap 104 and 106 places upper and lower two sides respectively, and the 3rd P type trap 108 then places centre.In preferred embodiment of the present invention, for fear of arbitrary P type trap and the N in it
+Ooze assorted interval knot because of the P in this P type trap
+Ooze assorted district and N
+Oozing assorted district receives the reverse biased that static discharge current causes simultaneously and punctures four N in the ESD protection circuit 100
+Ooze assorted district, that is the first, second, third and the 4th N
+Ooze assorted district 112,116,118 and 122, all than first, second and third P
+The layout area that oozes assorted district 110,114 and 120 is little.
Except the area that can save this integrated circuit (IC) chip; because the parasitic capacitance that the parasitic capacitance that produces in the place, corner of a tetragonal layout produces greater than the place, corner in an octangle layout; therefore; be octagonal ESD protection circuit 100 and compare with the known ESD protection circuit that is tetragonal layout and can reduce by about 17% capacitance, comparatively slick and sly simultaneously corner also can reduce unnecessary microwave effect.
The shown ESD protection circuit 100 of Fig. 9 is established at the narrow radio frequency circuit, that is to say, ESD protection circuit 300 only need comprise single electrostatic discharge (ESD) protection unit 302 and just be enough to deal with the requirement of this narrow radio frequency circuit for frequency range.Relatively, and even if be applied to wide band radio-frequency circuit ultra-wide band radio-frequency circuit, ESD protection circuit 300 just need comprise two or more protected locations that are connected in series mutually 302.See also Figure 10 and Figure 11, Figure 10 and Figure 11 are applied to secondary (protected location 302 that comprises two serial connections) ESD protection circuit 400 of wide band radio-frequency circuit and the layout of level Four (protected location 302 that comprises four serial connections) ESD protection circuit 500 among the of the present invention the 4th and the 5th embodiment.Circuit 400 comprises a first order protected location 402 that is connected to the pin of an integrated circuit (IC) chip, an and second level protected location 404 that is connected to an internal circuit (this wide band radio-frequency circuit).Circuit 500 comprises fourth stage protected location 508 that a first order protected location 502, that is connected to the pin of an integrated circuit (IC) chip is connected to an internal circuit, and two second level and third level protected location 504 and 506 that are connected to the first order and fourth stage protected location 502 and 508.
The level Four protected location 502,504,506 and 508 that is comprised in the shown ESD protection circuit 500 of Figure 11 is the ㄇ font and arranges; certainly; also but layout is in line for these level Four protected locations 502,504,506 and 508; for instance, the layout boundary that is prolonging this integrated circuit (IC) chip in line.Yet; because each pin in the integrated circuit (IC) chip all need dispose a corresponding ESD protection circuit; and the distance between two pins is limited; therefore; in order not occupy the too much limited length of side of this integrated circuit (IC) chip; in the fifth embodiment of the present invention, these level Four protected locations 502,504,506 and 508 suggestion are taked ㄇ font arrangement form as shown in Figure 11.In addition, ESD protection circuit also can comprise three-level protective unit (not being shown among the figure).
In ESD protection circuit of the present invention; owing to can produce a predetermined delay with the inductance that transmission line was made; therefore; directly be contacted with the electrostatic circuit protected location of the pin of an integrated circuit (IC) chip; it for example similarly is the first order protected location 502 among Figure 11; need layout to become to have bigger area, to prevent the damage of ESD protection circuit 500 as much as possible.In addition, for can bear this internal circuit do not expect and based on above-mentioned reason, directly be contacted with the electrostatic circuit protected location of this internal circuit by the shock wave that transmits that for example the fourth stage protected location 508 among Figure 11 also needs layout to become to have bigger area.As shown in figure 11, the first order and fourth stage protected location 502 and 508 (all extra flag one " greatly " word) have than the second level and third level protected location 504 and 506 (all extra flag one " in " word) be big layout area.
See also Figure 12, Figure 12 is for being applied to the layout of the Pyatyi ESD protection circuit 600 of ultra-wide band radio-frequency circuit in the sixth embodiment of the present invention.The first order protected location 502 that is different from the shown ESD protection circuit of Figure 11 500 only can be electrically connected to single internal circuit by single fourth stage protected location 508, and the first order protected location 602 in the ESD protection circuit 600 can be connected to three different internal circuits respectively by three fourth stage protected locations 604,606 and 608.The pin that ESD protection circuit 600 is suitable for is positioned at the corner of an integrated circuit (IC) chip.
See also Figure 13, Figure 13 is for being applied to the layout of the dual path ESD protection circuit 700 of ultra-wide band radio-frequency circuit in the seventh embodiment of the present invention.First order protected location 502 in the shown ESD protection circuit 500 of Figure 11 only can arrive fourth stage protected locations 508 via the second level and third level protected location 504 and 506 formed single-pathways; otherwise the first order protected location 702 in the ESD protection circuit 700 can arrive a level V protected location 714 via a second level 704, a third level 706 and a fourth stage protected location 708 and a second level 710, a third level 712 and fourth stage protected location 708 formed dual paths respectively.The pin that ESD protection circuit 700 is suitable for is positioned at an integrated circuit (IC) chip border.
Except postpone based on inductance and factor such as pre-shockproof wave and having of must adopting protected location than layout area greatly; it for example similarly is protected location 602,604,606,608,702 and 714; ESD protection circuit 600 and 700 can be positioned at the position of an integrated circuit (IC) chip according to it and change the layout area of all the other protected locations adaptively; for example protected location 612 and 708 have middle homalographic, and protected location 610 and 706 has than small size.
See also Figure 14 and Figure 15, and please consult Fig. 6 and Fig. 9 simultaneously, Figure 14 and Figure 15 are a P of ESD protection circuit 100 in the preferred embodiment of the present invention
+Ooze the enlarged drawing in assorted district 110.The one P
+Oozing the multi-crystal silicification thing (poly silicon) 190 that has deposited a predetermined pattern (as Figure 14 and rectangle 191, T font 193 or cross 194 shown in Figure 15) in the assorted district 110, being used for equivalence to go up a P otherwise flat
+Ooze assorted district 110 and be transformed into a uneven P
+Ooze assorted district 110.In ESD protection circuit of the present invention; silicide 190 also can be deposited on other and ooze in the assorted district, and the predetermined pattern among Figure 14 and Figure 15 is the arrangement of symmetry in addition, therefore can be so that the distribution of electric current is comparatively average; certainly, this predetermined pattern also can asymmetricly be arranged.
Generally speaking, an ESD protection circuit is provided with a steady resistance (ballastingresistance) usually, damaged by too high static discharge voltage preventing, yet this steady resistance is area occupied very.In preferred embodiment of the present invention, in the equivalence, can be by changing the distance of 190 of silicides, to adjust this steady resistance.In addition, silicide 190 can stop and disperse effectively static discharge current i in addition
ESDAt last, silicide 190 can increase by a P
+The one P type trap 104 belows of oozing 110 places, assorted district produce the area of free electron, to reduce threshold voltage V
T, and and then enhancing static discharge usefulness.
Compare with known technology, ESD protection circuit 100 of the present invention comprises three P type traps 104,106 and 108, and wherein a P type trap 104 comprises a P
+Ooze assorted district the 110 and the one N
+Ooze assorted district 112, the two P type traps 106 and comprise the 2nd P
+Ooze assorted district the 114 and the 2nd N
+Ooze assorted district 116, the three P type traps 108 and then comprise the 3rd P
+Ooze assorted district the 120, the 3rd N
+Ooze assorted district the 118 and the 4th N
+Ooze assorted district 122.ESD protection circuit of the present invention has following advantage at least:
1. the notion of distributing amplifier can be reached Broadband Matching, reduces the electric capacity of each protective circuit unit, and because of the different protective circuit of delay designed size that each transmission line caused;
2. the design of pin guiding (Pad-oriented) and wafer guide (Wafer-oriented), that is ESD protection circuit of the present invention can be along with the shape and the position of this pin in an integrated circuit (IC) chip of pin, and the required frequency range of this integrated circuit (IC) chip and adjust size and layout type;
3. can independently finish all patterns (ND, PD, PS, NS and DS test pattern), not need extra clamp circuit;
4. the design of triple well can reduce leakage current effectively;
5. utilize traditional V
TInjection technique, may command are positioned at the concentration of N type semiconductor substrate between adjacent two P type traps, make its lightly conducting when static discharge, to reduce the threshold voltage V of protective circuit
T
6.N
+Ooze assorted district and P
+Oozing in the assorted district and deposit silicide, increasing the ability of its anti-electrostatic discharging;
7. silicon shape thing can increase N effectively
+Ooze assorted district and P
+Ooze the contact area between the trap at Za Qu and its place, easier generation free electron helps the conducting parasitic transistor;
8. be useful on the manufacturing process of making ESD protection circuit of the present invention and can be the standard CMOS manufacturing process, do not need extra mask;
9. directly as for the solder joint below, can reduce the substrate loss, increase and isolate (isolation) and prevent that gain from reducing (gain degradation); And
10. ESD protection circuit of the present invention also can be used for the SOI manufacturing process, if can control back-gate biasing (backgate bias), effect is better.
The above only is preferred embodiment of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (4)
1. ESD protection circuit that is used for a radio circuit, this ESD protection circuit includes:
At least one electrostatic discharge (ESD) protection unit, wherein each this electrostatic discharge (ESD) protection unit all includes:
One guiding device; And
One equivalent electric capacity, its first end is coupled to this guiding device, and its second end is coupled to earth point altogether;
Wherein when this ESD protection circuit was formed in a plurality of these electrostatic discharge (ESD) protection unit, then this a plurality of electrostatic discharge (ESD) protections unit was the serial connection shape.
2. ESD protection circuit as claimed in claim 1, wherein this guiding device is for ground roll is altogether led, a transmission line or an inductance equivalent device.
3. ESD protection circuit as claimed in claim 1, wherein the quantity of this electrostatic discharge (ESD) protection unit is directly proportional with the frequency range of this radio circuit.
4. ESD protection circuit as claimed in claim 1, wherein this ESD protection circuit also includes one 50 ohm matched impedance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100445514A CN1317763C (en) | 2004-05-13 | 2004-05-13 | Electrostatic discharge protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100445514A CN1317763C (en) | 2004-05-13 | 2004-05-13 | Electrostatic discharge protecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1571155A CN1571155A (en) | 2005-01-26 |
| CN1317763C true CN1317763C (en) | 2007-05-23 |
Family
ID=34481911
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100445514A Expired - Lifetime CN1317763C (en) | 2004-05-13 | 2004-05-13 | Electrostatic discharge protecting circuit |
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| Country | Link |
|---|---|
| CN (1) | CN1317763C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI780956B (en) * | 2020-11-16 | 2022-10-11 | 力旺電子股份有限公司 | Integrated circuit with capability of inhibiting esd zap |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1175795A (en) * | 1996-09-03 | 1998-03-11 | 摩托罗拉公司 | Non-breakdown triggered electrostatic discharge protection circuit for integrated circuit and method therefor |
| CN1275806A (en) * | 1999-05-28 | 2000-12-06 | 凌阳科技股份有限公司 | Electrostatic discharging protector for polysilicon diode |
| CN1399386A (en) * | 2001-07-27 | 2003-02-26 | 旺宏电子股份有限公司 | Electrostatic discharge protection circuit |
| CN1404195A (en) * | 2001-08-29 | 2003-03-19 | 旺宏电子股份有限公司 | Electrostatic discharge protector circuit |
| CN1428909A (en) * | 2001-12-25 | 2003-07-09 | 原相科技股份有限公司 | Static protecting circuit |
| CN2580605Y (en) * | 2002-11-11 | 2003-10-15 | 威盛电子股份有限公司 | Integrated circuit with static discharge protective function |
| US20040075964A1 (en) * | 2002-10-21 | 2004-04-22 | Ming-Dou Ker | Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks |
-
2004
- 2004-05-13 CN CNB2004100445514A patent/CN1317763C/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1175795A (en) * | 1996-09-03 | 1998-03-11 | 摩托罗拉公司 | Non-breakdown triggered electrostatic discharge protection circuit for integrated circuit and method therefor |
| CN1275806A (en) * | 1999-05-28 | 2000-12-06 | 凌阳科技股份有限公司 | Electrostatic discharging protector for polysilicon diode |
| CN1399386A (en) * | 2001-07-27 | 2003-02-26 | 旺宏电子股份有限公司 | Electrostatic discharge protection circuit |
| CN1404195A (en) * | 2001-08-29 | 2003-03-19 | 旺宏电子股份有限公司 | Electrostatic discharge protector circuit |
| CN1428909A (en) * | 2001-12-25 | 2003-07-09 | 原相科技股份有限公司 | Static protecting circuit |
| US20040075964A1 (en) * | 2002-10-21 | 2004-04-22 | Ming-Dou Ker | Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks |
| CN2580605Y (en) * | 2002-11-11 | 2003-10-15 | 威盛电子股份有限公司 | Integrated circuit with static discharge protective function |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI780956B (en) * | 2020-11-16 | 2022-10-11 | 力旺電子股份有限公司 | Integrated circuit with capability of inhibiting esd zap |
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|---|---|
| CN1571155A (en) | 2005-01-26 |
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