CN102569374A - Silicon-controlled rectifier device embedded with Zener trigger structure - Google Patents
Silicon-controlled rectifier device embedded with Zener trigger structure Download PDFInfo
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Abstract
The invention discloses a silicon-controlled rectifier device embedded with a Zener trigger structure, which comprises a P- substrate layer, wherein an N- well and a P- well which are connected side by side are arranged on the P- substrate layer, and a junction between the N- well and the P- well is provided with a third N+ active injection region; a first N+ active injection region and a first P+ active injection region are arranged on the N- well side by side; a second P+ active injection region and a second N+ active injection region are arranged on the P- well side by side; the first N+ active injection region and the first P+ active injection region are connected through a first metal electrode; and the second P+ active injection region and the second N+ active injection region are connected through a second metal electrode. According to the silicon-controlled rectifier device embedded with the Zener trigger structure, a Zener diode is used as an auxiliary triggering unit, the trigger voltage of a silicon-controlled rectifier can be further effectively reduced, the ESD (Electro Static Discharge) protection of low trigger voltage is realized, and thus the silicon-controlled rectifier can be directly applied to ESD protection of a deep sub-micron integrated circuit chip with a power supply domain of 1.2-5V.
Description
Technical field
The invention belongs to integrated circuit electrostatic defending technical field, be specifically related to a kind of silicon-controlled device of embedded Zener triggered structure.
Background technology
Along with developing rapidly of electronic information technology; Current semiconductor device tends to miniaturization, high density and multifunction day by day; Particularly as fashional consumption electronics and portable product etc. to the relatively strict application of mainboard area requirements, be easy to receive the influence of electrostatic discharge (ESD).Static is at every moment ubiquitous, in the sixties, along with the appearance to the highstrung MOS device of static; Electrostatic problem has also occurred; To the seventies electrostatic problem more and more come seriously, the 80-90 age is along with the density of integrated circuit is increasing; The thickness of its silicon dioxide film more and more approaches (micron changes to nanometer) on the one hand, and its electrostatic potential that bears is more and more lower; On the other hand; Produce and the material such as the plastics of accumulation static, rubber etc. are a large amount of to be used, and makes more and more ubiquity of static; Only U.S.'s electronics industry every year because of static cause with a toll of hundred million dollars of hundreds ofs; Therefore electrostatic breakdown has become the stealthy killer of electronics industry, is electronics industry ubiquitous " hard virus ", when internal and external reasons conditions being possessed sometime, will show effect.
Electrostatic breakdown has disguise, potentiality, randomness and complexity.Only if static discharge takes place in human body directly perception static, also differ the sensation of electric shock is arranged surely but the static discharge human body takes place, this is because the static discharge voltage of human perception is 2～3V, so static has disguise; The performance that some electronic devices and components receives behind the electrostatic damage does not significantly descend, but the discharge meeting that repeatedly adds up causes internal injury and forms hidden danger to device.Therefore static has potentiality to the damage of device; After an element generation, until before its damage, all processes all receive the threat of static, and the generation of these static also has randomness, and it damages also has randomness; The failure analysis work of electrostatic discharge damage, time-consuming, bothersome, expensive because of the essence of electronic product, thin, small design feature, the technology of having relatively high expectations often need be used highly sophisticated devices such as ESEM.Even so, the damage that some electrostatic damage phenomenon also is difficult to cause with other reasons is distinguished, and people's mistake was lost efficacy electrostatic damage be used as other inefficacies.This usually owing to early failure or inefficacy in confused situation, thereby had covered the true cause that lost efficacy unconsciously before damage of electrostatic discharge is not fully realized; So static has complexity to the analysis of electronic device damage.
The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and FIM (electric field induction pattern).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.
Under the normal operating conditions of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the input and output pin; And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.
ESD static is because the time is short, and energy is big, often circuit is produced the impact of moment and causes each components from being damaged in the circuit, and this just requires the ESD safeguard structure that good current drain ability not only will be arranged, and for ESD static a kind of reaction speed is faster arranged.
The selection of circuit protecting element decides according to claimed wiring situation, available circuit board space and by the electrical characteristics of protective circuit.Because utilize in the IC circuit that advanced technologies technology makes oxide layer thinner, grid oxic horizon is more vulnerable to infringement; And some adopt the deep submicron process and the complicated semiconductor functional circuits of fine linewidth wiring very, and to the influence of circuit transient process sensitivity more, this will cause the problems referred to above to increase the weight of.Therefore require the protection device must possess low clamping voltage so that effective esd protection to be provided; And the response time is enough short in to satisfy the requirement of High-Speed Data Line; Encapsulation integrated level height is to be suitable for the nervous situation of portable equipment printed circuit board area; Also to guarantee repeatedly simultaneously after the ESD process not can deterioration to guarantee the due quality of high end equipment.
The ESD phenomenon more and more receives the attention of each major company at present, develops rapider.As shown in Figure 1, the current-voltage characteristic of ESD protective device has following index: trigger voltage and trigger current (Vt1, It1), keep voltage with keep electric current (Vh, Ih), inefficacy voltage and inefficacy electric current (Vt2, It2).VDD representes the ic power operating voltage among Fig. 1, and BVox representes the voltage limit that the IC interior device can bear, and VDD is called the ESD design window to the zone between the BVox; The size of inefficacy electric current I t2 can be used for weighing the robustness of ESD device, in the ESD design process, must and keep voltage Vh with trigger voltage Vt1 and be controlled in the ESD design window, shown in A among Fig. 1; If the current-voltage characteristic curve of ESD device (IV curve) exceeds BVox, the Vt1 shown in B among Fig. 1, promptly Vt1 has surpassed the voltage limit of being born by protective circuit; Can burn out internal circuit; If the current-voltage characteristic curve of ESD device (IV curve) is lower than VDD, the Vh shown in C among Fig. 1, promptly Vh is lower than the supply voltage of integrated circuit operate as normal; Latch-up can take place, and influences the circuit operate as normal.
In present ESD protection field; Silicon-controlled device as shown in Figure 2 relies on the advantage of the strong robustness of its unit are to obtain important concern; But this silicon-controlled device is in time residual effect is answered; Trigger voltage is too high, is difficult to directly apply to the chip protection, how to reduce trigger voltage at present still in exploration.
Fig. 3 is to too high this deficiency of traditional SCR structure trigger voltage and the structure after improving; Main way is on original N-trap and P-trap border, to add one deck N+ or the active injection region of P+; SCR structure after the improvement has played certain function to the reduction of trigger voltage, but can't reach the ESD requirement of shelter of integrated circuit.
The equivalent circuit diagram of above-mentioned two kinds of structures is as shown in Figure 4, when ESD electric current N-trap dead resistance R1 pressure drop when reaching 0.7V, the parasitic diode D1 conducting of Q1; Open Q1; Q1 after the unlatching will have electric current to flow through P-trap dead resistance R2, when the pressure drop that produces when the electric current of the R2 that flows through reaches 0.7V, open Q2; This moment, SCR started working the big electric current of the ESD that releases.
Summary of the invention
To the above-mentioned technological deficiency of existing in prior technology, the invention provides a kind of silicon-controlled device of embedded Zener triggered structure, trigger voltage is low, can directly apply to the ESD protection of chip.
A kind of silicon-controlled device of embedded Zener triggered structure comprises:
The P-substrate layer;
Described P-substrate layer is provided with N-trap and P-trap, and described N-trap links to each other with the P-trap side by side; The joint of described N-trap and P-trap is provided with the active injection region of the 3rd N+;
Be provided with active injection region of a N+ and the active injection region of a P+ on the described N-trap side by side; The active injection region of a described P+ is between active injection region of first N+ and the active injection region of the 3rd N+;
Be provided with active injection region of the 2nd P+ and the active injection region of the 2nd N+ on the described P-trap side by side; The active injection region of described the 2nd P+ is between active injection region of second N+ and the active injection region of the 3rd N+;
The active injection region of a described N+ links to each other through first metal electrode with the active injection region of a P+, and the active injection region of described the 2nd P+ links to each other through second metal electrode with the active injection region of the 2nd N+.
Active injection region of a described N+ and the active injection region of a P+, the active injection region of the 2nd P+ and the active injection region of the 2nd N+ or the active injection region of a P+ and the active injection region of the 3rd N+ are through shallow-trench isolation, the shared active area in active injection region of described the 3rd N+ and the active injection region of the 2nd P+.
In the optimized technical scheme, the distance between active injection region of described the 3rd N+ and the active injection region of the 2nd P+ is 0～0.5um; Can realize the ESD protective device of different trigger voltages.
The equivalent electric circuit of described silicon-controlled device is made up of two resistance, two triodes and a Zener diode; Wherein, The emitter of first triode links to each other with an end of first resistance and constitutes the anode of silicon-controlled device; The base stage of first triode links to each other with the other end of first resistance, the collector electrode of second triode and the negative electrode of Zener diode; The collector electrode of first triode links to each other with an end of second resistance and the base stage of second triode, the other end of second resistance and the emitter of second triode with link to each other with the anode of Zener diode and constitute the negative electrode of silicon-controlled device.
Described first triode is the positive-negative-positive triode, and described second triode is a NPN type triode.
Described first triode is made up of the active injection region of a described P+, N-trap and P-trap; Described second triode is made up of described N-trap, P-trap and the active injection region of the 2nd N+; Described first resistance is the dead resistance of N-trap; Described second resistance is the dead resistance of P-trap; Described Zener diode is made up of active injection region of described the 3rd N+ and the active injection region of the 2nd P+.
The protection voltage range of silicon-controlled device of the present invention can reach (1.2～5) V, and trigger voltage is (5～10) V.
The present invention is through embedded zener structure in silicon-controlled device; Utilize zener as the auxiliary triggering unit; Further effectively reduce the silicon controlled trigger voltage; Realize the ESD protection of low trigger voltage, reduce the ESD design window, make controllable silicon can directly apply to the ESD protection that power domain is the deep submicron integrated circuit chip of 1.2～5V; Zener triggered structure among the present invention is to the suitable adjustment of this body structure of controllable silicon and form in addition, need not external unit, has practiced thrift chip area.
Description of drawings
Fig. 1 is the current-voltage characteristic sketch map of ESD protective device.
Fig. 2 is the structural representation of traditional silicon-controlled device.
Fig. 3 is the structural representation of existing modified model silicon-controlled device.
Fig. 4 is the equivalent circuit diagram of Fig. 2 and two kinds of silicon-controlled devices of Fig. 3.
Fig. 5 is the structural representation of silicon-controlled device of the present invention.
Fig. 6 is the equivalent circuit diagram of silicon-controlled device of the present invention.
Fig. 7 is the ESD current drain path profile of silicon-controlled device of the present invention.
Fig. 8 is ESD current drain path profile in the silicon-controlled device equivalent electric circuit of the present invention.
Fig. 9 is the enforcement domain of silicon-controlled device of the present invention.
Figure 10 is the current-voltage characteristic sketch map of silicon-controlled device of the present invention and traditional silicon-controlled device and existing modified model silicon-controlled device.
Embodiment
In order to describe the present invention more particularly, technical scheme of the present invention and relative theory thereof are elaborated below in conjunction with accompanying drawing and embodiment.
Like Fig. 5 and shown in Figure 9, a kind of silicon-controlled device of embedded Zener triggered structure comprises:
P-substrate layer 10;
P-substrate layer 10 is provided with N-trap 21 and P-trap 22, and N-trap 21 links to each other with P-trap 22 side by side; N-trap 21 is provided with the active injection region 33 of the 3rd N+ with the joint of P-trap 22;
Be provided with active injection region 31 of a N+ and the active injection region 41 of a P+ on the N-trap 21 side by side; The active injection region 41 of the one P+ is between active injection region 31 of first N+ and the active injection region 33 of the 3rd N+;
Be provided with active injection region 42 of the 2nd P+ and the active injection region 32 of the 2nd N+ on the P-trap 22 side by side; The active injection region 42 of the 2nd P+ is between active injection region 32 of second N+ and the active injection region 33 of the 3rd N+;
The active injection region 31 of the one N+ links to each other through first metal electrode 51 with the active injection region 41 of a P+, and the active injection region 42 of the 2nd P+ links to each other through second metal electrode 52 with the active injection region 32 of the 2nd N+.
The active injection region 33 of the active injection region of an active injection region 31 of the one N+ and a P+ 41, the active injection region 42 of the 2nd P+ and the active injection region 32 of the 2nd N+ or the active injection region 41 of a P+ and the 3rd N+ isolates through shallow slot 6, is filled with silica in the shallow slot 6; The active injection region of active injection region 33 of the 3rd N+ and the 2nd P+ 42 shared active areas.
In the present embodiment, the active injection region 33 of the 3rd N+ link to each other side by side with the active injection region 42 of the 2nd P+ (mutual spacing from be 0).
As shown in Figure 6, the equivalent electric circuit of this execution mode silicon-controlled device is made up of two resistance R 1～R2, two triode Q1～Q2 and a Zener diode Z; Wherein, The emitter of the first triode Q1 links to each other with an end of first resistance R 1 and constitutes the anode of silicon-controlled device; The base stage of the first triode Q1 links to each other with the other end of first resistance R 1, the collector electrode of the second triode Q2 and the negative electrode of Zener diode Z; The collector electrode of the first triode Q1 links to each other with an end of second resistance R 2 and the base stage of the second triode Q2, and the other end of second resistance R 2 and the emitter of the second triode Q2 link to each other with anode with Zener diode Z and constitute the negative electrode of silicon-controlled device.
The first triode Q1 is the positive-negative-positive triode, and the second triode Q2 is a NPN type triode.
The first triode Q1 is made up of the active injection region of a P+ 41, N-trap 21 and P-trap 22; The second triode Q2 is made up of the active injection region 32 of N-trap 21, P-trap 22 and the 2nd N+; First resistance R 1 is the dead resistance of N-trap 21; Second resistance R 2 is the dead resistance of P-trap 22; Zener diode Z is made up of active injection region 33 of the 3rd N+ and the active injection region 42 of the 2nd P+.
As shown in Figure 8, when esd event took place, the ESD electric current at first can flow into negative electrode from flow through dead resistance R1 and the Zener diode Z of N-trap of anode; In figure shown in the dotted arrow, when the pressure drop that on R1, produces when the electric current on the R1 that flows through reaches 0.7V, the emitter junction diode D1 conducting of the first triode Q1; Q1 is unlocked, and has the flow through dead resistance R2 of P-trap of electric current this moment, when the pressure drop that on R2, produces when the electric current on the R2 that flows through reaches 0.7V; The emitter junction diode D2 conducting of the second triode Q2, Q2 is unlocked, and the controllable silicon that formed by Q1 and Q2 this moment is triggered; The big electric current of ESD that begins to release is shown in figure dotted line arrow.
It is as shown in Figure 7 that esd event is reflected to the current path of silicon-controlled device section; Article one, the path is the Zener path, and shown in dotted arrow among the figure, PNP pipe Q1 is opened in the pressure drop of Zener conducting after-current on the dead resistance of N-trap; Open the PNP path, shown in figure dotted line arrow; NPN pipe Q2 is opened in the pressure drop of electric current on the dead resistance of P-trap of PNP pipe, and Q1 and Q2 constitute SCR structure, and the SCR path shown in solid arrow among the figure, is born main esd discharge function by open-minded at this moment.
The current-voltage characteristic of this execution mode shown in Figure 10 and traditional silicon-controlled device and existing modified model silicon-controlled device; From figure, can find out obviously that the trigger voltage of traditional silicon-controlled device is 17.25V; The trigger voltage of existing modified model silicon-controlled device is 14.34V, and the trigger voltage of this execution mode has only 5.25V; Can see simultaneously; This execution mode is kept voltage to raising also has positive effect, and the voltage of keeping of traditional silicon-controlled device has only 2.34V, and the voltage of keeping of existing modified model silicon-controlled device also has only 2.94V; Cause latch-up easily; And the keeping voltage and can reach 4.98V of this execution mode, can effectively avoiding latch-up effect, be more suitable for being applied on the electrostatic defending of deep submicron integrated circuit.
Claims (3)
1. the silicon-controlled device of an embedded Zener triggered structure is characterized in that, comprising:
P-substrate layer (10);
Described P-substrate layer (10) is provided with N-trap (21) and P-trap (22), and described N-trap (21) links to each other with P-trap (22) side by side; Described N-trap (21) is provided with the active injection region of the 3rd N+ (33) with the joint of P-trap (22);
(21) are provided with active injection region of a N+ (31) and the active injection region of a P+ (41) side by side on the described N-trap; The active injection region of a described P+ (41) is positioned between active injection region of a N+ (31) and the active injection region of the 3rd N+ (33);
Be provided with active injection region of the 2nd P+ (42) and the active injection region of the 2nd N+ (32) on the described P-trap (22) side by side; The active injection region of described the 2nd P+ (42) is positioned between active injection region of the 2nd N+ (32) and the active injection region of the 3rd N+ (33);
The active injection region of a described N+ (31) links to each other through first metal electrode (51) with the active injection region of a P+ (41), and the active injection region of described the 2nd P+ (32) links to each other through second metal electrode (52) with the active injection region of the 2nd N+ (42).
2. the silicon-controlled device of embedded Zener triggered structure according to claim 1; It is characterized in that: the active injection region of a described N+ (31) through shallow slot (6) isolates described three N+ active injection region (33) and two P+ active injection region (42) shared active area with active injection region of the 2nd N+ (32) or the active injection region of a P+ (41) with the active injection region of the 3rd N+ (33) with the active injection region of a P+ (41), the active injection region of the 2nd P+ (42).
3. the silicon-controlled device of embedded Zener triggered structure according to claim 1 is characterized in that: the distance between active injection region of described the 3rd N+ (33) and the active injection region of the 2nd P+ (42) is 0～0.5um.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810386A (en) * | 2015-04-16 | 2015-07-29 | 江苏艾伦摩尔微电子科技有限公司 | High area efficiency diode triggered controllable silicon based on two-dimension design |
| CN108807362A (en) * | 2017-04-26 | 2018-11-13 | 旺宏电子股份有限公司 | Electric static discharge protector and electrostatic charging method |
| CN109768041A (en) * | 2019-01-22 | 2019-05-17 | 电子科技大学 | A kind of high maintenance voltage ESD device based on SCR |
| US11600730B2 (en) | 2020-12-03 | 2023-03-07 | Micross Corpus Christi Corporation | Spiral transient voltage suppressor or Zener structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060278928A1 (en) * | 2005-06-14 | 2006-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor layout structure for ESD protection circuits |
| CN102290417A (en) * | 2011-08-24 | 2011-12-21 | 浙江大学 | Transient voltage suppressor based on DTSCR (Dual Triggered Silicon Controlled Rectifier) |
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2012
- 2012-01-18 CN CN201210015046.1A patent/CN102569374B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060278928A1 (en) * | 2005-06-14 | 2006-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor layout structure for ESD protection circuits |
| CN102290417A (en) * | 2011-08-24 | 2011-12-21 | 浙江大学 | Transient voltage suppressor based on DTSCR (Dual Triggered Silicon Controlled Rectifier) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810386A (en) * | 2015-04-16 | 2015-07-29 | 江苏艾伦摩尔微电子科技有限公司 | High area efficiency diode triggered controllable silicon based on two-dimension design |
| CN108807362A (en) * | 2017-04-26 | 2018-11-13 | 旺宏电子股份有限公司 | Electric static discharge protector and electrostatic charging method |
| CN108807362B (en) * | 2017-04-26 | 2021-02-23 | 旺宏电子股份有限公司 | Electrostatic discharge protection device and electrostatic discharge method |
| CN109768041A (en) * | 2019-01-22 | 2019-05-17 | 电子科技大学 | A kind of high maintenance voltage ESD device based on SCR |
| US11600730B2 (en) | 2020-12-03 | 2023-03-07 | Micross Corpus Christi Corporation | Spiral transient voltage suppressor or Zener structure |
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