CN102306649A - Bidirectional dual-channel transient voltage suppressor (TVS) - Google Patents
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- CN102306649A CN102306649A CN201110244002A CN201110244002A CN102306649A CN 102306649 A CN102306649 A CN 102306649A CN 201110244002 A CN201110244002 A CN 201110244002A CN 201110244002 A CN201110244002 A CN 201110244002A CN 102306649 A CN102306649 A CN 102306649A
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Abstract
The invention discloses a bidirectional dual-channel transient voltage suppressor (TVS), which comprises a P+ substrate layer, wherein a first N+ buried layer, a first P- epitaxial region, a second P- epitaxial region, a third P- epitaxial region and a second N+ buried layer are sequentially arranged on the P+ substrate layer from left to right; a first N injection region and a second N injection region are arranged on the first N+ buried layer and the second N+ buried layer respectively; a first N+ active injection region and a second N+ active injection region are arranged on the first P- epitaxial region and the third P- epitaxial region respectively; and a first P+ active injection region, a second P+ active injection region and a third P+ active injection region are arranged on the first N injection region, the second P- epitaxial region and the second N injection region respectively. Due to the adoption of a combined structure of a Zener voltage-regulator tube and a low-capacitance diode, the parasitic capacitance of the TVS is further reduced, on resistance is reduced, and the clamp characteristic of the TVS is improved; and the TVS can be widely applied to static electricity protection of certain portable equipment and high-speed interfaces.
Description
Technical field
The invention belongs to integrated circuit electrostatic defending technical field, be specifically related to a kind of two-way twin-channel Transient Voltage Suppressor.
Background technology
Along with developing rapidly of electronic information technology; Current semiconductor device tends to miniaturization, high density and multifunction day by day; Particularly as fashional consumption electronics and portable product etc. to the relatively strict application of mainboard area requirements, be easy to receive the influence of electrostatic discharge (ESD).Static is at every moment ubiquitous; In the sixties; Along with appearance to the highstrung MOS device of static; Electrostatic problem has also occurred; To the seventies electrostatic problem more and more come seriously, the 80-90 age is along with the density of integrated circuit is increasing; The thickness of its silicon dioxide film more and more approaches (micron changes to nanometer) on the one hand, and its electrostatic potential that bears is more and more lower; On the other hand; Produce and accumulate the material such as the plastics of static; Rubber etc. are a large amount of to be used; Make more and more ubiquity of static; Only U.S.'s electronics industry every year because of static cause with a toll of hundred million dollars of hundreds ofs; Therefore electrostatic breakdown has become the stealthy killer of electronics industry, is electronics industry ubiquitous " hard virus ", when internal and external reasons conditions being possessed sometime, will show effect.
Electrostatic breakdown has disguise, potentiality, randomness and complexity.Only if static discharge takes place in human body directly perception static, also differ the sensation of electric shock is arranged surely but the static discharge human body takes place, this is because the static discharge voltage of human perception is 2～3V, so static has disguise; The performance that some electronic devices and components receives behind the electrostatic damage does not significantly descend, but the discharge meeting that repeatedly adds up causes internal injury and forms hidden danger to device.Therefore static has potentiality to the damage of device; After an element generation, until before its damage, all processes all receive the threat of static, and the generation of these static also has randomness, and it damages also has randomness; The failure analysis work of electrostatic discharge damage, time-consuming, bothersome, expensive because of the essence of electronic product, thin, small design feature, the technology of having relatively high expectations often need be used highly sophisticated devices such as ESEM.Even so, the damage that some electrostatic damage phenomenon also is difficult to cause with other reasons is distinguished, and people's mistake was lost efficacy electrostatic damage be used as other inefficacies.This usually owing to early failure or inefficacy in confused situation, thereby had covered the true cause that lost efficacy unconsciously before damage of electrostatic discharge is not fully realized.So static has complexity to the analysis of electronic device damage.
The pattern of static discharge phenomenon is divided into four kinds usually: HBM (human body discharge mode), MM (machine discharge mode), CDM (assembly charging and discharging pattern) and FIM (electric field induction pattern).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes circuit malfunction.Therefore, damaged by ESD, all will carry out effective ESD protection, the ESD electric current is released each pin of chip in order to prevent inside chip.
Under the normal operating conditions of integrated circuit, electrostatic discharge protector is to be in closing state, can not influence the current potential on the input and output pin; And externally static pours into integrated circuit and when producing moment high-tension, this device can be opened conducting, emits electrostatic induced current rapidly.
ESD static is because the time is short, and energy is big, often circuit is produced the impact of moment and causes each components from being damaged in the circuit, and this just requires the ESD safeguard structure that good current drain ability not only will be arranged, and for ESD static a kind of reaction speed is faster arranged.
The selection of circuit protecting element decides according to claimed wiring situation, available circuit board space and by the electrical characteristics of protective circuit.Because utilize in the IC circuit that the advanced technologies technology makes oxide layer thinner, grid oxic horizon is more vulnerable to infringement; And some adopt the deep submicron process and the complicated semiconductor functional circuits of fine linewidth wiring very, and to the influence of circuit transient process sensitivity more, this will cause the problems referred to above to increase the weight of.Therefore require the protection device must possess low clamping voltage so that effective esd protection to be provided; And the response time is enough short in to satisfy the requirement of High-Speed Data Line; Encapsulation integrated level height is to be suitable for the nervous situation of portable equipment printed circuit board area; Also to guarantee repeatedly simultaneously after the ESD process not can deterioration to guarantee the due quality of high end equipment.Transient Voltage Suppressor (TVS:Transient Voltage Suppressor) produces for addressing these problems just, and it has become the guardian technique device of protection electronic message unit.
But diode structure is to inject N+ formation PN junction on the P substrate or on the P extension mostly among traditional TVS, rely on the bigger big electric current of PN junction area carrying ESD, or injection P+ forms PN junction on N substrate or N extension; Present traditional TVS is mainly used in mobile phone, and in the portable electronic products such as MP3 and digital camera, these products are because data transmission bauds is slow, and therefore, less demanding to the parasitic capacitance of TVS generally allows in the scope of (30～100) pF; But the high-end digital product of present some basically all adopts like high-speed transfer interfaces such as USB2.0, USB3.0, HDMI; Like USB3.0; Message transmission rate reaches 600MBps; Therefore the parasitic capacitance to TVS requires high; Necessarily require to be lower than 3.5pF even lower; So the TVS of the big capacitance of tradition is applied to can influence in the high-speed transfer interface signal integrity of whole system, lose the performance of ESD protection, can not satisfy this high speed requirement.
Summary of the invention
To the above-mentioned technological deficiency of existing in prior technology, the invention provides a kind of two-way twin-channel Transient Voltage Suppressor, parasitic capacitance is low, satisfies the high speed requirement of coffret.
A kind of two-way twin-channel Transient Voltage Suppressor; Comprise the P+ substrate layer, from left to right be provided with first isolation channel, a N+ buried regions, second isolation channel, a P-epitaxial region, the 3rd isolation channel, the 2nd P-epitaxial region, the 4th isolation channel, the 3rd P-epitaxial region, the 5th isolation channel, the 2nd N+ buried regions, the 6th isolation channel on the described P+ substrate layer successively;
Be respectively equipped with a N injection region and the 2nd N injection region on a described N+ buried regions and the 2nd N+ buried regions;
Be respectively equipped with active injection region of a N+ and the active injection region of the 2nd N+ on a described P-epitaxial region and the 3rd P-epitaxial region;
Be respectively equipped with the active injection region of a P+, the active injection region of the 2nd P+ and the active injection region of the 3rd P+ on a described N injection region, the 2nd P-epitaxial region and the 2nd N injection region;
The active injection region of a described P+ links to each other through first metal electrode with the active injection region of a N+; The active injection region of described the 3rd P+ links to each other through second metal electrode with the active injection region of the 2nd N+; The active injection region of described the 2nd P+ links to each other with grounding electrode.
In the optimized technical scheme, the doping content of a described P-epitaxial region, the 2nd P-epitaxial region and the 3rd P-epitaxial region is (3 * 10
16～2 * 10
17) atom/cm
3, thickness is (3～4.5) um; Can suppress ghost effect effectively.
In the optimized technical scheme, the doping content of a described N injection region and the 2nd N injection region is (3 * 10
16～2 * 10
17) atom/cm
3Can suppress ghost effect effectively.
In the optimized technical scheme, the doping content of a described N+ buried regions and the 2nd N+ buried regions is (3 * 10
18～1 * 10
19) atom/cm
3, thickness is (1～1.5) um; Can suppress ghost effect effectively.
In the optimized technical scheme, the width of described first isolation channel, second isolation channel, the 3rd isolation channel, the 4th isolation channel, the 5th isolation channel and the 6th isolation channel is (1.5～2) um, and the degree of depth is (6～8) um; Can suppress ghost effect effectively.
In the optimized technical scheme, the width of active injection region of a described P+ and the active injection region of the 3rd P+ be respectively a described N+ buried regions and the 2nd N+ buried regions width (0.4～0.7) doubly; Can suppress ghost effect effectively.
The equivalent electric circuit of described Transient Voltage Suppressor is made up of four diodes and two Zener voltage-stabiliser tubes; Wherein, The negative electrode of first diode links to each other with the negative electrode of the first Zener voltage-stabiliser tube; The anode of first diode links to each other with the negative electrode of second diode and constitutes an end of described Transient Voltage Suppressor; The anode of second diode links to each other and ground connection with the anode of the first Zener voltage-stabiliser tube, the anode of the second Zener voltage-stabiliser tube and the anode of the 4th diode; The negative electrode of the 4th diode links to each other with the anode of the 3rd diode and constitutes the other end of described Transient Voltage Suppressor, and the negative electrode of the 3rd diode links to each other with the negative electrode of the second Zener voltage-stabiliser tube.
Described first diode is made up of an active injection region of a described P+ and a described N injection region; Described second diode is made up of a described P-epitaxial region and the active injection region of a described N+; Described the 3rd diode is made up of active injection region of described the 3rd P+ and described the 2nd N injection region; Described the 4th diode is made up of described the 3rd P-epitaxial region and the active injection region of described the 2nd N+; The described first Zener voltage-stabiliser tube is made up of a described P+ substrate layer and a described N+ buried regions; The described second Zener voltage-stabiliser tube is made up of described P+ substrate layer and described the 2nd N+ buried regions.
The protection voltage range of Transient Voltage Suppressor of the present invention can reach (1.2～5) V, and the clamp voltage scope is (7～12) V.
Useful technique effect of the present invention is:
(1) the present invention is through two-way twin-channel structural design; Make TVS have extremely short response time and quite high surge absorbability; When the high energy impact events of moment is stood at its two ends; TVS can become Low ESR to the resistance value between two ends by high impedance at a terrific speed; To absorb an instantaneous large-current; Thereby with its voltage strangulation on a predetermined numerical value, thereby the circuit element of protection back is not subjected to the impact of high voltage transient spike.
(2) the present invention is through adopting the combining structure and the deep trench isolation technology of Zener voltage-stabiliser tube and low di-cap; Further reduced the parasitic capacitance of TVS; Ghost effect is suppressed to minimum level; Simultaneously through adopting the low-resistance injection region; Further reduced conducting resistance; Improved the clamper characteristic of TVS, can be widely used on the electrostatic defending of some portable sets and high-speed interface.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 is an equivalent circuit diagram of the present invention.
Fig. 3 is a protection of the present invention path sketch map.
Fig. 4 is a manufacture craft schematic flow sheet of the present invention.
Embodiment
In order to describe the present invention more particularly, technical scheme of the present invention and relative theory thereof and manufacturing process are elaborated below in conjunction with accompanying drawing and embodiment.
As shown in Figure 1; A kind of two-way twin-channel Transient Voltage Suppressor; Comprise P+ substrate layer 10, from left to right be provided with first isolation channel 31, a N+ buried regions 11, second isolation channel 32, a P-epitaxial region 01, the 3rd isolation channel 33, the 2nd P-epitaxial region 02, the 4th isolation channel 34, the 3rd P-epitaxial region 03, the 5th isolation channel 35, the 2nd N+ buried regions 12, the 6th isolation channel 36 on the P+ substrate layer 10 successively;
Be respectively equipped with a N injection region 21 and the 2nd N injection region 22 on the one N+ buried regions 11 and the 2nd N+ buried regions 12;
Be respectively equipped with active injection region 51 of a N+ and the active injection region 52 of the 2nd N+ on the one P-epitaxial region 01 and the 3rd P-epitaxial region 03;
Be respectively equipped with the active injection region of a P+ 41, the active injection region 42 of the 2nd P+ and the active injection region 43 of the 3rd P+ on the one N injection region 21, the 2nd P-epitaxial region 02 and the 2nd N injection region 22;
The active injection region 41 of the one P+ links to each other through first metal electrode 61 with the active injection region 51 of a N+; The active injection region 43 of the 3rd P+ links to each other through second metal electrode 62 with the active injection region 52 of the 2nd N+; The active injection region 42 of the 2nd P+ links to each other with grounding electrode 60.
In this execution mode, the doping content of a P-epitaxial region 01, the 2nd P-epitaxial region 02 and the 3rd P-epitaxial region 03 is 8 * 10
16Atom/cm
3, thickness is 4um; The doping content of the one N injection region 21 and the 2nd N injection region 22 is 1 * 10
17Atom/cm
3The doping content of the one N+ buried regions 11 and the 2nd N+ buried regions 12 is 5 * 10
18Atom/cm
3, thickness is 1.2um; The width of first isolation channel 31, second isolation channel 32, the 3rd isolation channel 33, the 4th isolation channel 34, the 5th isolation channel 35 and the 6th isolation channel 36 is 1.8um, and the degree of depth is 7um; The width of active injection region 41 of the one P+ and the active injection region 43 of the 3rd P+ is respectively 0.5 times of width of a N+ buried regions 11 and the 2nd N+ buried regions 12.
As shown in Figure 2, the equivalent electric circuit of the Transient Voltage Suppressor of this execution mode is made up of four diodes and two Zener voltage-stabiliser tubes; Wherein, The negative electrode of the first diode D1 links to each other with the negative electrode of the first Zener voltage-stabiliser tube Q1; The anode of the first diode D1 links to each other with the negative electrode of the second diode D2 and constitutes an end I/O1 of Transient Voltage Suppressor; The anode of the anode of the second diode D2 and the first Zener voltage-stabiliser tube Q1; The anode of the second Zener voltage-stabiliser tube Q2 links to each other with the anode of the 4th diode D4 and ground connection GND; The negative electrode of the 4th diode D4 links to each other with the anode of the 3rd diode D3 and constitutes the other end I/O2 of Transient Voltage Suppressor, and the negative electrode of the 3rd diode D3 links to each other with the negative electrode of the second Zener voltage-stabiliser tube Q2.
The first diode D1 is made up of an active injection region 41 of a P+ and a N injection region 21; The second diode D2 is made up of a P-epitaxial region 01 and the active injection region 51 of a N+; The 3rd diode D3 is made up of active injection region 43 of the 3rd P+ and the 2nd N injection region 22; The 4th diode D4 is made up of the 3rd P-epitaxial region 03 and the active injection region 52 of the 2nd N+; The first Zener voltage-stabiliser tube Q1 is made up of a P+ substrate layer 10 and a N+ buried regions 11; The second Zener voltage-stabiliser tube Q2 is made up of P+ substrate layer 10 and the 2nd N+ buried regions 12.
As shown in Figure 3, the Transient Voltage Suppressor of this execution mode can be realized the protection (path 1) that passes through, and protection from arbitrary end to ground (path 2) and ground are to the protection (path 3) of arbitrary end.When ESD comes temporarily, be example with path 2, the ESD electric current flows into from the other end I/O2 of Transient Voltage Suppressor, at first flows through the 3rd diode D3, through the second Zener voltage-stabiliser tube Q2, flows to ground end GND; The voltage of final input/output terminal is clamped at V=V
D3+ V
Q2, wherein: V
D3The forward voltage drop of representing the 3rd diode D3 is about about 0.6～0.7V V
Q2The reverse breakdown voltage of representing the second Zener voltage-stabiliser tube Q2; Can obtain the magnitude of voltage of different application scope through the concentration of control P+ substrate layer and N+ buried regions, be controlled between 5～8V, therefore usually; The voltage of input/output terminal is clamped in the safe voltage scope, has played protective effect.
As shown in Figure 4, the manufacturing process of the Transient Voltage Suppressor of this execution mode is: at first utilize step such as deposit etching about on the P+ substrate, to form two N+ buried regions, see Fig. 4 (a); Growth layer of even P-epitaxial loayer on the P+ substrate of N+ buried regions of having grown is seen Fig. 4 (b) then; The etching deep trouth is isolated in the P-epitaxial loayer, and the P-epitaxial loayer is separated into five P-epitaxial regions, fills polysilicon or silicon dioxide in the groove, sees Fig. 4 (c); Mode that utilize to inject diffusion about form the N injection region of low impedance path on two P-epitaxial regions, see Fig. 4 (d); On P-epitaxial region and N injection region, form corresponding P+ injection region and N+ injection region at last, interconnected accordingly through the metal electrode realization, see Fig. 4 (e).
Utilize device simulation software Medici and process simulation software Tsuprem4 that the TVS of traditional TVS and this execution mode is carried out comprehensive verification respectively relatively; And the parasitic capacitance of analyzing two kinds of TVS structures is big or small; Simulation result draws: the parasitic capacitance size of traditional TVS is 56.44pF; And the parasitic capacitance of this execution mode TVS size is 3.24pF; So the TVS of this execution mode has reduced the parasitic capacitance of device effectively, satisfies the high speed requirement of coffret.
Claims (6)
1. two-way twin-channel Transient Voltage Suppressor; It is characterized in that: comprise the P+ substrate layer, from left to right be provided with first isolation channel, a N+ buried regions, second isolation channel, a P-epitaxial region, the 3rd isolation channel, the 2nd P-epitaxial region, the 4th isolation channel, the 3rd P-epitaxial region, the 5th isolation channel, the 2nd N+ buried regions, the 6th isolation channel on the described P+ substrate layer successively;
Be respectively equipped with a N injection region and the 2nd N injection region on a described N+ buried regions and the 2nd N+ buried regions;
Be respectively equipped with active injection region of a N+ and the active injection region of the 2nd N+ on a described P-epitaxial region and the 3rd P-epitaxial region;
Be respectively equipped with the active injection region of a P+, the active injection region of the 2nd P+ and the active injection region of the 3rd P+ on a described N injection region, the 2nd P-epitaxial region and the 2nd N injection region;
The active injection region of a described P+ links to each other through first metal electrode with the active injection region of a N+; The active injection region of described the 3rd P+ links to each other through second metal electrode with the active injection region of the 2nd N+; The active injection region of described the 2nd P+ links to each other with grounding electrode.
2. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the doping content of a described P-epitaxial region, the 2nd P-epitaxial region and the 3rd P-epitaxial region is 3 * 10
16～2 * 10
17Atom/cm
3, thickness is 3～4.5um.
3. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the doping content of a described N injection region and the 2nd N injection region is 3 * 10
16～2 * 10
17Atom/cm
3
4. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the doping content of a described N+ buried regions and the 2nd N+ buried regions is 3 * 10
18～1 * 10
19Atom/cm
3, thickness is 1～1.5um.
5. two-way twin-channel Transient Voltage Suppressor according to claim 1; It is characterized in that: the width of described first isolation channel, second isolation channel, the 3rd isolation channel, the 4th isolation channel, the 5th isolation channel and the 6th isolation channel is 1.5～2um, and the degree of depth is 6～8um.
6. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the width of active injection region of a described P+ and the active injection region of the 3rd P+ is respectively 0.4～0.7 times of width of a described N+ buried regions and the 2nd N+ buried regions.
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| CN102593155A (en) * | 2012-03-01 | 2012-07-18 | 浙江大学 | Multi-porous channel current equalizing-based transient voltage suppressor |
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| CN102593155A (en) * | 2012-03-01 | 2012-07-18 | 浙江大学 | Multi-porous channel current equalizing-based transient voltage suppressor |
| CN102593155B (en) * | 2012-03-01 | 2014-03-12 | 浙江大学 | Multi-porous channel current equalizing-based transient voltage suppressor |
| CN103377916A (en) * | 2012-04-19 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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Application publication date: 20120104 |