CN102306649A - Bidirectional dual-channel transient voltage suppressor (TVS) - Google Patents

Abstract

The invention discloses a bidirectional double-channel transient voltage suppressor, which comprises a P+ substrate layer, on which a first N+ buried layer, a first P-extaxial region, and a second P-extaxial region are sequentially arranged from left to right. region, the third P- epitaxial region, the second N+ buried layer; the first N+ buried layer and the second N+ buried layer are respectively provided with a first N implanted region and a second N implanted region; the first P- epitaxial region and the second N+ buried layer The first N+ active injection region and the second N+ active injection region are respectively arranged on the three P- epitaxial regions; the first P+ Active injection region, second P+ active injection region and third P+ active injection region. The present invention further reduces the parasitic capacitance of the TVS by adopting the combination structure of the Zener voltage regulator tube and the low-capacitance diode, reduces the on-resistance, improves the clamping characteristic of the TVS, and can be widely used in some portable devices and high-speed interfaces on the electrostatic protection.

Description

A Bidirectional Dual Channel Transient Voltage Suppressor

technical field

The invention belongs to the technical field of electrostatic protection for integrated circuits, and in particular relates to a bidirectional and dual-channel transient voltage suppressor.

Background technique

With the rapid development of electronic information technology, the current semiconductor devices tend to be miniaturized, high-density and multi-functional, especially for applications such as fashion consumer electronics and portable products that have strict requirements on the motherboard area, they are vulnerable to electrostatic discharge (ESD) )Impact. Static electricity exists all the time and everywhere. In the 1960s, with the emergence of MOS devices that are very sensitive to static electricity, the problem of static electricity also appeared. In the 1970s, the problem of static electricity became more and more serious. The density of the circuit is getting bigger and bigger. On the one hand, the thickness of the silicon dioxide film is getting thinner (micron to nanometer), and the electrostatic voltage it bears is getting lower and lower; on the other hand, materials that generate and accumulate static electricity such as plastics The extensive use of rubber, etc. makes static electricity more and more common. The US electronics industry alone loses tens of billions of dollars due to static electricity every year. Therefore, static electricity damage has become an invisible killer of the electronics industry and a common "hard virus" in the electronics industry. ", it will happen when the internal and external conditions are met at a certain time.

Static damage has concealment, potentiality, randomness and complexity. The human body cannot directly perceive static electricity unless electrostatic discharge occurs, but the human body may not feel an electric shock when electrostatic discharge occurs. This is because the electrostatic discharge voltage perceived by the human body is 2 to 3V, so static electricity is concealed; There is no obvious decline in performance after damage, but multiple cumulative discharges will cause internal damage to the device and form a hidden danger. Therefore, static electricity has potential damage to devices; from the time a component is generated until it is damaged, all processes are threatened by static electricity, and the generation of these static electricity is also random, and its damage is also random; electrostatic discharge The failure analysis of damage is time-consuming, time-consuming, and expensive due to the fine, fine, and tiny structural characteristics of electronic products. Higher technology often requires the use of high-precision instruments such as scanning electron microscopes. Even so, some electrostatic damage phenomena are difficult to distinguish from damage caused by other reasons, which makes people mistake electrostatic damage failures for other failures. Before the electrostatic discharge damage is fully understood, it is often attributed to early failure or unknown failure, thus unconsciously covering up the real cause of failure. Therefore, the analysis of electrostatic damage to electronic devices is complex.

The modes of electrostatic discharge phenomenon are usually divided into four types: HBM (Human Body Discharge Model), MM (Machine Discharge Mode), CDM (Component Charge Discharge Mode) and FIM (Field Induction Mode). The two most common electrostatic discharge modes that industrial products must pass are HBM and MM. When an electrostatic discharge occurs, the charge usually flows in from one pin of the chip and flows out from the other pin. At this time, the current generated by the electrostatic charge is usually as high as several amperes, and the voltage generated at the charge input pin is as high as several volts or even Dozens of volts. If a large ESD current flows into the internal chip, it will cause damage to the internal chip. At the same time, the high voltage generated at the input pin will also cause gate oxide breakdown of the internal device, resulting in circuit failure. Therefore, in order to prevent the internal chip from being damaged by ESD, each pin of the chip must be effectively protected against ESD to discharge the ESD current.

In the normal working state of the integrated circuit, the electrostatic discharge protection device is in the off state and will not affect the potential on the input and output pins; when the external static electricity is poured into the integrated circuit to generate a momentary high voltage, the device will Turn on the conduction, and quickly discharge the electrostatic current.

Because of the short time and high energy of ESD static electricity, it often has an instantaneous impact on the circuit and causes damage to various devices in the circuit. This requires the ESD protection structure not only to have a good current discharge capability, but also to have a faster ESD static electricity. reaction speed.

The choice of circuit protection components is based on the wiring to be protected, the available board space, and the electrical characteristics of the circuit being protected. Because the oxide layer in the IC circuit manufactured by advanced technology is relatively thin, the gate oxide layer is more susceptible to damage; and some complex semiconductor functional circuits using deep submicron technology and very fine line width wiring have a greater impact on the transient process of the circuit Sensitive, which will exacerbate the above problems. Therefore, it is required that the protection device must have a low clamping voltage to provide effective ESD protection; and the response time is short enough to meet the requirements of high-speed data lines; the package integration is high to apply to the tight area of the printed circuit board of portable devices; Ensure that it will not deteriorate after multiple ESD processes to ensure the quality that high-end equipment should have. Transient Voltage Suppressor (TVS: Transient Voltage Suppressor) was created to solve these problems, and it has become a key technical device for protecting electronic information equipment.

However, most of the diode structures in traditional TVS are implanted with N+ on the P substrate or on the P epitaxy to form a PN junction, relying on a large PN junction area to carry the large ESD current, or injecting P+ on the N substrate or N epitaxy to form a PN junction. Conclusion; At present, traditional TVS is mainly used in portable electronic products such as mobile phones, MP3 and digital cameras. Due to the slow data transmission speed of these products, the requirements for the parasitic capacitance of TVS are not high, and generally allow (30 ~ 100)pF However, some of the current high-end digital products basically use high-speed transmission interfaces such as USB2.0, USB3.0, HDMI, etc., such as USB3.0, and the data transmission rate reaches 600MBps, so the parasitic capacitance of TVS is extremely demanding. It must be lower than 3.5pF or even lower, so the traditional TVS with large capacitance value applied to the high-speed transmission interface will affect the signal integrity of the entire system, lose the performance of ESD protection, and can no longer meet this high-speed requirement.

Contents of the invention

Aiming at the above-mentioned technical defects in the prior art, the present invention provides a bidirectional and dual-channel transient voltage suppressor, which has low parasitic capacitance and meets the high-speed requirements of the transmission interface.

A bidirectional dual-channel transient voltage suppressor, comprising a P+ substrate layer, the P+ substrate layer is provided with a first isolation groove, a first N+ buried layer, a second isolation groove, a first P+ substrate layer in sequence from left to right - epitaxial region, third isolation trench, second P-epitaxial region, fourth isolation trench, third P-epitaxial region, fifth isolation trench, second N+ buried layer, sixth isolation trench;

The first N+ buried layer and the second N+ buried layer are respectively provided with a first N injection region and a second N injection region;

A first N+ active injection region and a second N+ active injection region are respectively provided on the first P- epitaxial region and the third P- epitaxial region;

A first P+ active implant region, a second P+ active implant region and a third P+ active implant region are respectively arranged on the first N implant region, the second P- epitaxial region and the second N implant region;

The first P+ active injection region is connected to the first N+ active injection region through a first metal electrode; the third P+ active injection region is connected to the second N+ active injection region through a second metal electrode; The second P+ active injection region is connected to the ground electrode.

In a preferred technical solution, the doping concentration of the first P-epitaxial region, the second P-epitaxial region and the third P-epitaxial region is (3×10 ¹⁶ -2×10 ¹⁷ ) atom/cm ³ , The thickness is (3-4.5) um; it can effectively suppress the parasitic effect.

In a preferred technical solution, the doping concentration of the first N implantation region and the second N implantation region is (3×10 ¹⁶ -2×10 ¹⁷ ) atom/cm ³ ; parasitic effects can be effectively suppressed.

In a preferred technical solution, the doping concentration of the first N+ buried layer and the second N+ buried layer is (3×10 ¹⁸ -1×10 ¹⁹ ) atom/cm ³ , and the thickness is (1-1.5) um; Can effectively suppress parasitic effects.

In a preferred technical solution, the width of the first isolation groove, the second isolation groove, the third isolation groove, the fourth isolation groove, the fifth isolation groove and the sixth isolation groove is (1.5-2) um, and the depth is (6~8)um; can effectively suppress parasitic effects.

In a preferred technical solution, the widths of the first P+ active injection region and the third P+ active injection region are respectively (0.4-0.7) of the widths of the first N+ buried layer and the second N+ buried layer times; can effectively suppress parasitic effects.

The equivalent circuit of the transient voltage suppressor is composed of four diodes and two zener voltage regulators; wherein, the cathode of the first diode is connected with the cathode of the first zener voltage regulator, and the first two The anode of the pole tube is connected with the cathode of the second diode and constitutes one end of the transient voltage suppressor, the anode of the second diode is connected with the anode of the first Zener voltage regulator, the second Zener voltage regulator The anode of the tube is connected to the anode of the fourth diode and grounded, the cathode of the fourth diode is connected to the anode of the third diode and constitutes the other end of the transient voltage suppressor, and the third diode The cathode of the second Zener voltage regulator is connected to the cathode.

The first diode is composed of the first P+ active injection region and the first N injection region; the second diode is composed of the first P- epitaxial region and the first N injection region. The first N+ active injection region is formed; the third diode is formed by the third P+ active injection region and the second N injection region; the fourth diode is formed by The third P- epitaxial region and the second N+ active implant region; the first Zener voltage regulator is composed of the P+ substrate layer and the first N+ buried layer; The second Zener voltage regulator is composed of the P+ substrate layer and the second N+ buried layer.

The protection voltage range of the transient voltage suppressor of the invention can reach (1.2-5) V, and the clamping voltage range is (7-12) V.

The beneficial technical effect of the present invention is:

(1) The present invention makes the TVS have a very short response time and a relatively high surge absorption capacity through the structural design of two-way and two channels. The impedance value between the two ends changes from high impedance to low impedance to absorb an instantaneous large current, thereby clamping the voltage at both ends to a predetermined value, so as to protect the subsequent circuit components from the impact of transient high-voltage spikes .

(2) The present invention further reduces the parasitic capacitance of the TVS by adopting the combined structure of Zener voltage regulator tube and low-capacitance diode and the deep trench isolation technology, and suppresses the parasitic effect to a minimum degree, and at the same time, by adopting the low-resistance injection region, further The on-resistance is reduced, the clamping characteristic of TVS is improved, and it can be widely used in the electrostatic protection of some portable devices and high-speed interfaces.

Description of drawings

Fig. 1 is a structural schematic diagram of the present invention.

Fig. 2 is an equivalent circuit diagram of the present invention.

Fig. 3 is a schematic diagram of the protection path of the present invention.

Fig. 4 is a schematic diagram of the manufacturing process of the present invention.

Detailed ways

In order to describe the present invention more specifically, the technical solution of the present invention and its related principles and manufacturing process will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 1, a bidirectional dual-channel transient voltage suppressor includes a P+ substrate layer 10, on which a first isolation groove 31, a first N+ buried layer 11, a first N+ buried layer 11, and Two isolation grooves 32, the first P-epitaxy region 01, the third isolation groove 33, the second P-epitaxy region 02, the fourth isolation groove 34, the third P-epitaxy region 03, the fifth isolation groove 35, the second N+ Buried layer 12, sixth isolation trench 36;

The first N+ buried layer 11 and the second N+ buried layer 12 are respectively provided with a first N implanted region 21 and a second N implanted region 22;

A first N+ active injection region 51 and a second N+ active injection region 52 are provided on the first P- epitaxial region 01 and the third P-epitaxial region 03 respectively;

A first P+ active implant region 41, a second P+ active implant region 42 and a third P+ active implant region are respectively provided on the first N implant region 21, the second P- epitaxial region O2 and the second N implant region 22. 43;

The first P+ active injection region 41 and the first N+ active injection region 51 are connected through the first metal electrode 61; the third P+ active injection region 43 and the second N+ active injection region 52 are connected through the second metal electrode 62; The second P+ active injection region 42 is connected to the ground electrode 60 .

In this embodiment, the doping concentration of the first P-epitaxial region 01, the second P-epitaxial region 02 and the third P-epitaxial region 03 is 8×10 ¹⁶ atom/cm ³ , and the thickness is 4um; the first N implantation The doping concentration of the region 21 and the second N implanted region 22 is 1×10 ¹⁷ atom/cm ³ ; the doping concentration of the first N+ buried layer 11 and the second N+ buried layer 12 is 5×10 ¹⁸ atom/cm ³ , The thickness is 1.2um; the width of the first isolation groove 31, the second isolation groove 32, the third isolation groove 33, the fourth isolation groove 34, the fifth isolation groove 35 and the sixth isolation groove 36 is 1.8um, and the depth is 7um; The widths of the first P+ active injection region 41 and the third P+ active injection region 43 are 0.5 times the widths of the first N+ buried layer 11 and the second N+ buried layer 12 respectively.

As shown in Figure 2, the equivalent circuit of the transient voltage suppressor of the present embodiment is composed of four diodes and two Zener voltage regulators; wherein, the cathode of the first diode D1 is connected to the first Zener voltage regulator The cathode of the tube Q1 is connected, the anode of the first diode D1 is connected to the cathode of the second diode D2 and constitutes one end I/O1 of the transient voltage suppressor, the anode of the second diode D2 is connected to the first Zener The anode of the voltage regulator Q1, the anode of the second Zener voltage regulator Q2 and the anode of the fourth diode D4 are connected to the ground GND, and the cathode of the fourth diode D4 is connected to the anode of the third diode D3 and connected to the ground. The other terminal I/O2 of the transient voltage suppressor is formed, and the cathode of the third diode D3 is connected with the cathode of the second Zener voltage regulator Q2.

The first diode D1 is composed of the first P+ active injection region 41 and the first N injection region 21; the second diode D2 is composed of the first P- epitaxial region 01 and the first N+ active injection region 51; The third diode D3 is composed of the third P+ active injection region 43 and the second N injection region 22; the fourth diode D4 is composed of the third P- epitaxial region 03 and the second N+ active injection region 52; the first The Zener voltage regulator Q1 is composed of a P+ substrate layer 10 and a first N+ buried layer 11 ; the second Zener voltage regulator Q2 is composed of a P+ substrate layer 10 and a second N+ buried layer 12 .

As shown in Figure 3, the transient voltage suppressor of this embodiment can realize protection from one end to the other end (path 1), protection from any end to ground (path 2) and protection from ground to any end (path 3). ). When ESD comes, taking path 2 as an example, the ESD current flows in from the other end of the transient voltage suppressor I/O2, first flows through the third diode D3, passes through the second Zener voltage regulator Q2, and flows to the ground end GND; the voltage at the final input and output terminals is clamped at V=V _D3 +V _Q2 , where: V _D3 represents the forward voltage drop of the third diode D3, which is about 0.6~0.7V, and V _Q2 represents the second diode D3 The reverse breakdown voltage of the nano-zener transistor Q2 can obtain voltage values in different application ranges by controlling the concentration of the P+ substrate layer and the N+ buried layer, usually controlled between 5 and 8V. Therefore, the voltage at the input and output terminals is clamped at Within the safe voltage range, it plays a protective role.

As shown in Figure 4, the manufacturing process of the transient voltage suppressor in this embodiment is as follows: first, two N+ buried layers are formed on the left and right sides of the P+ substrate by steps such as deposition and etching, as shown in Figure 4(a); A uniform P- epitaxial layer is grown on the P+ substrate with the N+ buried layer, as shown in Figure 4(b); deep grooves are etched in the P- epitaxial layer for isolation, and the P-epitaxial layer is divided into five P -The epitaxial region, the groove is filled with polysilicon or silicon dioxide, as shown in Figure 4(c); the N implanted region of the low-resistance channel is formed on the left and right P-epitaxial regions by means of implantation and diffusion, as shown in Figure 4(d); Finally, corresponding P+ implantation regions and N+ implantation regions are formed on the P- epitaxial region and N implantation region, and the corresponding interconnections are realized through metal electrodes, as shown in FIG. 4( e ).

Using the device simulation software Medici and the process simulation software Tsuprem4, the traditional TVS and the TVS of this embodiment are respectively comprehensively verified and compared, and the parasitic capacitance of the two TVS structures are analyzed. The simulation results show that the parasitic capacitance of the traditional TVS is 56.44pF , and the parasitic capacitance of the TVS in this embodiment is 3.24pF, so the TVS in this embodiment effectively reduces the parasitic capacitance of the device and meets the high-speed requirements of the transmission interface.

Claims (6)

1. two-way twin-channel Transient Voltage Suppressor; It is characterized in that: comprise the P+ substrate layer, from left to right be provided with first isolation channel, a N+ buried regions, second isolation channel, a P-epitaxial region, the 3rd isolation channel, the 2nd P-epitaxial region, the 4th isolation channel, the 3rd P-epitaxial region, the 5th isolation channel, the 2nd N+ buried regions, the 6th isolation channel on the described P+ substrate layer successively;

Be respectively equipped with a N injection region and the 2nd N injection region on a described N+ buried regions and the 2nd N+ buried regions;

Be respectively equipped with active injection region of a N+ and the active injection region of the 2nd N+ on a described P-epitaxial region and the 3rd P-epitaxial region;

Be respectively equipped with the active injection region of a P+, the active injection region of the 2nd P+ and the active injection region of the 3rd P+ on a described N injection region, the 2nd P-epitaxial region and the 2nd N injection region;

The active injection region of a described P+ links to each other through first metal electrode with the active injection region of a N+; The active injection region of described the 3rd P+ links to each other through second metal electrode with the active injection region of the 2nd N+; The active injection region of described the 2nd P+ links to each other with grounding electrode.

2. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the doping content of a described P-epitaxial region, the 2nd P-epitaxial region and the 3rd P-epitaxial region is 3 * 10 ¹⁶～2 * 10 ¹⁷Atom/cm ³, thickness is 3～4.5um.

3. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the doping content of a described N injection region and the 2nd N injection region is 3 * 10 ¹⁶～2 * 10 ¹⁷Atom/cm ³

4. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the doping content of a described N+ buried regions and the 2nd N+ buried regions is 3 * 10 ¹⁸～1 * 10 ¹⁹Atom/cm ³, thickness is 1～1.5um.

5. two-way twin-channel Transient Voltage Suppressor according to claim 1; It is characterized in that: the width of described first isolation channel, second isolation channel, the 3rd isolation channel, the 4th isolation channel, the 5th isolation channel and the 6th isolation channel is 1.5～2um, and the degree of depth is 6～8um.

6. two-way twin-channel Transient Voltage Suppressor according to claim 1 is characterized in that: the width of active injection region of a described P+ and the active injection region of the 3rd P+ is respectively 0.4～0.7 times of width of a described N+ buried regions and the 2nd N+ buried regions.

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