CN106298972B - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN106298972B CN106298972B CN201510306834.XA CN201510306834A CN106298972B CN 106298972 B CN106298972 B CN 106298972B CN 201510306834 A CN201510306834 A CN 201510306834A CN 106298972 B CN106298972 B CN 106298972B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 3
- 239000000243 solution Substances 0.000 description 17
- 230000008569 process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000001052 transient effect Effects 0.000 description 7
- 230000002457 bidirectional effect Effects 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of semiconductor device and its manufacturing method, method includes: that multiple grooves are etched in the silicon chip substrate of growth of doping silicon layer；Thermal oxide is carried out to the silicon wafer for forming the multiple groove, fills silica in each groove, and prepare doped region；In the grown above silicon dielectric layer for forming the doped region；Multiple metal apertures are prepared on the dielectric layer, and grow metal layer on the lower surface of the silicon chip substrate；The multiple metal aperture is divided into two parts, respectively as the first input/output end port and the second input/output end port, using the metal layer as third input/output end port.According to the technical solution of the present invention, the manufacturing cost of packet routing device can be reduced while improving packet routing device performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture of semiconductor device
Method and a kind of semiconductor device.
Background technique
Transient Voltage Suppressor (TVS) is a kind of for protecting sensitive semiconductor device, makes it from transient voltage surge
It destroys and specially designed solid-state semiconductor device, it has, and clamp coefficient is small, small in size, response is fast, leakage current is small and reliable
The advantages that property is high, thus be widely used on voltage transient and carrying out surge protection.Low-capacitance TVS is suitable for high-frequency circuit
Protection device reduce the decaying of high-frequency circuit signal because it can reduce interference of the parasitic capacitance to circuit.Low capacitor two
Pole pipe needs grow high resistivity on highly dope p-type substrate.
The transient voltage that static discharge (ESD) and some other voltage surge form occur at random is typically found in each
In kind electronic device.As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device be increasingly easy by
To the influence of voltage surge, fatal harm is even resulted in.Various voltage surges can induce wink from static discharge to lightning etc.
State current spike, impact of the Transient Voltage Suppressor (TVS) commonly used to protection sensitive circuit by surge.It is answered based on different
With Transient Voltage Suppressor can play the role of circuit protection by changing the clamping voltag of surge discharge path and itself.
In order to save chip area, and higher Surge handling capability is obtained, the concept of groove TVS has been suggested and studied.Groove
The junction of TVS is formed in the side wall of longitudinal groove, in this way, it has more effective junction areas under identical chip area,
I.e. stronger discharge capability.The small package size of groove TVS is very crucial to the high-end IC of protection is applied to.
The structural schematic diagram of currently used groove TVS includes P-type wafer 102, N-type diffusion/injection region as shown in Figure 1:
Domain 104, polysilicon/metal 106.
Currently used groove TVS can only realize unidirectional protection, need to go here and there multiple TVS if necessary to carry out bidirectional protective
Join or be connected in parallel, increases device area and manufacturing cost.
Therefore, the manufacturing cost that device how is reduced while improving device performance, becomes urgently to be resolved at present and asks
Topic.
Summary of the invention
The present invention is based on the above problems, proposes a kind of new technical solution, is improving packet routing device
The manufacturing cost of packet routing device is reduced while performance.
In view of this, the invention proposes a kind of manufacturing methods of semiconductor device, comprising: mixed in growth
Multiple grooves are etched in the silicon chip substrate of miscellaneous silicon layer；Thermal oxide is carried out to the silicon wafer for forming the multiple groove, each described
Silica is filled in groove, and prepares doped region；In the grown above silicon dielectric layer for forming the doped region；It is being given an account of
Multiple metal apertures are prepared on matter layer, and grow metal layer on the lower surface of the silicon chip substrate；By the multiple metal aperture etc.
It is divided into two parts, respectively as the first input/output end port and the second input/output end port, using the metal layer as third
Input/output end port.
In the technical scheme, on the basis of conventional groove packet routing device, two winks was made by process modification
State voltage suppressor device is integrated together, and device area is small, and technology difficulty is low, reduces device manufacturing cost.Improved wink
State voltage suppressor device is able to achieve two-path bidirectional defencive function, and the protection feature and reliability of device are all improved.
In the above-mentioned technical solutions, it is preferable that described that multiple grooves, packet are etched in the silicon chip substrate of growth of doping silicon layer
It includes: the growth of doping silicon layer on the upper surface of silicon chip substrate；Mask material is grown on the doped silicon layer, to form exposure mask figure
Shape；The silicon wafer for forming mask pattern is performed etching, to form multiple grooves.
In the above-mentioned technical solutions, it is preferable that described that multiple metal apertures are prepared on the dielectric layer, comprising: described
Mask material is grown on dielectric layer, and multiple medium holes are formed with etching；Each medium holes are filled using metal material, with
To the multiple metal aperture.
In the above-mentioned technical solutions, it is preferable that prepare to form the doping using the mode of ion diffusion or ion implanting
Region.
In the above-mentioned technical solutions, it is preferable that the silicon chip substrate is P-type wafer substrate, and the doped silicon layer is mixed for N-type
Miscellaneous silicon layer.
In the above-mentioned technical solutions, it is preferable that the mask material includes photoresist.
In the above-mentioned technical solutions, it is preferable that the bottom of the groove is located in the range of the silicon chip substrate.
In the above-mentioned technical solutions, it is preferable that the ion is P-type ion.
In the above-mentioned technical solutions, it is preferable that when etching forms the groove, lithographic method includes dry etching.
In the technical scheme, dry etching includes brilliant hair, gaseous corrosion, plasma etching etc., and dry etching
Easily realize that automation, treatment process are not introduced into pollution, cleannes height.
In the above-mentioned technical solutions, it is preferable that when etching forms the medium holes, lithographic method includes dry etching.
In the technical scheme, dry etching includes brilliant hair, gaseous corrosion, plasma etching etc., and dry etching
Easily realize that automation, treatment process are not introduced into pollution, cleannes height.
According to another aspect of the present invention, a kind of semiconductor device, the two-way transient state electricity are additionally provided
Press suppression device as the semiconductor device as described in any one of above-mentioned technical proposal manufacturing method make and
At.
By above technical scheme, packet routing device is reduced while improving packet routing device performance
Manufacturing cost.
Detailed description of the invention
Fig. 1 shows the structural schematic diagram of groove-shaped packet routing device in the related technology；
Fig. 2 shows the processes of the manufacturing method of semiconductor device according to an embodiment of the invention
Schematic diagram；
Fig. 3 shows the equivalent circuit diagram of the semiconductor device of embodiment according to the present invention；
Fig. 4 to Figure 10 shows semiconductor device according to an embodiment of the invention in manufacturing process
In structural schematic diagram.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
To be implemented using other than the one described here other modes, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 2 shows the processes of the manufacturing method of semiconductor device according to an embodiment of the invention
Schematic diagram.
As shown in Fig. 2, the manufacturing method of the semiconductor device of the embodiment of the present invention, comprising: step
202, one doped silicon layer of growth regulation on the upper surface of silicon chip substrate；Step 204, exposure mask material is grown on the doped silicon layer
Material, to form mask pattern；Step 206, the silicon wafer for forming mask pattern is performed etching, to form multiple grooves；Step
208, thermal oxide is carried out to the silicon wafer for forming the multiple groove, and silica is filled in each groove, removal filling
The silica of silicon chip surface after silica；Step 210, doped region is formed using the mode of ion diffusion or ion implanting；
Step 212, in the grown above silicon dielectric layer for forming the doped region；Step 214, exposure mask material is grown on the dielectric layer
Material forms multiple medium holes with etching；Step 216, each medium holes are filled using metal material, to obtain multiple metals
Hole, and metal layer is grown on the lower surface of the silicon chip substrate；Step 218, the multiple metal aperture is divided into two parts,
Respectively as the first input/output end port and the second input/output end port, using the metal layer as third input/output terminal
Mouthful.
In the technical scheme, on the basis of conventional groove packet routing device, two winks was made by process modification
State voltage suppressor device is integrated together, and device area is small, and technology difficulty is low, reduces device manufacturing cost.Improved wink
State voltage suppressor device is able to achieve two-path bidirectional defencive function, and the protection feature and reliability of device are all improved.
In the above-mentioned technical solutions, it is preferable that the silicon chip substrate is P-type wafer substrate, and the doped silicon layer is mixed for N-type
Miscellaneous silicon layer.
In the above-mentioned technical solutions, it is preferable that the mask material includes photoresist.
In the above-mentioned technical solutions, it is preferable that the bottom of the groove is located in the range of the silicon chip substrate.
In the above-mentioned technical solutions, it is preferable that the ion is P-type ion.
In the above-mentioned technical solutions, it is preferable that when etching forms the groove, lithographic method includes dry etching.
In the technical scheme, dry etching includes brilliant hair, gaseous corrosion, plasma etching etc., and dry etching
Easily realize that automation, treatment process are not introduced into pollution, cleannes height.
In the above-mentioned technical solutions, it is preferable that when etching forms the medium holes, lithographic method includes dry etching.
In the technical scheme, dry etching includes brilliant hair, gaseous corrosion, plasma etching etc., and dry etching
Easily realize that automation, treatment process are not introduced into pollution, cleannes height.
Fig. 3 shows the equivalent circuit diagram of the semiconductor device of embodiment according to the present invention.
As shown in figure 3, the semiconductor device of embodiment according to the present invention makes five by process modification
Packet routing device is integrated together, and device area is small, and technology difficulty is low, reduces device manufacturing cost.It is improved
Packet routing device is able to achieve bidirectional protective function, and the protection feature and reliability of device are all improved.
The manufacturing method of semiconductor device, specifically includes:
As shown in figure 4, extension, diffusion or injection side can be used in 402 front preparation n-type doping silicon 404 of P-type wafer
Formula is formed.
As shown in figure 5, using photoresist as exposure mask, dry etching forms groove.
Groove is filled using silica 408 as shown in fig. 6, carrying out thermal oxide, the silica on etching removal surface retains ditch
Silica in slot.
As shown in fig. 7, forming P-doped zone domain 406 using diffusion or injection mode.
As shown in figure 8, preparation media material 410.
As shown in figure 9, using photoresist as exposure mask, medium holes are formed on surface, fill metal.It is prepared in silicon chip back side
Metal layer 412.
The line schematic diagram for ultimately forming device is as shown in Figure 10.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, according to the technical solution of the present invention, in traditional ditch
On the basis of slot packet routing device, it is integrated together five packet routing devices by process modification, device side
Product is small, and technology difficulty is low, reduces device manufacturing cost.Improved packet routing device is able to achieve two-path bidirectional protection
Function, the protection feature and reliability of device are all improved.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of manufacturing method of semiconductor device characterized by comprising
Multiple grooves are etched in the silicon chip substrate of growth of doping silicon layer；
Thermal oxide is carried out to the silicon wafer for forming the multiple groove, fills silica in each groove, and prepare doping
Region；
In the grown above silicon dielectric layer for forming the doped region；
Multiple metal apertures are prepared on the dielectric layer, and grow metal layer on the lower surface of the silicon chip substrate；
The multiple metal aperture is divided into two parts, respectively as the first input/output end port and the second input/output terminal
Mouthful, using the metal layer as third input/output end port；
It is described that multiple metal apertures are prepared on the dielectric layer, comprising:
Mask material is grown on the dielectric layer, multiple medium holes are formed with etching；
Each medium holes are filled using metal material, to obtain the multiple metal aperture.
2. the manufacturing method of semiconductor device according to claim 1, which is characterized in that described to grow
Multiple grooves are etched in the silicon chip substrate of doped silicon layer, comprising:
The growth of doping silicon layer on the upper surface of silicon chip substrate；
Mask material is grown on the doped silicon layer, to form mask pattern；
The silicon wafer for forming mask pattern is performed etching, to form multiple grooves.
3. the manufacturing method of semiconductor device according to claim 1, which is characterized in that
It prepares to form the doped region using the mode of ion diffusion or ion implanting.
4. the manufacturing method of semiconductor device according to claim 1, which is characterized in that the silicon wafer lining
Bottom is P-type wafer substrate, and the doped silicon layer is n-type doping silicon layer.
5. the manufacturing method of semiconductor device according to claim 1, which is characterized in that the exposure mask material
Material includes photoresist.
6. the manufacturing method of semiconductor device according to claim 1, which is characterized in that the groove
Bottom is located in the range of the silicon chip substrate.
7. the manufacturing method of semiconductor device according to claim 3, which is characterized in that the ion is
P-type ion.
8. the manufacturing method of semiconductor device according to claim 1, which is characterized in that formed in etching
When the groove, lithographic method includes dry etching, and
When etching forms the medium holes, lithographic method includes dry etching.
9. a kind of semiconductor device, which is characterized in that the semiconductor device is wanted by such as right
The manufacturing method of semiconductor device described in asking any one of 1 to 8 is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510306834.XA CN106298972B (en) | 2015-06-05 | 2015-06-05 | Semiconductor device and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510306834.XA CN106298972B (en) | 2015-06-05 | 2015-06-05 | Semiconductor device and its manufacturing method |
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| CN106298972A CN106298972A (en) | 2017-01-04 |
| CN106298972B true CN106298972B (en) | 2019-11-08 |
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| CN109950326B (en) * | 2019-04-15 | 2024-05-17 | 马鞍山市槟城电子有限公司 | Bidirectional diode, manufacturing method thereof and overvoltage protection device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| CN103840013A (en) * | 2014-01-26 | 2014-06-04 | 上海韦尔半导体股份有限公司 | Bidirectional TVS and manufacturing method of bidirectional TVS |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8835977B2 (en) * | 2012-12-19 | 2014-09-16 | Alpha And Omega Semiconductor Incorporated | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| CN103840013A (en) * | 2014-01-26 | 2014-06-04 | 上海韦尔半导体股份有限公司 | Bidirectional TVS and manufacturing method of bidirectional TVS |
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