CN108091649A - Transient Voltage Suppressor and preparation method thereof - Google Patents
Transient Voltage Suppressor and preparation method thereof Download PDFInfo
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- CN108091649A CN108091649A CN201711337521.6A CN201711337521A CN108091649A CN 108091649 A CN108091649 A CN 108091649A CN 201711337521 A CN201711337521 A CN 201711337521A CN 108091649 A CN108091649 A CN 108091649A
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- type
- injection region
- hole
- transient voltage
- voltage suppressor
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- 230000001052 transient effect Effects 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 69
- 238000002347 injection Methods 0.000 claims abstract description 50
- 239000007924 injection Substances 0.000 claims abstract description 50
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of Transient Voltage Suppressors and preparation method thereof.The Transient Voltage Suppressor includes P type substrate, the N-type extension being formed in the P type substrate, the p-type extension being formed in the N-type extension, the silicon oxide layer being formed in the p-type extension, through the silicon oxide layer, the p-type extension and the groove for extending to the outer Yanzhong of the N-type, the p-type injection region being formed in the N-type extension of the channel bottom, it is formed at the silica of the trenched side-wall, the silica and the polysilicon on p-type injection region surface being formed in the groove, through the first through hole and the second through hole of the silica, it is formed at the first N-type injection region of the p-type epitaxial surface and the corresponding first through hole, it is formed at the second N-type injection region of the p-type epitaxial surface and corresponding second through hole.
Description
【Technical field】
The present invention relates to semiconductor device processing technology fields, particularly, are related to a kind of Transient Voltage Suppressor and its system
Make method.
【Background technology】
Transient Voltage Suppressor (TVS) is a kind of for protecting sensitive semiconductor device, it is made to exempt from transient voltage surge
It destroys and specially designed solid-state semiconductor device, it has, and clamp coefficient is small, small, response is fast, leakage current is small and reliable
The advantages that property is high, thus be widely used on voltage transient and carrying out surge protection.The Transient Voltage Suppressor of low capacitance
Suitable for the protection device of high-frequency circuit, because it can reduce interference of the parasitic capacitance to circuit, high-frequency circuit signal is reduced
Attenuation.
The transient voltage that static discharge (ESD) and some other voltage surge form occur at random is typically found in each
In kind electronic device.As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device more and more easily by
To the influence of voltage surge, fatal harm is even resulted in.Various voltage surges can induce wink from static discharge to lightning etc.
State current spike, Transient Voltage Suppressor are impacted commonly used to protection sensitive circuit be subject to surge.Based on different applications, wink
State voltage suppressor can play the role of circuit protection by changing surge discharge path and the clamp voltage of itself.In order to save
Chip area is saved, and obtains higher Surge handling capability, the concept of groove Transient Voltage Suppressor has been suggested and studied.
The junction of groove TVS is formed at the side wall of longitudinal groove, in this way, under identical chip area, it has more effectively knots
Area, i.e., stronger discharge capability.The small package size of groove Transient Voltage Suppressor is very crucial for protecting high-end chip.
Unidirectional protection can only be realized currently used Transient Voltage Suppressor (such as groove Transient Voltage Suppressor), such as
Fruit needs progress bidirectional protective to need multiple Transient Voltage Suppressor serial or parallel connections together, but can so increase device
Part area and manufacture cost.
【The content of the invention】
For the deficiency of existing method, the present invention proposes a kind of Transient Voltage Suppressor and preparation method thereof.
A kind of Transient Voltage Suppressor including P type substrate, the N-type extension being formed in the P type substrate, is formed at
P-type extension in the N-type extension, the silicon oxide layer being formed in the p-type extension, through the silicon oxide layer, the p-type
Extension simultaneously extends to the groove of the outer Yanzhong of the N-type, the p-type injection region being formed in the N-type extension of the channel bottom, is formed
Silica in the trenched side-wall, the silica being formed in the groove and p-type injection region surface polysilicon, pass through
It wears the first through hole of the silica and the second through hole, be formed at the of the p-type epitaxial surface and the corresponding first through hole
One N-type injection region, the second N-type injection region for being formed at the p-type epitaxial surface and corresponding second through hole.
In one embodiment, the Transient Voltage Suppressor further includes the first metal, and first metal includes the
A part, second portion and Part III, the first portion, second portion and Part III are also connected with the first N respectively
Type injection region, the second N-type injection region and the polysilicon.
In one embodiment, the Transient Voltage Suppressor further includes the second metal, and second metal is formed at
Surface of the P type substrate away from the N-type extension.
In one embodiment, the groove is between the first through hole and second through hole.
In one embodiment, the depth of the first N-type injection region and the depth phase of the second N-type injection region
Deng.
A kind of production method of Transient Voltage Suppressor, comprises the following steps：
P type substrate is provided, N-type extension, p-type extension, silicon oxide layer are sequentially formed in the P type substrate, formation runs through
The silicon oxide layer, the p-type extension and the groove for extending to the outer Yanzhong of the N-type；
Thermal oxide is carried out, silica is formed in the trench wall；
Remove the silica of the channel bottom；
P-type ion implanting is carried out so as to outside the N-type of the channel bottom to the N-type epitaxial surface using the groove
Prolong surface and form p-type injection region；
Polysilicon layer is formed in the trench and above the silicon oxide layer；
Remove polysilicon of the groove top above the polysilicon and the silicon oxide layer of the silicon oxide layer, institute
The polysilicon for stating lower trench is retained；
Using photoresist as mask, etch the silicon oxide layer and form first through hole through the silicon oxide layer and the
Two through holes carry out N-type ion implanting so as to be formed in the p-type epitaxial surface using the first through hole and second through hole
First N-type injection region of the corresponding first through hole and the second N-type injection region of corresponding second through hole.
In one embodiment, the method is further comprising the steps of：
Form the first metal, first metal includes first portion, second portion and Part III, described first
Divide, second portion and Part III are also connected with the first N-type injection region, the second N-type injection region and the polysilicon respectively.
In one embodiment, the method is further comprising the steps of：In the P type substrate away from the N-type extension
Surface forms the second metal.
In one embodiment, the groove is between the first through hole and second through hole.
In one embodiment, the depth of the first N-type injection region and the depth phase of the second N-type injection region
Deng.
The Transient Voltage Suppressor that the Transient Voltage Suppressor of the present invention and the production method obtain, in structure design
It introduces multigroup protection circuit to be integrated, optimize technique makes multigroup circuit only can be achieved with integrating with 1 set of mask, makes to reduce device
Part manufactures cost, reduces parasitic capacitance.
【Description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure, wherein：
Fig. 1 is the structure diagram of transient state film suppressor of the present invention.
Fig. 2 is the schematic equivalent circuit of Transient Voltage Suppressor shown in Fig. 1.
Fig. 3 is the flow chart of the production method of Transient Voltage Suppressor shown in Fig. 1.
Fig. 4-Figure 10 is the structure diagram of each step of production method shown in Fig. 3.
【Main element symbol description】
Transient Voltage Suppressor 100；Diode 101,102,103,104,105,106；Step S1-S9
【Specific embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
Referring to Fig. 1, Fig. 1 is the structure diagram of Transient Voltage Suppressor 100 of the present invention.The Transient Voltage Suppressor
100 include P type substrate, the N-type extension being formed in the P type substrate, the p-type extension being formed in the N-type extension, formation
In in the p-type extension silicon oxide layer, through the silicon oxide layer, the p-type extension and extend to Yanzhong outside the N-type
Groove, the p-type injection region being formed in the N-type extension of the channel bottom, the silica for being formed at the trenched side-wall, formation
The polysilicon of silica and p-type injection region surface in the groove, the first through hole and the through the silica
Two through holes, the first N-type injection region for being formed at the p-type epitaxial surface and the corresponding first through hole are formed at outside the p-type
Prolong the second N-type injection region on surface and corresponding second through hole, the first metal, the second metal.
First metal includes first portion, second portion and Part III, the first portion, second portion and the
Three parts are also connected with the first N-type injection region, the second N-type injection region and the polysilicon respectively.Second metal is formed
In surface of the P type substrate away from the N-type extension.Further, the groove is located at the first through hole and described the
Between two through holes.The depth of the first N-type injection region and the deep equality of the second N-type injection region.The first portion,
The terminals of second portion, Part III and second metal as the Transient Voltage Suppressor 100.
Referring to Fig. 2, Fig. 2 is the schematic equivalent circuit of Transient Voltage Suppressor 100 described in Fig. 1.The P type substrate with
The N-type extension forms the first diode 101, and the N-type extension on the left of the groove forms the second pole pipe 102, institute with p-type extension
It states the p-type extension on the left of groove and forms the 3rd diode 103 with the first N-type injection region；N-type extension on the right side of the groove
The 4th diode 104 is formed with p-type extension, the p-type extension on the right side of the groove forms the five or two with the first N-type injection region
Pole pipe 105；The N-type extension forms the 6th diode 106 with the p-type injection region.
Refer to Fig. 3-Figure 10, Fig. 3 is the flow chart of the production method of Transient Voltage Suppressor 100 shown in Fig. 1, Fig. 4-figure
10 be the structure diagram of each step of production method shown in Fig. 3.
The production method of the Transient Voltage Suppressor 100 includes the following steps S1-S9.
Step S1, referring to Fig. 4, provide P type substrate, sequentially formed in the P type substrate N-type extension, p-type extension,
Silicon oxide layer is formed through the silicon oxide layer, the p-type extension and the groove for extending to the outer Yanzhong of the N-type.
Referring to Fig. 5, carrying out thermal oxide, silica is formed in the trench wall by step S2.
Step S3, referring to Fig. 6, removing the silica of the channel bottom.Dry etching may be employed and remove the ditch
The silica of trench bottom.
Step S4, referring to Fig. 7, carrying out p-type ion implanting to the N-type epitaxial surface so as in institute using the groove
The N-type epitaxial surface for stating channel bottom forms p-type injection region.
Step S5, referring to Fig. 8, forming polysilicon layer in the trench and above the silicon oxide layer.
Step S6, referring to Fig. 9, removing polysilicon and the silica of the groove top adjacent to the silicon oxide layer
The polysilicon of layer top, the polysilicon of the lower trench are retained.Dry etching may be employed and remove the groove top neighbour
Polysilicon above the polysilicon and the silicon oxide layer of the nearly silicon oxide layer.
Step S7 referring to Fig. 10, using photoresist as mask, etches the silicon oxide layer and is formed through the oxidation
The first through hole of silicon layer and the second through hole, using the first through hole and second through hole carry out N-type ion implanting so as to
The p-type epitaxial surface forms the first N-type injection region of the corresponding first through hole and the second N-type of corresponding second through hole
Injection region.The first through hole may be employed dry etching with the second through hole and be formed.
Step S8, referring to Fig. 1, forming the first metal, first metal includes first portion, second portion and the 3rd
Part, the first portion, second portion and Part III are also connected with the first N-type injection region, the second N-type injection region respectively
And the polysilicon.
Step S9, referring to Fig. 1, forming the second metal away from the N-type epitaxial surface in the P type substrate.
The Transient Voltage Suppressor that the Transient Voltage Suppressor of the present invention and the production method obtain, in structure design
It introduces multigroup protection circuit to be integrated, optimize technique makes multigroup circuit only can be achieved with integrating with 1 set of mask, makes to reduce device
Part manufactures cost, reduces parasitic capacitance.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
It encloses.
Claims (10)
1. a kind of Transient Voltage Suppressor, it is characterised in that：The Transient Voltage Suppressor includes P type substrate, is formed at the P
N-type extension on type substrate, the p-type extension being formed in the N-type extension, the silicon oxide layer being formed in the p-type extension,
Through the silicon oxide layer, the p-type extension and extend to the groove of Yanzhong outside the N-type, the N for being formed at the channel bottom
P-type injection region in type extension is formed at the silica of the trenched side-wall, the silica being formed in the groove and described
The polysilicon on p-type injection region surface, the first through hole through the silica and the second through hole are formed at the p-type extension table
Face and the first N-type injection region of the corresponding first through hole are formed at the p-type epitaxial surface and corresponding second through hole
Second N-type injection region.
2. Transient Voltage Suppressor as described in claim 1, it is characterised in that：The Transient Voltage Suppressor further includes first
Metal, first metal include first portion, second portion and Part III, the first portion, second portion and the 3rd
Part is also connected with the first N-type injection region, the second N-type injection region and the polysilicon respectively.
3. Transient Voltage Suppressor as claimed in claim 2, it is characterised in that：The Transient Voltage Suppressor further includes second
Metal, second metal are formed at surface of the P type substrate away from the N-type extension.
4. Transient Voltage Suppressor as described in claim 1, it is characterised in that：The groove is located at the first through hole and institute
It states between the second through hole.
5. Transient Voltage Suppressor as described in claim 1, it is characterised in that：The depth of the first N-type injection region and institute
State the deep equality of the second N-type injection region.
6. a kind of production method of Transient Voltage Suppressor, it is characterised in that：It the described method comprises the following steps：
P type substrate is provided, N-type extension, p-type extension, silicon oxide layer are sequentially formed in the P type substrate, is formed through described
Silicon oxide layer, the p-type extension and the groove for extending to the outer Yanzhong of the N-type；
Thermal oxide is carried out, silica is formed in the trench wall；
Remove the silica of the channel bottom；
P-type ion implanting is carried out so as in the N-type extension table of the channel bottom to the N-type epitaxial surface using the groove
Face forms p-type injection region；
Polysilicon layer is formed in the trench and above the silicon oxide layer；
Remove polysilicon of the groove top above the polysilicon and the silicon oxide layer of the silicon oxide layer, the ditch
The polysilicon of slot lower part is retained；And
Using photoresist as mask, etch the silicon oxide layer and formed and led to through the first through hole of the silicon oxide layer and second
Hole carries out N-type ion implanting using the first through hole and second through hole, so as to be formed pair in the p-type epitaxial surface
Answer the first N-type injection region of the first through hole and the second N-type injection region of corresponding second through hole.
7. the production method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：The method further includes following
Step：
Form the first metal, first metal includes first portion, second portion and Part III, the first portion, the
Two parts and Part III are also connected with the first N-type injection region, the second N-type injection region and the polysilicon respectively.
8. the production method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：The method further includes following
Step：In the P type substrate the second metal is formed away from the N-type epitaxial surface.
9. the production method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：The groove is located at described the
Between one through hole and second through hole.
10. the production method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：The first N-type injection region
Depth and the second N-type injection region deep equality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711337521.6A CN108091649A (en) | 2017-12-14 | 2017-12-14 | Transient Voltage Suppressor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711337521.6A CN108091649A (en) | 2017-12-14 | 2017-12-14 | Transient Voltage Suppressor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108091649A true CN108091649A (en) | 2018-05-29 |
Family
ID=62174326
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711337521.6A Withdrawn CN108091649A (en) | 2017-12-14 | 2017-12-14 | Transient Voltage Suppressor and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449153A (en) * | 2018-10-31 | 2019-03-08 | 深圳市富裕泰贸易有限公司 | A kind of power device protection chip and its manufacturing method |
-
2017
- 2017-12-14 CN CN201711337521.6A patent/CN108091649A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449153A (en) * | 2018-10-31 | 2019-03-08 | 深圳市富裕泰贸易有限公司 | A kind of power device protection chip and its manufacturing method |
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Application publication date: 20180529 |
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