CN107316863B - Transient Voltage Suppressor and preparation method thereof - Google Patents
Transient Voltage Suppressor and preparation method thereof Download PDFInfo
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- CN107316863B CN107316863B CN201710564685.6A CN201710564685A CN107316863B CN 107316863 B CN107316863 B CN 107316863B CN 201710564685 A CN201710564685 A CN 201710564685A CN 107316863 B CN107316863 B CN 107316863B
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- 230000001052 transient effect Effects 0.000 title claims abstract description 41
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 238000000407 epitaxy Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 2
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Abstract
The present invention relates to a kind of Transient Voltage Suppressors and preparation method thereof.The Transient Voltage Suppressor includes N-type substrate, the N-type epitaxy layer being formed in the N-type substrate, it is formed in the p-well on the N-type epitaxy layer surface, it is formed in spaced first groove and second groove in the p-well, the n-type doping region being formed in the first groove and the second groove and N-type polycrystalline silicon, the first input electrode being formed in the N-type polycrystalline silicon in the first groove, the second input electrode being formed in the N-type polycrystalline silicon in the second groove, and it is formed in the output electrode in the p-well between the first groove and the second groove, n-type doping region and the N-type polycrystalline silicon in the p-well and first groove constitute the first Zener diode, n-type doping region and the N-type polycrystalline silicon in the p-well and second groove constitute the second Zener diode.
Description
[technical field]
The present invention relates to semiconductor chip manufacturing technology fields, particularly, are related to a kind of Transient Voltage Suppressor and its system
Make method.
[background technique]
Transient Voltage Suppressor (TVS) is a kind of for protecting sensitive semiconductor device, makes it from transient voltage surge
It destroys and specially designed solid-state semiconductor device, it has, and clamp coefficient is small, small in size, response is fast, leakage current is small and reliable
The advantages that property is high, thus be widely used on voltage transient and carrying out surge protection.Static discharge (ESD) and other one
The transient voltage that a little voltage surge forms occur at random, is typically found in various electronic devices.Increasingly with semiconductor devices
Tend to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to the influence of voltage surge, even results in fatal
Injury.Various voltage surges can induce transient current spikes from static discharge to lightning etc., and Transient Voltage Suppressor is usually used
To protect impact of the sensitive circuit by surge.However, how improving device performance and reducing the manufacturing cost of device is industry
Important topic.
[summary of the invention]
The invention proposes a kind of Transient Voltage Suppressor and its manufacturing methods, improve device performance, reduce device
Manufacturing cost.
A kind of Transient Voltage Suppressor comprising N-type substrate, is formed the N-type epitaxy layer being formed in the N-type substrate
In the N-type epitaxy layer surface p-well, be formed in spaced first groove and second groove in the p-well, be formed in institute
State n-type doping region and N-type polycrystalline silicon in first groove and the second groove, the N-type being formed in the first groove
It the first input electrode on polysilicon, the second input electrode in the N-type polycrystalline silicon being formed in the second groove and is formed
The output electrode in p-well between the first groove and the second groove, the p-well are mixed with the N-type in first groove
Miscellaneous region and the N-type polycrystalline silicon constitute the first Zener diode, n-type doping region and institute in the p-well and second groove
It states N-type polycrystalline silicon and constitutes the second Zener diode.
In one embodiment, the n-type doping region is formed uniformly in the first groove and the second groove
Surface, the n-type doping region in the first groove be sandwiched in the first groove and the N-type polycrystalline silicon in it
Between, the n-type doping region in the second groove is sandwiched between the second groove and the N-type polycrystalline silicon in it.
In one embodiment, the first groove is identical as the size of the second groove.
In one embodiment, top surface, the n-type doping region of the p-well far from the N-type substrate are separate described
The either flush of the top surface of N-type substrate and the N-type polycrystalline silicon far from the N-type substrate.
In one embodiment, the thickness of first input electrode, second input electrode and the output electrode
Degree is equal.
A kind of production method of Transient Voltage Suppressor comprising following steps:
N-type substrate is provided, forms N-type epitaxy layer in the N-type substrate, prepares and aoxidizes on the N-type epitaxy layer surface
Layer carries out first time photoetching to the oxide layer, and dry etching forms two injection windows；
The P-type ion note of at least different-energy three times is carried out in the corresponding N-type epitaxy layer of described two injection windows
Enter；
High annealing is carried out, the P-type ion of described two injection window injections diffuses to form p-well；
Use the oxide layer as exposure mask, carries out dry etching using described two injection windows, formed and be located at the P
The bottom of first groove and second groove in trap, the first groove and the second groove has away from the bottom of the p-well
Preset distance；
N-type thermal diffusion is carried out, so that the first groove and the second groove surface form n-type doping region；
Remove the oxide layer；
In the first groove and the second groove and the N-doped zone field surface forms N-type polycrystalline silicon；And
The first input electrode is formed in the N-type polycrystalline silicon of the first groove, in the N-type polycrystalline silicon of the second groove
The second input electrode of upper formation forms output electrode in the p-well between the first groove and the second groove,
Wherein, the p-well and n-type doping region and N-type polycrystalline silicon composition two pole of the first Zener in first groove
N-type doping region and the N-type polycrystalline silicon in pipe, the p-well and second groove constitute the second Zener diode.
In one embodiment, the energy of the injection of P-type ion three times is gradually increased.
In one embodiment, the step of removal oxide layer includes carrying out wet etching to remove the oxidation
Layer.
In one embodiment, the method also includes: in the N-type epitaxy layer, the p-well, the N-doped zone
N-type polycrystalline silicon layer is formed on domain, is carried out dry etching and is removed the N-type epitaxy layer, the p-well, the N-doped zone field surface
Part N-type polycrystalline silicon, the N-type polycrystalline silicon in the first groove and the second groove retains to form the N-type more
Crystal silicon.
In one embodiment, the method also includes: in the N-type epitaxy layer, the p-well, the N-doped zone
Domain and the N-type polycrystalline silicon surface prepare metal layer, carry out second of photoetching to the metal layer, dry or wet etch and fast
Speed heat annealing, forms first input electrode, the second input electrode and output electrode.
Compared to the prior art, in Transient Voltage Suppressor proposed by the present invention and preparation method thereof, it is only necessary to carry out two
Secondary photoetching can be prepared by the Transient Voltage Suppressor, and simple process reduces manufacturing cost, two Zener diodes
P-well is formed by the ion implanting of different-energy more than three times, and doping concentration is uniform, the stable breakdown voltage of device with it is consistent
Property is good.The area N of two Zener diodes can increase machining area, improve by diffuseing to form after etching groove
Device original area, reduces device cost.The Transient Voltage Suppressor that the method is formed is inputted at least two-way, side
Just multiple circuits are protected in application process simultaneously, reduces the application cost of device.
[Detailed description of the invention]
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure, in which:
Fig. 1 is the structural schematic diagram of Transient Voltage Suppressor of the present invention.
Fig. 2 is the schematic equivalent circuit of Transient Voltage Suppressor shown in Fig. 1.
Fig. 3 is the flow chart of the production method of Transient Voltage Suppressor shown in Fig. 1.
Fig. 4-Figure 12 is the structural schematic diagram of each step of production method shown in Fig. 3.
[main element symbol description]
Transient Voltage Suppressor 100；N-type substrate 101；N-type epitaxy layer 102；P-well 103；First groove 104；Second groove
105；N-type doping region 106；N-type polycrystalline silicon 107；First input electrode 108；Second input electrode 109；Output electrode 110；
First Zener diode 111；Second Zener diode 112；Oxide layer 113；Inject window 114；Step S1~S8
[specific embodiment]
The technical scheme in the embodiments of the invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's all other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
Big to solve prior art Transient Voltage Suppressor area, technology difficulty is high, and the technologies such as device manufacturing cost height are asked
Topic, the present invention provide a kind of improved Transient Voltage Suppressor, please refer to Fig. 1 and Fig. 2, and Fig. 1 is transient voltage suppression of the present invention
The structural schematic diagram of device 100 processed, Fig. 2 are the schematic equivalent circuits of Transient Voltage Suppressor 100 shown in Fig. 1.The transient state electricity
Pressure suppressor 100 includes N-type substrate 101, the N-type epitaxy layer 102 being formed in the N-type substrate 101, is formed in the N-type
The p-well 103 on 102 surface of epitaxial layer is formed in spaced first groove 104 and second groove 105, shape in the p-well 103
First groove 104 described in Cheng Yu and the n-type doping region 106 in the second groove 105 and N-type polycrystalline silicon 107 are formed in institute
State the first input electrode 108 in the N-type polycrystalline silicon 107 in first groove 104, the N-type being formed in the second groove 105
The second input electrode 109 on polysilicon 107 and the P being formed between the first groove 104 and the second groove 105
Output electrode 110 on trap 103, the p-well 103 in the first groove 104 n-type doping region 106 and the N-type it is more
Crystal silicon 107 constitutes the first Zener diode 111, the p-well 103 in the second groove 105 n-type doping region 106 and
The N-type polycrystalline silicon 108 constitutes the second Zener diode 112.
Specifically, the n-type doping region 106 is formed uniformly in the first groove 104 and 105 table of second groove
Face, the n-type doping region 106 in the first groove 104 is sandwiched in the first groove 104 and the N-type in it is more
Between crystal silicon 107, the n-type doping region 106 in the second groove 105 is sandwiched in the second groove 105 and its
Between the N-type polycrystalline silicon 107.In present embodiment, the bottom of the first groove 104 and the second groove 105 is away from institute
The bottom for stating p-well 103 has preset distance, i.e., the described first groove 104 cannot run through the p-well with the second groove 105
103.The size of the first groove 104 and the second groove 105 is essentially identical, the first groove 104 and described second
The thickness in the n-type doping region 106 in groove 105 is equal.Top surface of the p-well 103 far from the N-type substrate 101, the N
Top surface and the N-type polycrystalline silicon 107 of the type doped region 106 far from the N-type substrate 101 are far from the N-type substrate 101
Either flush.The thickness of first input electrode 108, second input electrode 109 and the output electrode 110 is homogeneous
Deng.
Fig. 3-Figure 12 is please referred to, Fig. 3 is the flow chart of the production method of Transient Voltage Suppressor 100 shown in Fig. 1, Fig. 4-figure
12 be the structural schematic diagram of each step of production method shown in Fig. 3.The production method of the Transient Voltage Suppressor 100 include with
Lower step S1~S8.
Step S1 forms N-type epitaxy layer 102 referring to Fig. 4, providing N-type substrate 101 in the N-type substrate 101,
102 surface of N-type epitaxy layer prepares oxide layer 113, carries out first time photoetching to the oxide layer 113, dry etching is formed
Two injection windows 114.Specifically, in one embodiment, the N-type substrate 101 is N-type silicon chip, the N-type epitaxy layer
102 grow from the N-type substrate, and the oxide layer 111 is silicon dioxide layer, can be by institute in the step S1
It states 102 surface thermal oxide of N-type epitaxy layer and prepares the silicon dioxide layer.
Step S2, referring to Fig. 5, the corresponding N-type epitaxy layer of described two injection windows 114 into 102 rows at least
The P-type ion injection of different-energy three times.In the step S2, the energy of the injection of P-type ion three times successively enhances.
Step S3, referring to Fig. 6, high annealing is carried out, the P-type ion divergent contour that described two injection windows 114 inject
At p-well 103.
Step S4, referring to Fig. 7, use the oxide layer 113 as exposure mask, using described two injection windows 114 into
Row dry etching forms the first groove 104 being located in the p-well 103 and second groove 105, the first groove 104 and institute
The bottom for stating second groove 105 has preset distance away from the bottom of the p-well 103.
Step S5, referring to Fig. 8, N-type thermal diffusion is carried out in the first groove 104 and the second groove 105, so that
The first groove 104 forms n-type doping region 106 with 105 surface of second groove；
Step S6, referring to Fig. 9, removing the oxide layer 113；Specifically, in the step S3, wet process corruption can be carried out
Etching off removes the oxide layer 113.
Step S7 please refers to Figure 10 and 11, the first groove 104 in the second groove 105 and the N-type is mixed
Miscellaneous 106 surface of region forms N-type polycrystalline silicon 107.Specifically, in the step S7, referring to Fig. 10, in the N-type epitaxy layer
102, the p-well 103, N-type polycrystalline silicon layer is formed on the n-type doping region 106；Figure 11 is please referred to, dry etching is carried out and goes
Except the N-type epitaxy layer 102, the p-well 103, the part N-type polycrystalline silicon on 106 surface of n-type doping region, described first
N-type polycrystalline silicon in groove 104 and the second groove 105 retains to form the N-type polycrystalline silicon 107.
Step S8, please refers to Figure 11, forms the first input electrode in the N-type polycrystalline silicon 107 of the first groove 104
108, the second input electrode 109 is formed in the N-type polycrystalline silicon 107 of the second groove 105, the first groove 104 with
Output electrode 110 is formed in p-well 103 between the second groove 105.Specifically, in the step S8: outside the N-type
Prolong layer 102, the p-well 103, the n-type doping region 106 and 107 surface of the N-type polycrystalline silicon and prepare metal layer, to described
Metal layer carries out second of photoetching, dry or wet etch and rapid thermal annealing, forms first input electrode 108, second
Input electrode 109 and output electrode 110.
Compared to the prior art, in Transient Voltage Suppressor 100 proposed by the present invention and preparation method thereof, it is only necessary to carry out
Twi-lithography can be prepared by the Transient Voltage Suppressor 100, and simple process reduces manufacturing cost, two Zeners two
The p-well of pole pipe 111,112 is formed by the ion implanting of different-energy more than three times, and doping concentration is uniform, the breakdown potential of device
Press stability and consistency good.Two Zeners, two pole 111,112 pipes the area N can pass through divergent contour after etching groove
At increasing machining area, improve device original area, reduce device cost.The transient voltage suppression that the method is formed
Device 100 processed is inputted at least two-way, is facilitated in application process to multiple circuits while being protected, reduces being applied to for device
This.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to protection model of the invention
It encloses.
Claims (9)
1. a kind of Transient Voltage Suppressor, it is characterised in that: the Transient Voltage Suppressor includes N-type substrate, is formed in the N
N-type epitaxy layer on type substrate, is formed in spaced in the p-well p-well for being formed in the N-type epitaxy layer surface
One groove and second groove, the n-type doping region being formed in the first groove and the second groove and N-type polycrystalline silicon,
The first input electrode in the N-type polycrystalline silicon being formed in the first groove, the N-type polycrystalline being formed in the second groove
The second input electrode on silicon and the output electrode in the p-well being formed between the first groove and the second groove, institute
The n-type doping region and the N-type polycrystalline silicon stated in p-well and first groove constitute the first Zener diode, the p-well and second
N-type doping region and the N-type polycrystalline silicon in groove constitute the second Zener diode；The n-type doping region is formed uniformly
The n-type doping region in the first groove and the second groove surface, the first groove is sandwiched in described first
Between groove and the N-type polycrystalline silicon in it, the n-type doping region in the second groove is sandwiched in the second groove
Between the N-type polycrystalline silicon in it；Wherein, by carrying out N-type thermal diffusion, so that the first groove and second ditch
Rooved face forms the n-type doping region.
2. Transient Voltage Suppressor as described in claim 1, it is characterised in that: the first groove and the second groove
Size is identical.
3. Transient Voltage Suppressor as described in claim 1, it is characterised in that: top of the p-well far from the N-type substrate
The top surface of top surface and the N-type polycrystalline silicon far from the N-type substrate of face, the n-type doping region far from the N-type substrate
Concordantly.
4. Transient Voltage Suppressor as described in claim 1, it is characterised in that: first input electrode, described second defeated
The thickness for entering electrode and the output electrode is equal.
5. a kind of production method of Transient Voltage Suppressor comprising following steps:
N-type substrate is provided, forms N-type epitaxy layer in the N-type substrate, prepares oxide layer on the N-type epitaxy layer surface, it is right
The oxide layer carries out first time photoetching, and dry etching forms two injection windows；
The P-type ion injection of at least different-energy three times is carried out in the corresponding N-type epitaxy layer of described two injection windows；
High annealing is carried out, the P-type ion of described two injection window injections diffuses to form p-well；
Use the oxide layer as exposure mask, carries out dry etching using described two injection windows, formed and be located in the p-well
First groove and second groove, the bottom of the first groove and the second groove has predetermined away from the bottom of the p-well
Distance；
N-type thermal diffusion is carried out, so that the first groove and the second groove surface form n-type doping region；
Remove the oxide layer；
In the first groove and the second groove and the N-doped zone field surface forms N-type polycrystalline silicon；And
The first input electrode is formed in the N-type polycrystalline silicon of the first groove, the shape in the N-type polycrystalline silicon of the second groove
At the second input electrode, output electrode is formed in the p-well between the first groove and the second groove,
Wherein, the p-well and n-type doping region and the N-type polycrystalline silicon the first Zener diode of composition in first groove, institute
The n-type doping region and the N-type polycrystalline silicon stated in p-well and second groove constitute the second Zener diode.
6. the production method of Transient Voltage Suppressor as claimed in claim 5, it is characterised in that: the note of P-type ion three times
The energy entered is gradually increased.
7. the production method of Transient Voltage Suppressor as claimed in claim 5, it is characterised in that: the removal oxide layer
The step of include carrying out wet etching to remove the oxide layer.
8. the production method of Transient Voltage Suppressor as claimed in claim 5, it is characterised in that: the method also includes:
The N-type epitaxy layer, the p-well form N-type polycrystalline silicon layer on the n-type doping region, carry out dry etching and remove the N
Type epitaxial layer, the p-well, the part N-type polycrystalline silicon of the N-doped zone field surface, the first groove and second ditch
N-type polycrystalline silicon in slot retains to form the N-type polycrystalline silicon.
9. the production method of Transient Voltage Suppressor as claimed in claim 5, it is characterised in that: the method also includes:
The N-type epitaxy layer, the p-well, the n-type doping region and the N-type polycrystalline silicon surface prepare metal layer, to the metal
Layer carries out second of photoetching, dry or wet etch and rapid thermal annealing, forms first input electrode, the second input electrode
And output electrode.
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| CN109360823B (en) * | 2018-10-08 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Groove type transient voltage suppressor and manufacturing method thereof |
| CN109950326A (en) * | 2019-04-15 | 2019-06-28 | 深圳市槟城电子有限公司 | A kind of bilateral diode and preparation method thereof, overvoltage protection |
| CN113690232A (en) * | 2021-08-24 | 2021-11-23 | 安芯半导体技术(深圳)有限公司 | Bidirectional electrostatic protection chip and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818084A (en) * | 1996-05-15 | 1998-10-06 | Siliconix Incorporated | Pseudo-Schottky diode |
| CN101536189A (en) * | 2006-11-16 | 2009-09-16 | 万国半导体股份有限公司 | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (tvs) and emi filter |
| CN101557103A (en) * | 2008-04-11 | 2009-10-14 | 上海韦尔半导体股份有限公司 | Transient voltage suppresser diode and manufacturing method thereof |
| CN103354236A (en) * | 2013-07-12 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | Silicon-controlled transient voltage inhibitor with embedded Zener diode structure |
| CN103579366A (en) * | 2012-08-03 | 2014-02-12 | 上海华虹Nec电子有限公司 | TVS device and manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7880223B2 (en) * | 2005-02-11 | 2011-02-01 | Alpha & Omega Semiconductor, Ltd. | Latch-up free vertical TVS diode array structure using trench isolation |
| US20100025809A1 (en) * | 2008-07-30 | 2010-02-04 | Trion Technology, Inc. | Integrated Circuit and Method of Forming Sealed Trench Junction Termination |
-
2017
- 2017-07-12 CN CN201710564685.6A patent/CN107316863B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818084A (en) * | 1996-05-15 | 1998-10-06 | Siliconix Incorporated | Pseudo-Schottky diode |
| CN101536189A (en) * | 2006-11-16 | 2009-09-16 | 万国半导体股份有限公司 | Circuit configuration and manufacturing processes for vertical transient voltage suppressor (tvs) and emi filter |
| CN101557103A (en) * | 2008-04-11 | 2009-10-14 | 上海韦尔半导体股份有限公司 | Transient voltage suppresser diode and manufacturing method thereof |
| CN103579366A (en) * | 2012-08-03 | 2014-02-12 | 上海华虹Nec电子有限公司 | TVS device and manufacturing method |
| CN103354236A (en) * | 2013-07-12 | 2013-10-16 | 江苏艾伦摩尔微电子科技有限公司 | Silicon-controlled transient voltage inhibitor with embedded Zener diode structure |
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