CN205984999U - Take power transistor of electrostatic discharge protective diode structure - Google Patents
Take power transistor of electrostatic discharge protective diode structure Download PDFInfo
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- CN205984999U CN205984999U CN201620705988.6U CN201620705988U CN205984999U CN 205984999 U CN205984999 U CN 205984999U CN 201620705988 U CN201620705988 U CN 201620705988U CN 205984999 U CN205984999 U CN 205984999U
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Abstract
The utility model relates to a take power transistor of electrostatic discharge protective diode structure. Power transistor includes the terminal area, the active area, be located the polysilicon gate district between terminal area and the active area, polysilicon gate phase separation in polysilicon gate district and the active area, the polysilicon gate district is including the electrostatic discharge protective diode structure of grid and grid both sides, the material of grid and electrostatic discharge protective diode structure is polycrystalline silicon, the electrostatic discharge protective diode structure of grid both sides includes a plurality of P type doped regions and N type doped region, and P type doped region and N type doped region interval arrangement on the first direction, polysilicon gate district both sides are in outermost N type doped region and have seted up first contact hole, the second contact hole has been seted up to the grid. The utility model discloses a polysilicon gate phase separation in polysilicon gate district and the active area forms an independent island structure, be convenient for the grid through the second contact hole draw forth with grid metallic interconnect, do benefit to and encapsulate in batches.
Description
Technical field
This utility model is related to field of semiconductor manufacture, more particularly to a kind of static electrification discharge prevention diode structure
Power transistor.
Background technology
Static discharge is one of most important integrity problem of power device.Static discharge abbreviation ESD
(ElectroStatic Discharge), is a kind of rapid electric charge transfer phenomena between two objects, and this phenomenon is adjoint
There are very big electric field and electric current density.Electrostatic is hard to guard against, generally deposits in production, storage, transport and the use of power device
?.Static discharge can produce several kilovolts of discharge voltage at power device two ends, in the application and production of power device, is to lead
Cause the major reason that power device damages.When the voltage at device two ends exceedes breakdown voltage, any significant electric current is all
Very big power consumption can be caused, lead to device to produce local heating.If temperature rise is sufficiently large, temperature is caused to reach intrinsic temperature, that is,
Just this situation occurs in local, and the electric current being formed is likely to cause heat is run quickly.Increasingly complicated and micro- electricity with electromagnetic environment
The continuous reduction of the power device gate oxide thickness that the development of sub- technology is led to, the protection to ESD becomes more and more important.
The development of the power transistor of domestic integrated anti-ESD protection is still in the starting stage, with external main flow power crystal
The matured product gap with ESD protection of pipe manufacturer is larger.Power device esd protection structure generally adopts PN junction, SCR (controlled
Silicon) and three kinds of structures of POLY (polysilicon) diode.
Utility model content
Based on this it is necessary to provide a kind of power transistor of the static electrification discharge prevention diode structure being easy to and encapsulating.
A kind of power transistor of static electrification discharge prevention diode structure, surrounds including termination environment with by described termination environment
Active area, also include positioned at the polysilicon gate polar region between described termination environment and active area, described polysilicon gate polar region and institute
The polysilicon gate stated in active area is separated, and described polysilicon gate polar region includes grid and the static discharge of described grid both sides is protected
Shield diode structure, the material of described grid and electro-static discharge protection diodes structure is polysilicon, described grid both sides
Electro-static discharge protection diodes structure includes multiple p-type doped regions and n-type doping area, and described p-type doped region and n-type doping area
It is spaced in a first direction, described first direction is the direction that described grid extends to both sides；Described polysilicon gate polar region
Both sides are in the p-type doped region of outermost or n-type doping area offers the first contact hole, and described grid offers the second contact hole,
Described second contact hole is used for being connected with gate metal, and described first contact hole is used for being connected with source metal.
Wherein in an embodiment, the doping type of described grid is N-type.
Wherein in an embodiment, described polysilicon gate polar region is surrounded by described active area and termination environment, wherein said
Three faces of polysilicon gate polar region are surrounded by described active area, and remaining one side is formed by described termination environment surrounds.
Wherein in an embodiment, the width in each p-type doped region and n-type doping area is all equal, the direction of described width
It is the second direction perpendicular to described first direction.
Wherein in an embodiment, described grid first side adjacent with described termination environment outwardly makes described grid
The width of pole is more than the width in described p-type doped region and n-type doping area.
Wherein in an embodiment, described second contact hole is arranged at the region that described first side is outwardly formed.
Wherein in an embodiment, the cross section of described first contact hole is the strip extending along described second direction
Shape, the cross section of described second contact hole is the strip extending along described first direction.
Wherein in an embodiment, the doping content of each described p-type doped region is less than the doping in each described n-type doping area
Concentration, each described p-type doped region size in said first direction is more than each described n-type doping area in said first direction
Size.
Wherein in an embodiment, described grid with described first in relative second with each p-type doped region and each N
The corresponding side of type doped region keeps concordant.
Wherein in an embodiment, the adjacent each pair p-type doped region of described electro-static discharge protection diodes structure and N-type
Doped region forms a diode, and the number of diodes of the both sides of described grid is each 3～6 of every side.
Polycrystalline in the power transistor of above-mentioned static electrification discharge prevention diode structure, polysilicon gate polar region and active area
Si-gate bar is separated, and forms an independent little island structure, and polysilicon gate polar region both sides are tied for electro-static discharge protection diodes
Structure, middle is grid, is easy to grid and is connected with gate metal by the second contact hole extraction, encapsulates beneficial to batch.
Brief description
Fig. 1 is the planar structure schematic diagram of the power transistor of static electrification discharge prevention diode structure in an embodiment；
Fig. 2 is the planar structure schematic diagram of grid 31 in an embodiment；
Fig. 3 is the planar structure schematic diagram of grid 31 in another embodiment；
Fig. 4 is the planar structure signal of device after the polycrystalline grid 21 that increased on the basis of Fig. 1 in active area 2
Figure；
Fig. 5 is the flow process of the manufacture method of power transistor of static electrification discharge prevention diode structure in an embodiment
Figure.
Specific embodiment
For the ease of understanding this utility model, below with reference to relevant drawings, this utility model is more fully retouched
State.First-selection embodiment of the present utility model is given in accompanying drawing.But, this utility model can come real in many different forms
Existing however it is not limited to embodiment described herein.On the contrary, providing the purpose of these embodiments to be to make to public affairs of the present utility model
Open content more thoroughly comprehensive.
Unless otherwise defined, all of technology used herein and scientific terminology are led with belonging to technology of the present utility model
The implication that the technical staff in domain is generally understood that is identical.In term used in the description of the present utility model it is simply herein
The purpose of description specific embodiment is it is not intended that in limiting this utility model.Term as used herein " and/or " include
The arbitrary and all of combination of one or more related Listed Items.
The technical words that semiconductor applications vocabulary used herein is commonly used for those skilled in the art, such as p-type
And N-type impurity, for distinguishing doping content, simply P+ type is represented the p-type of heavy dopant concentration, the P of doping content in p-type representative
Type, P-type represents the p-type that concentration is lightly doped, and N+ type represents the N-type of heavy dopant concentration, the N-type of doping content, N- in N-type representative
Type represents the N-type that concentration is lightly doped.
Power transistor can be vertical DMOS field-effect transistor (VDMOSFET), insulation
Grid bipolar transistor (IGBT) constant power device.It is most susceptible to due between the grid source electrode of power transistor such as VDMOS
ESD damage, therefore, this utility model relates generally to the esd protection structure between grid source electrode.
Fig. 1 is the planar structure schematic diagram of the power transistor of static electrification discharge prevention diode structure in an embodiment,
Including termination environment 1, the active area 2 being surrounded by termination environment 1, and it is located at the polysilicon gate polar region between termination environment 1 and active area 2
3, polysilicon gate polar region 3 is separated with the polysilicon gate (not showing in Fig. 1) in active area 2.Polysilicon gate polar region 3 includes grid 31
With the electro-static discharge protection diodes structure 32 of grid 31 both sides, the material of grid 31 and electro-static discharge protection diodes structure 32
It is polysilicon.Fig. 2 is the planar structure schematic diagram of grid 31 in an embodiment.Electrostatic discharge (ESD) protection two pole of grid 31 both sides
Tubular construction 32 includes multiple p-type doped regions and n-type doping area, in p-type doped region and n-type doping area Y direction in fig. 2 between
Every arrangement, and the direction that Y direction extends to both sides for grid 31.Every a pair of p-type doped region becomes a PN with n-type doping district's groups
Diode.Polysilicon gate polar region 3 both sides are in the p-type doped region of outermost or n-type doping area offers the first contact hole 321, grid
Pole 31 offers the second contact hole 311.Second contact hole 311 is used for being connected with gate metal, and the first contact hole 321 is used for and source
Pole metal is connected.
The power transistor of above-mentioned static electrification discharge prevention diode structure is many in polysilicon gate polar region 3 and active area 2
Crystal silicon grizzly bar is separated, and forms an independent little island structure, and polysilicon gate polar region 3 both sides are electro-static discharge protection diodes
Structure 32, middle is grid 31, is easy to grid 31 and is connected with gate metal by the second contact hole 311 extraction, seals beneficial to batch
Dress.The PN diode that p-type doped region becomes with n-type doping district's groups can clamp to grid source forward voltage and backward voltage simultaneously,
Prevent the damage to power device of the high electrostatic potential of different directions.
Because grid source bias operation scope is 0-20V, therefore between design grid source during esd protection structure, cut-in voltage can not
Less than 20V, in order to avoid ESD protection diode is opened during power transistor (such as VDMOS) normal work.But ESD protective device
Cut-in voltage nor too big, because if cut-in voltage is higher than gate oxide breakdown voltage, does not then have ESD protective effect.
The setting of therefore cut-in voltage (total breakdown voltage) Vtrig of ESD protection diode should meet following principle：Vgs<Vtrig<
BVox, that is, be more than grid source bias, be less than gate oxide breakdown voltage.Specifically multiple polysilicon diodes can be cascaded
To improve the cut-in voltage of ESD protection diode.Wherein in an embodiment, the number of polysilicon diode is 31 liang of grid
Each 3 to 6 of the electro-static discharge protection diodes structure 32 of side, specifically flexibly can be arranged according to the thickness of grid oxygen.
In the embodiment shown in fig. 1, polysilicon gate polar region 3 be at least partially by the active region 2 and termination environment 1 surround, wherein polysilicon gate
Three faces in area 3 are at least partially by the active region 2 encirclements, and remaining one side is formed by termination environment 1 again surrounds.
In the embodiment depicted in figure 2, the doping type of grid 31 is N-type, the therefore electrostatic discharge (ESD) protection of grid 31 both sides
The doped region being in outermost in diode structure 32 is n-type doping area.And this n-type doping area is due to will arrange the first contact hole
321 the reason, so the size in Y direction is more than other n-type doping areas.
In the embodiment depicted in figure 2, the width in each p-type doped region and n-type doping area is all equal, and width herein refers to figure
The direction of X-axis in 2.Each p-type doped region is more than the size in Y direction for each n-type doping area in the size of Y direction, and reason is N
The doping content of type doped region is more than the doping content of p-type doped region.
Fig. 3 is the planar structure schematic diagram of grid 31 in another embodiment.In the embodiment shown in fig. 3, grid 31 and end
The adjacent one side a of petiolarea 1 outwardly makes the width of grid 31 be more than the width in p-type doped region and n-type doping area.And at this
In embodiment, the b relative with a is concordant with p-type doped region, the corresponding side in n-type doping area.
The total length impact HBM (human mould in the p-type doped region of electro-static discharge protection diodes structure 32 and n-type doping area
Type) voltage size.The anti-ESD index request of general power device reaches more than HBM 2000V.The anti-ESD's of power device
Ability is relevant with the total length of p-type doped region and n-type doping area, and total length is bigger, and the ability of anti-ESD is bigger, but total length
Conference increases grid source and drain electricity Igss.Electro-static discharge protection diodes structure 32 for grid 31 both sides respectively has 5 polysilicons two
The embodiment of pole pipe, when the width (X-direction in Fig. 3) in p-type doped region and n-type doping area is all 180 microns, HBM can
Reach 14KV, more than sufficient for HBM voltage request, and 180 microns of width has one for the encapsulation of big tube core
Determine difficulty, be unfavorable for that batch encapsulates.And adopt structure shown in Fig. 3, the prominent area that will not increase chip of grid 31, because
The outside (i.e. the outside of side a) of chip active area 2 edge grizzly bar be usually constructed with 30 to 50 microns active area 2 and termination environment 1 it
Between transition region, the top in this region is the gate metal for grizzly bar pass gate pole tension, and the lower section of transition region is that terminal was injected
Cross area, all there is no cellular, thus dexterously make use of these regions to increase grid pressure welding area area.
The design of above-mentioned grid 31 evagination can mitigate encapsulation difficulty, beneficial to scale encapsulation, will not increase grid simultaneously again
Source and drain electricity Igss, because the Igss electric leakage of esd protection structure is mainly by logarithm and the polysilicon diode of polysilicon diode
Length determined, and process on polysilicon shape so does not all affect on said two devices.
Further, in the embodiment shown in fig. 3, the second contact hole 311 is arranged at the region that side a is outwardly formed.
The grid region of the power transistor with ESD diode (such as VDMOS) is typically small.If as in Figure 2 by the second contact hole
311 central authorities being arranged at grid 31, then the pressure welding point in grid region be normally at the central authorities of chip, the presence meeting of the second contact hole 311
Lead to the out-of-flatness of grid region metal surface, cause the difficulty of pressure welding.And the second contact hole 311 is arranged at side a in embodiment illustrated in fig. 3
The region outwardly being formed, can vacate a panel region on the right side of grid 31 in figure 3, be more beneficial in the metal of grid region
Centre carries out pressure welding and encapsulation, is conducive to the batch being packaged to carry out.Further, in the embodiment shown in fig. 3, the first contact
The cross section in hole 321 is the strip extending along X-direction, and the cross section of the second contact hole 311 is the length extending along Y direction
Bar shaped.
Fig. 4 is the planar structure schematic diagram of device after the polycrystalline grid 21 that increased in active area 2, Fig. 4 dielectric layer,
Metal level and passivation layer are all not shown.3rd contact hole 22 is offered on polycrystalline grid 21, the 3rd contact hole 22 is used for and grid
Pole metal is connected.It is the etch areas of active area metal between dotted line A and B on the 3rd contact hole 22 side, between C and D.This quarter
Gate metal and source metal are separated by erosion region, and the active area outer peripheral areas of dotted line A and D are gate metal, dotted line B's and C
Active area inside region is source metal.Can keep away after polysilicon gate polar region 3 is separated as a little island structure with active area 2
Exempt from grid source short.Because if electro-static discharge protection diodes structure 32 is connected with polycrystalline grid 21, due to the first contact
Hole 321 is connected with source region metal, then electro-static discharge protection diodes structure 32, polycrystalline grid 21 are all connected with source electrode, and many
Crystal silicon grizzly bar 21 is connected with grid further through the 3rd contact hole 22, so will result in grid source short, makes cut-in voltage VTHFor
Zero, grid source breakdown voltage Vgs is zero, and grid source and drain electricity Igss lost efficacy (Over).This polysilicon gate polar region 3 independently little island structure pair
Bar shaped cellular is such, and square shaped cellular is even more it should be noted that this point.
Fig. 5 is the flow process of the manufacture method of power transistor of static electrification discharge prevention diode structure in an embodiment
Figure, comprises the following steps：
S110, forms field oxide and gate oxide on substrate.
(can be injected by P+ and be formed, in this specification, be referred to as first time P+ in the p-type field limiting ring forming termination environment
Injection) and after carrying out active area field oxide etching, carry out the preparation of the gate oxide of active area.An embodiment wherein
In, grow grid oxygen by the way of thermal oxide.The growth of grid oxygen can adopt dry oxygen technique, it would however also be possible to employ dry and wet do (dry oxygen-
Wet oxygen-dry oxygen) technique.
S120, on gate oxide and/or field oxide, depositing polysilicon is to form polysilicon gate.
In the present embodiment, it is depositing polysilicon, and carries out the N-type ion of polysilicon to spread (in other embodiments
Can be that N-type ion implanting is carried out to polysilicon), N-type ion can be phosphonium ion, then carry out photoetching and quarter to polysilicon
Erosion, forms polysilicon gate.Referring to Fig. 4, polysilicon gate here includes polysilicon gate polar region 3 and polycrystalline grid 21.Many
Polysilicon gate area 3 is specifically disposed on field oxide or gate oxide, can be according to the different kinds of process flow spirit of each company
Live and select.
S130, implanting p-type ion, form p-well in substrate, and polysilicon gate polar region is because of p-type ion implanting formation P- area.
Implanting p-type foreign ion simultaneously spreads, and forms p-well, and the electro-static discharge protection diodes structure 32 of grid 31 both sides
Region is now because injection forms P- area.
S140, injects N-type ion, forms N+ source region in p-well, forms ESD protection diode knot in polysilicon gate polar region
Structure.
This step, when injecting N-type ion (N+ injection), photoresist is covered in electro-static discharge protection diodes structure 32
P-type doped region be located position, make these regions do not have N-type impurity inject, therefore after N-type ion implanting, 31 liang of grid
The p-type doped region of side and n-type doping are spaced formation electro-static discharge protection diodes structure 32 in a first direction.Due to quiet
Photoresist and the N+ of N+ source region implant blocking layer that p-type doped region position in discharge of electricity protection diode structure 32 covers
Photoresist is formed in same layer photoetching level, thus with conventional (without ESD protection diode structure) power device
Part manufacturing process flow is compatible, does not increase photoetching level.Manufacture with respect to traditional power device with esd protection structure
Method decreases a photoetching level, thus decreasing manufacturing cost.
S150, dielectric layer deposited on substrate and polysilicon gate.
In the present embodiment, using non-impurity-doped silica glass (USG) and phosphorosilicate glass (PSG) double-decker as medium
Layer.In other embodiments, it would however also be possible to employ other known dielectric layer material and other structures (the dielectric layer knot of such as monolayer
Structure).
S160, carries out contact hole photoetching and etching, forms contact hole.
Contact hole includes：Second contact hole 311, for being connected with gate metal；First contact hole 321, for source electrode
Metal is connected；3rd contact hole 22, for being connected with gate metal.
S170, carries out P+ injection by contact hole to p-well.
After forming contact hole, it is in the region below corresponding contact hole in p-well and exposes, such that it is able to by contact hole pair
P-well carries out P+ injection.In order to reduce the Igss big problem of electric leakage in grid source in the esd protection structure of routine, the present embodiment is by tradition
Power device manufacturing process in be generally placed upon second P+ injection between step S140 and S150, be adjusted to and carve in contact hole
Carry out after erosion, so that the dielectric layer of step S150 deposit can stop that second P+ injects to electro-static discharge protection diodes structure
The impact of the p-type doped region in 32, does not become P+ area, thus can greatly reduce Igss electric leakage, low so as to produce
Cost, the power device of high reliability.
S180, forms metal interconnecting layer.
To after contact hole filler metal (such as tungsten), front metal layer is formed on dielectric layer.This step is gone back after completing
Can carry out forming passivation layer on front metal layer, carry out the steps such as the back process of power transistor.
Embodiment described above only have expressed several embodiments of the present utility model, and its description is more concrete and detailed,
But therefore can not be interpreted as the restriction to utility model patent scope.It should be pointed out that the common skill for this area
For art personnel, without departing from the concept of the premise utility, some deformation can also be made and improve, these broadly fall into
Protection domain of the present utility model.Therefore, the protection domain of this utility model patent should be defined by claims.
Claims (10)
1. a kind of power transistor of static electrification discharge prevention diode structure, surrounded including termination environment and by described termination environment
Active area is it is characterised in that also include positioned at the polysilicon gate polar region between described termination environment and active area, described polysilicon gate
Polysilicon gate in polar region and described active area is separated, and described polysilicon gate polar region includes the quiet of grid and described grid both sides
Discharge of electricity protection diode structure, the material of described grid and electro-static discharge protection diodes structure is polysilicon, described grid
The electro-static discharge protection diodes structure of pole both sides includes multiple p-type doped regions and multiple n-type doping area, and the doping of described p-type
Area and n-type doping area are spaced in a first direction, and described first direction is the direction that described grid extends to both sides；Described
Polysilicon gate polar region both sides are in the p-type doped region of outermost or n-type doping area offers the first contact hole, and described grid offers
Second contact hole, described second contact hole is used for being connected with gate metal, and described first contact hole is used for being connected with source metal.
2. the power transistor of static electrification discharge prevention diode structure according to claim 1 is it is characterised in that described
The doping type of grid is N-type.
3. the power transistor of static electrification discharge prevention diode structure according to claim 1 is it is characterised in that described
Polysilicon gate polar region is surrounded by described active area and termination environment, and three faces of wherein said polysilicon gate polar region are by described active area bag
Enclose, remaining one side is formed by described termination environment surrounds.
4. the power transistor of static electrification discharge prevention diode structure according to claim 3 is it is characterised in that each P
The width in type doped region and n-type doping area is all equal, and the direction of described width is the second direction perpendicular to described first direction.
5. the power transistor of static electrification discharge prevention diode structure according to claim 4 is it is characterised in that described
Grid first side adjacent with described termination environment outwardly makes the width of described grid be more than described p-type doped region and N-type
The width of doped region.
6. the power transistor of static electrification discharge prevention diode structure according to claim 5 is it is characterised in that described
Second contact hole is arranged at the region that described first side is outwardly formed.
7. the power transistor of static electrification discharge prevention diode structure according to claim 6 is it is characterised in that described
The cross section of the first contact hole is the strip extending along described second direction, and the cross section of described second contact hole is along described
The strip that first direction extends.
8. the power transistor of static electrification discharge prevention diode structure according to claim 5 is it is characterised in that described
Grid keeps concordant in relative second with the corresponding side of each p-type doped region and each n-type doping area with described first.
9. the power transistor of static electrification discharge prevention diode structure according to claim 1 is it is characterised in that described
The adjacent each pair p-type doped region of electro-static discharge protection diodes structure becomes a diode with n-type doping district's groups, described grid
The number of diodes of both sides is each 3～6 of every side.
10. the power transistor of static electrification discharge prevention diode structure according to claim 1 is it is characterised in that each
The doping content of described p-type doped region is less than the doping content in each described n-type doping area, and each described p-type doped region is described the
Size on one direction is more than each described n-type doping area size in said first direction.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115172457A (en) * | 2022-09-06 | 2022-10-11 | 江苏应能微电子有限公司 | Gate-source electrode protection structure of silicon carbide semiconductor field effect transistor and preparation method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115172457A (en) * | 2022-09-06 | 2022-10-11 | 江苏应能微电子有限公司 | Gate-source electrode protection structure of silicon carbide semiconductor field effect transistor and preparation method |
| CN115172457B (en) * | 2022-09-06 | 2024-05-03 | 江苏应能微电子股份有限公司 | Gate-source protection structure of silicon carbide semiconductor field effect transistor and preparation method |
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