CN108063137B - Transient voltage suppressor and manufacturing method thereof - Google Patents
Transient voltage suppressor and manufacturing method thereof Download PDFInfo
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- CN108063137B CN108063137B CN201711305304.9A CN201711305304A CN108063137B CN 108063137 B CN108063137 B CN 108063137B CN 201711305304 A CN201711305304 A CN 201711305304A CN 108063137 B CN108063137 B CN 108063137B
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- 230000001052 transient effect Effects 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 81
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 56
- 238000009792 diffusion process Methods 0.000 claims abstract description 53
- 238000000407 epitaxy Methods 0.000 claims abstract description 44
- 238000002347 injection Methods 0.000 claims abstract description 38
- 239000007924 injection Substances 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims description 24
- 230000000149 penetrating effect Effects 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000002457 bidirectional effect Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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Abstract
The invention relates to a transient voltage suppressor and a manufacturing method thereof. The transient voltage suppressor comprises an N-type substrate, a first groove and a second groove which are formed on the surface of the N-type substrate, a first P-type diffusion region and a second P-type diffusion region which are formed on the surface of the first groove and the surface of the second groove, an N-type epitaxy which is formed on the surface of the N-type substrate and the surfaces of the first P-type diffusion region and the second P-type diffusion region, a silicon oxide layer formed on the N-type epitaxy, two third grooves which penetrate through the N-type epitaxy and extend into the N-type substrate and two sides of the first P-type diffusion region, two fourth grooves which penetrate through the N-type epitaxy and extend into the N-type substrate and two sides of the second P-type diffusion region, silicon oxide positioned in the third groove and the fourth grooves, a first through hole corresponding to the first groove, a second through hole corresponding to the second groove, a P-type injection region which is formed on the surface of the N-type epitaxy and extends into the N-type substrate, an N-type injection region formed on the surface of the P-, And a P-type injection layer formed on the other side of the N-type substrate.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor device manufacturing, in particular to a transient voltage suppressor and a manufacturing method thereof.
[ background of the invention ]
The Transient Voltage Suppressor (TVS) is a solid semiconductor device specially designed for protecting sensitive semiconductor devices from transient voltage surge damage, and has the advantages of small clamping coefficient, small size, fast response, small leakage current, high reliability and the like, thus being widely applied to voltage transient and surge protection. The transient voltage suppressor with low capacitance is suitable for the protection device of the high-frequency circuit, because it can reduce the interference of the parasitic capacitance to the circuit and reduce the attenuation of the high-frequency circuit signal.
Electrostatic discharge (ESD) and other transient voltages that occur randomly in the form of some voltage surge are commonly found in a variety of electronic devices. As semiconductor devices increasingly tend to be miniaturized, high density, and multifunctional, electronic devices are increasingly susceptible to voltage surges, even fatal damage. Transient current spikes can be induced by various voltage surges from static discharge to lightning, and transient voltage suppressors are generally used for protecting sensitive circuits from surge impact. Based on different applications, the transient voltage suppressor can play a circuit protection role by changing the surge discharge path and the clamping voltage of the transient voltage suppressor. In order to save chip area and achieve higher surge resistance, the concept of trench transient voltage suppressors has been proposed and studied. The junction of the trench TVS is formed on the sidewall of the longitudinal trench, so that it has more effective junction area, i.e., stronger discharge capability, for the same chip area. The small package size of the trench transient voltage suppressor is critical to protect high-end chips.
The currently used transient voltage suppressor (such as a trench transient voltage suppressor) generally can only realize unidirectional protection, and if bidirectional protection is required, a plurality of transient voltage suppressors are required to be connected in series or in parallel, but the device area and the manufacturing cost are increased.
[ summary of the invention ]
Aiming at the defects of the existing method, the invention provides a transient voltage suppressor and a manufacturing method thereof.
A transient voltage suppressor comprises an N-type substrate, a first groove and a second groove which are formed on the surface of the N-type substrate, a first P-type diffusion region which is formed on the surface of the first groove and a second P-type diffusion region which is formed on the surface of the second groove, an N-type epitaxy which is formed on the surfaces of the N-type substrate and the first P-type diffusion region and the second P-type diffusion region, a silicon oxide layer which is formed on the N-type epitaxy, two third grooves which penetrate through the N-type epitaxy and extend to the N-type substrate and two sides of the first P-type diffusion region, two fourth grooves which penetrate through the N-type epitaxy and extend to the N-type substrate and two sides of the second P-type diffusion region, silicon oxide which is positioned in the third groove, silicon oxide which is positioned in the fourth grooves, a first through hole which corresponds to the first groove and penetrates through the silicon oxide layer, a second through hole which corresponds to the second groove and penetrates through the silicon oxide layer, The silicon oxide layer is formed on the surface of the N-type epitaxial layer and extends to a P-type injection region in the N-type substrate, the N-type injection region is formed on the surface of the P-type injection region, an opening penetrates through the silicon oxide layer and corresponds to the N-type injection region, and the P-type injection layer is formed on one side, far away from the N-type epitaxial layer, of the N-type substrate.
In one embodiment, the transient voltage suppressor further comprises a first metal layer formed on the silicon oxide layer and the silicon oxide and connected to the N-type epitaxy on the first trench and the second trench through the first via and the second via, and the first metal layer is further connected to the N-type implantation region through the opening.
In one embodiment, the transient voltage suppressor further comprises a second metal layer formed on the surface of the P-type injection layer away from the N-type substrate and connected with the N-type substrate.
In one embodiment, the P-type implant region is located between the two third trenches and the two fourth trenches.
In one embodiment, the depth of the third trench in the N-type substrate is less than the depth of the first trench, and the depth of the fourth trench in the N-type substrate is less than the depth of the second trench.
A method for manufacturing a transient voltage suppressor comprises the following steps:
providing an N-type substrate, forming an oxide layer on the N-type substrate, and etching the oxide layer and the N-type substrate by using a first photoresist as a mask to form a first groove and a second groove which penetrate through the oxide layer and extend into the N-type substrate;
performing P-type diffusion to form a first P-type diffusion region on the surface of the first groove and a second P-type diffusion region on the surface of the second groove;
removing the oxide layer, and forming an N-type epitaxy in the N-type substrate, the first groove and the second groove of the first P-type diffusion region and the second P-type diffusion region;
forming a silicon oxide layer on the surface of the N-type epitaxy, which is far away from the N-type substrate, two third grooves which penetrate through the silicon oxide layer and the N-type epitaxy and extend to the N-type substrate and two sides of the first P-type diffusion region are formed corresponding to two sides of the first P-type diffusion region, and two fourth grooves which penetrate through the silicon oxide layer and the N-type epitaxy and extend to the N-type substrate and two sides of the second P-type diffusion region are formed corresponding to two sides of the second P-type diffusion region;
filling the two third trenches and the two fourth trenches with silicon oxide;
etching the silicon oxide layer by using a second photoresist so as to form an opening penetrating through the silicon oxide layer, and performing P-type ion implantation on the N-type epitaxy by using the opening;
performing thermal annealing to form a P-type implantation region corresponding to the opening and extending from the N-type epitaxy to the N-type substrate; and
forming a first through hole penetrating through the silicon oxide layer and corresponding to the first trench and a second through hole penetrating through the silicon oxide layer and corresponding to the second trench;
and forming a P-type injection layer on the surface of the N-type substrate far away from the N-type epitaxy.
In one embodiment, the method further comprises the steps of:
and forming a first metal layer on the silicon oxide layer, wherein the first metal layer is connected with the N-type epitaxy through the first through hole and the second through hole, and the first metal layer is also connected with the N-type injection region through the opening.
In one embodiment, the N-type substrate is polished to be thinner on the surface far away from the N-type epitaxial surface to form the P-type injection layer, and a second metal layer is formed on the surface of the P-type injection layer far away from the N-type substrate.
In one embodiment, the P-type implant region is located between the two third trenches and the two fourth trenches.
In one embodiment, the depth of the third trench in the N-type substrate is less than the depth of the first trench, and the depth of the fourth trench in the N-type substrate is less than the depth of the second trench.
According to the transient voltage suppressor and the transient voltage suppressor obtained by the manufacturing method, on the basis of a traditional structure, a plurality of diodes are integrated together through improvement, two groups of diodes which are connected in series in an opposite direction reduce the capacitance of a device, and the reliability problem caused by large current in the using process is reduced due to the introduction of 1 unidirectional diode. The improved transient voltage suppressor can realize a two-way bidirectional protection function, and the protection characteristic and the reliability of the device are improved.
Furthermore, the P-type injection region can pass through multiple thermal processes, the junction depth is deep, the P-type concentration is low, the breakdown voltage of a PN junction is very high, and therefore the P-type injection region does not actually play a role in the working range of the device, an equivalent circuit is not shown, but the structure is arranged to rapidly drain the current without burning the system under certain extreme conditions (the temperature of the device is very high, and the thermal resistance coefficient of the device during normal working can be improved at the same time).
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic diagram of the structure of the transient movie suppressor of the present invention.
Fig. 2 is an equivalent circuit schematic diagram of the transient voltage suppressor of fig. 1.
Fig. 3 is a flow chart of a method of making the transient voltage suppressor of fig. 1.
Fig. 4-12 are schematic structural diagrams of steps of the manufacturing method shown in fig. 3.
[ description of main element symbols ]
A transient voltage suppressor 100; diodes 101, 102, 103, 104, 105; steps S1-S10
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram of a transient voltage suppressor 100 according to the present invention. The transient voltage suppressor 100 includes an N-type substrate, a first trench and a second trench formed on a surface of the N-type substrate, a first P-type diffusion region formed on a surface of the first trench and a second P-type diffusion region formed on a surface of the second trench, an N-type epitaxy formed on a surface of the N-type substrate and a surface of the first P-type diffusion region and the second P-type diffusion region, a silicon oxide layer formed on the N-type epitaxy, two third trenches penetrating through the N-type epitaxy and extending into the N-type substrate and to both sides of the first P-type diffusion region, two fourth trenches penetrating through the N-type epitaxy and extending into the N-type substrate and to both sides of the second P-type diffusion region, a silicon oxide in the third trenches, a silicon oxide in the fourth trenches, a first through hole corresponding to the first trench and penetrating through the silicon oxide layer, a second through hole corresponding to the second trench and penetrating through the silicon oxide layer, and a second through hole corresponding to the second trench and extending through the silicon oxide layer, The silicon oxide layer is formed on the surface of the N-type epitaxial layer and extends to a P-type injection region in the N-type substrate, the N-type injection region is formed on the surface of the P-type injection region, an opening penetrates through the silicon oxide layer and corresponds to the N-type injection region, and the P-type injection layer, a first metal layer and a second metal layer are formed on one side, far away from the N-type epitaxial layer, of the N-type substrate.
The first metal layer is formed on the silicon oxide layer and is connected with the N-type epitaxy on the first groove and the second groove through the first through hole and the second through hole, and the first metal layer is further connected with the N-type injection region through the opening. The second metal layer is formed on the surface, far away from the N-type substrate, of the P-type injection layer and connected with the N-type substrate.
Further, in this embodiment, the P-type implantation region is located between the two third trenches and the two fourth trenches. The depth of the third groove in the N-type substrate is smaller than that of the first groove, and the depth of the fourth groove in the N-type substrate is smaller than that of the second groove.
Referring to fig. 2, fig. 2 is an equivalent circuit diagram of the tvs 100 shown in fig. 1. The P-type injection region and the N-type substrate form a first diode 101, the N-type substrate and the P-type diffusion region in the first trench form a first diode 102, and the P-type diffusion region in the first trench and the N-type epitaxy in the first trench form a third diode 103; the N-type substrate also forms a fourth diode 104 with the P-type diffusion region in the second trench, which forms a fifth diode 105 with the N-type epitaxy in the second trench.
Referring to fig. 3-10, fig. 3 is a flowchart illustrating a method of manufacturing the tvs 100 shown in fig. 1, and fig. 4-10 are schematic structural diagrams illustrating steps of the method shown in fig. 3.
The method for manufacturing the transient voltage suppressor 100 includes the following steps S1-S10.
Step S1, referring to fig. 4, an N-type substrate is provided, an oxide layer is formed on the N-type substrate, and a first trench and a second trench penetrating the oxide layer and extending into the N-type substrate are formed by etching the oxide layer and the N-type substrate using a first photoresist as a mask. The etching may be dry etching. The material of the oxide layer may be silicon oxide.
In step S2, please refer to fig. 5, P-type diffusion is performed to form a first P-type diffusion region on the surface of the first trench and a second P-type diffusion region on the surface of the second trench.
In step S3, referring to fig. 6, the oxide layer is removed, and an N-type epitaxy is formed in the N-type substrate, the first trench and the second trench of the first and second P-type diffusion regions.
Step S4, please refer to fig. 7, a silicon oxide layer is formed on the surface of the N-type epitaxy away from the N-type substrate, two third trenches penetrating the silicon oxide layer and the N-type epitaxy and extending to the N-type substrate and the first P-type diffusion region are formed corresponding to two sides of the first P-type diffusion region, and two fourth trenches penetrating the silicon oxide layer and the N-type epitaxy and extending to two sides of the N-type substrate and the second P-type diffusion region are formed corresponding to two sides of the second P-type diffusion region. The third and fourth trenches may be formed by dry etching using a photoresist as a mask.
In step S5, please refer to fig. 8, the two third trenches and the two fourth trenches are filled with silicon oxide.
In step S6, referring to fig. 9, the silicon oxide layer is etched by using a second photoresist, so as to form an opening penetrating through the silicon oxide layer, and the N-type epitaxy is subjected to P-type ion implantation by using the opening. The etching may also be a dry etching.
In step S7, referring to fig. 10, a thermal anneal is performed to form a P-type implant region corresponding to the opening and extending from the N-type epitaxy into the N-type substrate.
In step S8, please refer to fig. 11, a first via penetrating through the silicon oxide layer and corresponding to the first trench and a second via penetrating through the silicon oxide layer and corresponding to the second trench are formed.
In step S9, referring to fig. 12, a first metal layer is formed on the silicon oxide layer, the first metal layer is connected to the N-type epitaxy through the first via and the second via, and the first metal layer is further connected to the N-type implantation region through the opening.
Step S10, referring to fig. 1, the N-type substrate is ground and thinned to form a P-type implantation layer, and a second metal layer is formed on the surface of the P-type implantation layer away from the N-type substrate.
According to the transient voltage suppressor 100 and the transient voltage suppressor 100 obtained by the manufacturing method, on the basis of a traditional structure, a plurality of diodes are integrated together through improvement, two groups of diodes which are connected in series in an opposite direction reduce the capacitance of a device, and the reliability problem caused by large current in the using process is reduced due to the introduction of 1 unidirectional diode. The improved transient voltage suppression 100 can realize a two-way bidirectional protection function, and the protection characteristic and the reliability of the device are improved.
Furthermore, the P-type injection region can pass through multiple thermal processes, the junction depth is deep, the P-type concentration is low, the breakdown voltage of a PN junction is very high, and therefore the P-type injection region does not actually play a role in the working range of the device, an equivalent circuit is not shown, but the structure is arranged to rapidly drain the current without burning the system under certain extreme conditions (the temperature of the device is very high, and the thermal resistance coefficient of the device during normal working can be improved at the same time).
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A transient voltage suppressor, characterized by: the transient voltage suppressor comprises an N-type substrate, a first groove and a second groove which are formed on the surface of the N-type substrate, a first P-type diffusion region which is formed on the surface of the first groove, a second P-type diffusion region which is formed on the surface of the second groove, N-type epitaxy which is formed on the surfaces of the N-type substrate and the first P-type diffusion region and the second P-type diffusion region, a silicon oxide layer which is formed on the N-type epitaxy, two third grooves which penetrate through the N-type epitaxy and extend into the N-type substrate and to two sides of the first P-type diffusion region, two fourth grooves which penetrate through the N-type epitaxy and extend to two sides of the N-type substrate and the second P-type diffusion region, silicon oxide which is positioned in the third grooves, silicon oxide which is positioned in the fourth grooves, a first through hole which corresponds to the first groove and penetrates through the silicon oxide layer, a second through hole which corresponds to the second groove and penetrates through the silicon oxide layer, The silicon oxide layer is formed on the surface of the N-type epitaxial layer and extends to a P-type injection region in the N-type substrate, the N-type injection region is formed on the surface of the P-type injection region, an opening penetrates through the silicon oxide layer and corresponds to the N-type injection region, and the P-type injection layer is formed on one side, far away from the N-type epitaxial layer, of the N-type substrate.
2. The transient voltage suppressor of claim 1, wherein: the transient voltage suppressor further comprises a first metal layer, wherein the first metal layer is formed on the silicon oxide layer and is in N-type epitaxial connection with the first groove and the second groove through the first through hole and the second through hole, and the first metal layer is further connected with the N-type injection region through the opening.
3. The transient voltage suppressor of claim 2, wherein: the transient voltage suppressor also comprises a second metal layer which is formed on the surface of the P-type injection layer far away from the N-type substrate.
4. The transient voltage suppressor of claim 1, wherein: the P-type injection region is positioned between the two third grooves and the two fourth grooves.
5. The transient voltage suppressor of claim 1, wherein: the depth of the third groove in the N-type substrate is smaller than that of the first groove, and the depth of the fourth groove in the N-type substrate is smaller than that of the second groove.
6. A method for manufacturing a transient voltage suppressor is characterized in that: the method comprises the following steps:
providing an N-type substrate, forming an oxide layer on the N-type substrate, and etching the oxide layer and the N-type substrate by using a first photoresist as a mask to form a first groove and a second groove which penetrate through the oxide layer and extend into the N-type substrate;
performing P-type diffusion to form a first P-type diffusion region on the surface of the first groove and a second P-type diffusion region on the surface of the second groove;
removing the oxide layer, and forming an N-type epitaxy in the N-type substrate, the first groove and the second groove of the first P-type diffusion region and the second P-type diffusion region;
forming a silicon oxide layer on the surface of the N-type epitaxy, which is far away from the N-type substrate, two third grooves which penetrate through the silicon oxide layer and the N-type epitaxy and extend to the N-type substrate and two sides of the first P-type diffusion region are formed corresponding to two sides of the first P-type diffusion region, and two fourth grooves which penetrate through the silicon oxide layer and the N-type epitaxy and extend to two sides of the N-type substrate and the second P-type diffusion region are formed corresponding to two sides of the second P-type diffusion region;
filling the two third trenches and the two fourth trenches with silicon oxide;
etching the silicon oxide layer by using a second photoresist so as to form an opening penetrating through the silicon oxide layer, and performing P-type ion implantation on the N-type epitaxy by using the opening;
performing thermal annealing to form a P-type implantation region corresponding to the opening and extending from the N-type epitaxy to the N-type substrate;
forming a first through hole penetrating through the silicon oxide layer and corresponding to the first trench and a second through hole penetrating through the silicon oxide layer and corresponding to the second trench; and
and forming a P-type injection layer on the surface of the N-type substrate far away from the N-type epitaxy.
7. The method of making a transient voltage suppressor according to claim 6, wherein: the method further comprises the steps of:
and forming a first metal layer on the silicon oxide layer, wherein the first metal layer is connected with the N-type epitaxy through the first through hole and the second through hole, and the first metal layer is also connected with the N-type injection region through the opening.
8. The method of making a transient voltage suppressor according to claim 7, wherein: grinding and thinning the surface of the N-type substrate far away from the N-type epitaxial surface to form the P-type injection layer, and forming a second metal layer on the surface of the P-type injection layer far away from the N-type substrate.
9. The method of making a transient voltage suppressor according to claim 6, wherein: the P-type injection region is positioned between the two third grooves and the two fourth grooves.
10. The method of making a transient voltage suppressor according to claim 6, wherein: the depth of the third groove in the N-type substrate is smaller than that of the first groove, and the depth of the fourth groove in the N-type substrate is smaller than that of the second groove.
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| CN108598078B (en) * | 2018-07-11 | 2024-06-04 | 上海艾为电子技术股份有限公司 | ESD protection circuit and electronic device |
| CN108987389B (en) * | 2018-07-24 | 2020-10-16 | 佛山市劲电科技有限公司 | Current protection chip and manufacturing method thereof |
| CN109244069B (en) * | 2018-09-19 | 2020-12-15 | 浙江昌新生物纤维股份有限公司 | Transient voltage suppressor and preparation method thereof |
| CN109326591B (en) * | 2018-10-08 | 2020-09-22 | 上海芯龙半导体技术股份有限公司 | Power device protection chip and manufacturing method thereof |
| CN113690231A (en) * | 2021-08-20 | 2021-11-23 | 安芯半导体技术(深圳)有限公司 | Surge protection chip and preparation method thereof |
| CN113690232A (en) * | 2021-08-24 | 2021-11-23 | 安芯半导体技术(深圳)有限公司 | Bidirectional electrostatic protection chip and preparation method thereof |
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| CN105702677A (en) * | 2014-12-09 | 2016-06-22 | 万国半导体股份有限公司 | TVS structure for high surge and low capacitance |
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| CN107301994A (en) * | 2017-07-12 | 2017-10-27 | 邓鹏飞 | Transient Voltage Suppressor and preparation method thereof |
| CN107301995A (en) * | 2017-07-12 | 2017-10-27 | 何春晖 | Transient Voltage Suppressor and preparation method thereof |
| CN107316864A (en) * | 2017-07-12 | 2017-11-03 | 孙丽芳 | Transient Voltage Suppressor and preparation method thereof |
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| CN105702677A (en) * | 2014-12-09 | 2016-06-22 | 万国半导体股份有限公司 | TVS structure for high surge and low capacitance |
| CN107017247A (en) * | 2015-12-22 | 2017-08-04 | 万国半导体股份有限公司 | Transient Voltage Suppressor with low breakdown voltage |
| CN107301994A (en) * | 2017-07-12 | 2017-10-27 | 邓鹏飞 | Transient Voltage Suppressor and preparation method thereof |
| CN107301995A (en) * | 2017-07-12 | 2017-10-27 | 何春晖 | Transient Voltage Suppressor and preparation method thereof |
| CN107316864A (en) * | 2017-07-12 | 2017-11-03 | 孙丽芳 | Transient Voltage Suppressor and preparation method thereof |
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