KR20130046261A - Manufacturing method of semiconductor device for esd protection and semiconductor device for esd protection manufactured by the method - Google Patents

Manufacturing method of semiconductor device for esd protection and semiconductor device for esd protection manufactured by the method Download PDF

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KR20130046261A
KR20130046261A KR1020110110742A KR20110110742A KR20130046261A KR 20130046261 A KR20130046261 A KR 20130046261A KR 1020110110742 A KR1020110110742 A KR 1020110110742A KR 20110110742 A KR20110110742 A KR 20110110742A KR 20130046261 A KR20130046261 A KR 20130046261A
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type semiconductor
region
type
pin diode
semiconductor device
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KR1020110110742A
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Korean (ko)
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KR101323143B1 (en
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김진형
선병수
임민정
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김진형
선병수
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • High Energy & Nuclear Physics (AREA)
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Abstract

PURPOSE: A method for manufacturing a semiconductor device for ESD protection and the semiconductor device manufactured by the method are provided to reduce capacitance by using an epi layer. CONSTITUTION: An epi layer is classified into a first area(220) and a second area(230). A second type semiconductor plug area(240) is formed in the second area of the epi layer. A second type semiconductor well(250) of high concentration is formed in the lower part of the plug region. A second type semiconductor bonding part is formed on the first area of the epi layer. A first type semiconductor bonding part is formed in the second semiconductor plug area.

Description

Manufacturing method of semiconductor device for electrostatic protection and electrostatic protection semiconductor device manufactured by the method {Manufacturing Method Of Semiconductor Device For ESD Protection and Semiconductor Device For ESD Protection Manufactured by The Method}

The present invention provides a method of manufacturing a semiconductor device for electrostatic protection and electrostatics produced by the method to protect the device from instantaneous high voltage ESD (Electrostatic Discharge) or high current surge (Surge) is located at the input and output terminals of the electronic device It relates to a semiconductor device for protection.

In general, various electronic devices and electrical devices are inevitably exposed to ESD signals or surge currents depending on the method of use or the environment. Therefore, ESD protection devices may be installed to protect devices or systems from such ESD signals or surge currents. do.

Conventionally, a zener diode is widely used as an ESD protection device using a semiconductor. In order to protect a device or a system from a high voltage ESD or a high current surge, the area of the zener diode needs to be large enough, and thus the capacitance of the zener diode is increased. It was also forced to have a high value.

Therefore, when the Zener diode is applied to an interface device that operates at a high speed, a signal delay occurs by limiting the response time when the interface device to be protected normally operates due to the high capacitance, thereby causing a malfunction. There was this.

To this end, devices with low capacitance, which can withstand high ESD and surges, have been developed, and ceramic TVS (Transient Voltage Suppressor) devices such as MOV (Metal Oxide Varistor) devices and Polymer TVS devices have been used. . However, ceramic-based TVS devices or Polymer TVS devices have low capacitance, but the clamping voltage, which is the residual voltage applied to the device or system after applying an ESD or surge signal, causes a very high leakage current. There has been a problem that the protection element causes the device or system to deteriorate.

The technical problem to be solved by the present invention is to configure a semiconductor device for electrostatic protection by using a silicon-based zener diode and a PIN diode together, a significantly lower capacitance and a higher ESD than when using a single zener diode The present invention provides a method for manufacturing an electrostatic protection semiconductor device capable of implementing a surge level, and an electrostatic protection semiconductor device manufactured by the method.

In order to solve the above technical problem, a method of manufacturing a semiconductor device for static electricity protection includes a first type semiconductor substrate having a large resistivity in a method of manufacturing a semiconductor device for static electricity protection, which is located at an input terminal of an electronic device and protects the electronic device from a transient voltage. A first step of forming an isolation region between devices perpendicular to the first type semiconductor epitaxial layer on the top to divide the first type semiconductor epitaxial layer into a first region and a second region; A second step of forming two second type semiconductor plug regions to a predetermined depth in the second region of the first type semiconductor epitaxial layer; Forming a high concentration of the second type semiconductor well at a lower end of the second type semiconductor plug region; A fourth step of forming a second type semiconductor junction by injecting a high concentration of a second type of semiconductor impurity to a predetermined depth into an upper surface of the first region of the first type semiconductor epitaxial layer; And a fifth step of forming a first type semiconductor junction by injecting a high concentration of first type semiconductor impurities to a predetermined depth between the second type semiconductor plug regions of the second region of the first type semiconductor epitaxial layer. A first PIN diode is formed in the first region, and a second PIN diode and a zener diode are formed in series in the second region.

In this case, the isolation region implants and diffuses a first type semiconductor impurity to the upper surface of the first type semiconductor substrate to form a vertical isolation layer. It is preferable to use a channeling effect generated due to vertical implantation of high energy ions.

In addition, the second type semiconductor well may be formed in a buried well type by a high energy ion implantation method, and be formed over the lower ends of two second type semiconductor plug regions.

The electrostatic protection semiconductor device manufactured by the above-described manufacturing method includes a first PIN diode, a second PIN diode connected in parallel with the first PIN diode, and a second PIN diode in parallel with the first PIN diode. And a Zener diode connected in series with the PIN diode.

The present invention implements an electrostatic protection semiconductor device with a PIN diode together with a zener diode which is frequently used as an electrostatic protection device, so that even when used in an input / output terminal of an interface device operating at a high speed, the operation of the interface device is very low. It has the advantage of protecting the interface devices from high voltage ESD or high current surge signals while having capacitance.

In addition, the present invention implements a PIN diode for determining the capacitance of the electrostatic protection semiconductor device using the epi layer of the semiconductor substrate having a low impurity concentration, thereby dramatically reducing the capacitance of the electrostatic protection semiconductor device as well as electrode pads. There is another advantage to eliminate the parasitic properties that occur in the back.

In addition, the present invention minimizes the high temperature diffusion process by using a high energy ion implantation process and by placing a Zener diode connected in series with the second PIN diode in the lower portion of the second PIN diode, a high ESD voltage and Another advantage is that surge current levels can be implemented to improve device characteristics.

1 is a process diagram of a method of manufacturing a semiconductor device for electrostatic protection according to an embodiment of the present invention.
2 is a structural diagram of a semiconductor device for electrostatic protection according to an embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a process diagram of a method of manufacturing a semiconductor device for electrostatic protection according to an embodiment of the present invention.

1, a method of manufacturing a semiconductor device for static electricity protection according to an embodiment of the present invention will be described. In this embodiment, for convenience, the first type semiconductor is a P-type semiconductor, and the second type semiconductor is an N-type semiconductor. It will be described as a challenge.

First, as shown in FIG. 1A, a P-type epitaxial layer 200 is formed on a P-type semiconductor substrate 100 having a large resistivity, so as to suppress leakage current between elements, an isolation layer with P-type impurities ( The P-type epitaxial layer 200 is formed into a first region 220 and a second region 230 by forming 210.

In this case, in order to diffuse the P-type impurity deeply to the P-type semiconductor substrate 100, the ion implantation is performed vertically without tilting during the high energy ion implantation, and the diffusion is formed by using the channeling effect generated at this time. By using a high energy ion implantation method using the channeling effect as described above, the high temperature thermal process is reduced, and impurities of the high concentration P-type semiconductor substrate 100 are diffused into the P-type epitaxial layer 200 to reduce the thickness of the epi layer and By preventing the increase in concentration, the capacitance of the device can be kept low and the breakdown voltage characteristic can be improved.

Next, as shown in FIG. 1B, the N-type impurities are ion-implanted and diffused into the second region 230 of the P-type epitaxial layer 200, and the two N-type plug regions 240 are fixed at a predetermined interval. To form. Thereafter, high energy ion implantation is performed to form a highly buried N-type well 250 having a continuous spread across both lower ends of the two N-type plug regions 240 (Fig. 1 (c)).

An N-type junction 270 is formed by implanting a high concentration of N-type impurities to a predetermined depth on the upper surface of the first region 220 of the P-type epitaxial layer 200 having a low impurity concentration. A P-type impurity 260 is formed on the upper surface of the P-type epitaxial layer 200 between the two N-type plug regions 240 to a certain depth to form a P-type junction 260 (Fig. 1 (d)). After forming the electrode pad by depositing a contact and a metal thin film, the device is completed.

In the electrostatic protection semiconductor device manufactured as described above, in the first region 220, the P-type semiconductor substrate 100, the P-type epitaxial layer 200, and the N-type junction 270 form the first PIN diode 10. In the second region 230, the P-type junction 260, the P-type epi layer 200, and the N-type plug region 240 form the second PIN diode 20, and the N-type well 250 and the P-type. The semiconductor substrate 100 forms the zener diode 30.

2 illustrates a structure diagram of the semiconductor device for static electricity protection configured as described above, wherein the second PIN diode 20 and the zener diode 30 are connected in series, and the first PIN diode 10 is a second PIN diode ( 20) and the Zener diode 30 are connected in parallel.

When the ESD signal by the negative charge is applied to the device, the ESD signal is bypassed through the first PIN diode 10, and when the ESD signal by the positive charge is applied in the breakdown region through the second PIN diode 20. The charge is transferred to the zener diode 30 in operation so that the ESD signal is absorbed.

In this case, the performance of the second PIN diode 20 is optimized by maintaining a predetermined distance between the P-type junction 260 and the N-type plug region 240 forming the carrier modulation region of the second PIN diode 20. This maximizes the ESD voltage and surge current levels.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. In addition, it is apparent that any person skilled in the art to which the present invention pertains may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

10-first PIN diode 20-second PIN diode
30-Zener Diodes
100-type 1 semiconductor substrate 200-type 1 semiconductor epi layer
210-isolation layer 220-first region
230-Second region 240-Second type semiconductor plug region
250-Type 2 semiconductor well 260-Type 1 semiconductor junction
270-Type 2 semiconductor junction

Claims (5)

In the manufacturing method of the electrostatic protection semiconductor device which is located at the input terminal of the electronic device to protect the electronic device from the transient voltage,
A first step of forming an isolation region between devices perpendicular to the first type semiconductor epitaxial layer on the first type semiconductor substrate having a high specific resistance to divide the first type semiconductor epitaxial layer into a first region and a second region;
A second step of forming two second type semiconductor plug regions to a predetermined depth in the second region of the first type semiconductor epitaxial layer;
Forming a high concentration of the second type semiconductor well at a lower end of the second type semiconductor plug region;
A fourth step of forming a second type semiconductor junction by injecting a high concentration of a second type of semiconductor impurity to a predetermined depth into an upper surface of the first region of the first type semiconductor epitaxial layer; And
A fifth step of forming a first type semiconductor junction by injecting a high concentration of first type semiconductor impurities to a predetermined depth between the second type semiconductor plug regions of the second region of the first type semiconductor epitaxial layer,
A first PIN diode is formed in the first region, and a second PIN diode and a zener diode are formed in series in the second region. The method of claim 1,
The isolation region is a method of manufacturing a semiconductor device for electrostatic protection, characterized in that to form a vertical isolation layer by implanting the first type semiconductor impurities to the upper surface of the first type semiconductor substrate. The method of claim 2,
The isolation layer is a method of manufacturing a semiconductor device for electrostatic protection, characterized in that formed using the channeling effect generated by the high energy ion implantation vertically. The method of claim 1,
The second type semiconductor well is formed in a buried well type by a high energy ion implantation method, and is formed over the lower ends of two second type semiconductor plug regions. It is prepared by the manufacturing method of any one of claims 1 to 4,
A first PIN diode, a second PIN diode connected in parallel with the first PIN diode, and a zener diode connected in series with the second PIN diode in parallel with the first PIN diode. Electrostatic protection semiconductor device, characterized in that formed.
KR1020110110742A 2011-10-27 2011-10-27 Manufacturing Method Of Semiconductor Device For ESD Protection and Semiconductor Device For ESD Protection Manufactured by The Method KR101323143B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101628754B1 (en) * 2015-02-17 2016-06-10 주식회사 시지트로닉스 Manufacturing method of dual mode protection device with symmetric bi-directional breakdown voltage

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* Cited by examiner, † Cited by third party
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US7538395B2 (en) * 2007-09-21 2009-05-26 Semiconductor Components Industries, L.L.C. Method of forming low capacitance ESD device and structure therefor
US7955941B2 (en) * 2008-09-11 2011-06-07 Semiconductor Components Industries, Llc Method of forming an integrated semiconductor device and structure therefor
KR101083001B1 (en) * 2010-12-23 2011-11-14 김진형 Semiconductor device for protection from static electricity and method for fabricating thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101628754B1 (en) * 2015-02-17 2016-06-10 주식회사 시지트로닉스 Manufacturing method of dual mode protection device with symmetric bi-directional breakdown voltage

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