CN106298773A - Integrated-type groove packet routing device and manufacture method thereof - Google Patents
Integrated-type groove packet routing device and manufacture method thereof Download PDFInfo
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- CN106298773A CN106298773A CN201510306442.3A CN201510306442A CN106298773A CN 106298773 A CN106298773 A CN 106298773A CN 201510306442 A CN201510306442 A CN 201510306442A CN 106298773 A CN106298773 A CN 106298773A
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Abstract
The invention provides a kind of integrated-type groove packet routing device and manufacture method thereof, method includes: etch multiple first groove in the silicon chip substrate of growth of doping silicon layer；Silicon oxide is filled in each first groove in multiple first grooves；The silicon chip filling silicon oxide etches multiple second groove；The silicon chip forming multiple second grooves is carried out ion implanting, and etches multiple 3rd groove；Polysilicon somatomedin layer is filled in each second groove and each 3rd groove；Dielectric layer prepares the first grommet on the position of corresponding each second groove, dielectric layer prepares the second grommet on the position of corresponding each 3rd groove；By multiple second grommet short circuits, and multiple first grommet are divided into two parts, respectively as the first input/output end port and the second input/output end port.By the program, device performance can be improved and reduce device cost.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to manufacture method and a kind of integrated-type groove packet routing device of a kind of integrated-type groove packet routing device.
Background technology
Transient Voltage Suppressor (TVS) is a kind of for protecting sensitive semiconductor device; make it exempt from transient voltage surge to destroy and specially designed solid-state semiconductor device; it has clamp, and coefficient is little, volume is little, response is fast, leakage current is little and high reliability, thus is widely used on voltage transient and carrying out surge protection.Low-capacitance TVS is applicable to the protection device of high-frequency circuit, because it can reduce the parasitic capacitance interference to circuit, reduces the decay of high-frequency circuit signal.Low di-cap needs at highly dope p-type Grown high resistivity
The transient voltage that static discharge (ESD) and some other voltage surge form occur at random, is typically found in various electronic device.Day by day tend to miniaturization, high density and multi-functional along with semiconductor device, electronic device becomes increasingly susceptible to the impact of voltage surge, even results in fatal harm.Various voltage surges can induce transient current spikes, Transient Voltage Suppressor (TVS) to be commonly used to protect sensitive circuit to be impacted by surge from static discharge to lightning etc..Based on different application, Transient Voltage Suppressor can play circuit protection effect by changing surge discharge path and the clamp voltage of self.In order to save chip area, and obtaining higher Surge handling capability, the concept of groove TVS has been suggested and studied.The junction of groove TVS is formed at the sidewall of longitudinal groove, and so, under identical chip area, it has more effectively junction area, the most higher discharge capability.The small package size of groove TVS is to being applied to protect high-end IC the most crucial.
The structural representation of at present conventional groove TVS is as shown in Figure 1: include P-type silicon sheet 102, N-type diffusion/injection zone 104, polysilicon/metal 106.
The most conventional groove TVS can only realize unidirectional protection, needs by multiple TVS serial or parallel connections together, to increase device area and manufacturing cost if needing to carry out bidirectional protective.
Accordingly, it would be desirable to a kind of new technical scheme, it is possible to while improving packet routing device performance, reduce the manufacturing cost of packet routing device.
Summary of the invention
The present invention is based on the problems referred to above, it is proposed that a kind of new technical scheme, reduces the manufacturing cost of packet routing device while improving packet routing device performance.
In view of this, the present invention proposes the manufacture method of a kind of integrated-type groove packet routing device, including: in the silicon chip substrate of growth of doping silicon layer, etch multiple first groove；Silicon oxide is filled in each first groove in the plurality of first groove；The silicon chip filling silicon oxide etches multiple second groove；The silicon chip forming the plurality of second groove is carried out ion implanting, and etches multiple 3rd groove；Polysilicon somatomedin layer is filled in each described second groove and each described 3rd groove；Described dielectric layer prepares the first grommet on the position of corresponding each described second groove, described dielectric layer prepares the second grommet on the position of corresponding each described 3rd groove；By multiple described second grommet short circuits, and multiple described first grommet are divided into two parts, respectively as the first input/output end port and the second input/output end port.
In this technical scheme, on the basis of conventional groove packet routing device, making two packet routing device be integrated together by process modification, device area is little, and technology difficulty is low, reduces device manufacturing cost.Packet routing device after improvement can realize bidirectional protective function, and protection feature and the reliability of device are obtained for lifting.
In technique scheme, it is preferable that described etch multiple first groove on the silicon chip of growth of doping silicon layer, including: growth of doping silicon layer in described silicon chip substrate；Described doped silicon layer grows the first mask material, to form the first mask pattern；The silicon chip forming the first mask pattern is performed etching, to form the plurality of first groove.
In technique scheme, preferably, described fill silicon oxide silicon chip on etch multiple second groove, including: remove described first mask material on the silicon chip of described formation the first mask pattern, and use silicon oxide as mask, described silicon chip to be performed etching, to form the plurality of second groove.
In technique scheme, it is preferable that the described silicon chip to forming the plurality of second groove carries out ion implanting, and etches multiple 3rd groove, including: the silicon chip forming the plurality of second groove is carried out ion implanting；Grown above silicon the second mask material after carrying out ion implanting, to form the second mask pattern；The silicon chip forming the second mask pattern is performed etching, to form multiple 3rd groove.
In technique scheme, preferably, described on described dielectric layer, prepare the first grommet on the position of corresponding each described second groove, described dielectric layer prepares the second grommet on the position of corresponding each described 3rd groove, including: growth regulation three mask material on dielectric layer, form the first contact hole with etching on the position of each described second groove corresponding on described dielectric layer, and on the position of corresponding each described 3rd groove, etching forms the second contact hole on described dielectric layer；Filler metal material in each described first contact hole and described second contact hole respectively, to obtain multiple first grommet and multiple second grommet, and the superficial growth dielectric layer of the silicon chip after filler metal material.
In technique scheme, it is preferable that described silicon chip substrate is N-type silicon chip substrate, described doped silicon layer is p-type doped silicon layer.
In technique scheme, it is preferable that described first mask material includes photoresist and/or dielectric layer.
In technique scheme, it is preferable that described second mask material and described 3rd mask material include photoresist.
In technique scheme, it is preferable that the bottom of described first groove is positioned in the range of described silicon chip substrate.
In technique scheme, it is preferable that the bottom of described second groove is positioned in the range of described doped silicon layer.
In technique scheme, it is preferable that described ion is N-type ion.
In technique scheme, it is preferable that when etching forms described second groove, lithographic method includes dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching etc., and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
In technique scheme, it is preferable that when etching forms described contact hole, lithographic method includes dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching etc., and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
According to a further aspect in the invention, additionally providing a kind of integrated-type groove packet routing device, described integrated-type groove packet routing device is made by the manufacture method of the integrated-type groove packet routing device as according to any one of technique scheme.
By above technical scheme, while improving packet routing device performance, reduce the manufacturing cost of packet routing device.
Accompanying drawing explanation
Fig. 1 shows the structural representation of groove-shaped packet routing device in correlation technique；
Fig. 2 shows the schematic flow sheet of the manufacture method of integrated-type groove packet routing device according to an embodiment of the invention；
Fig. 3 shows the equivalent circuit diagram of integrated-type groove packet routing device according to an embodiment of the invention；
Fig. 4 to Figure 13 shows integrated-type groove packet routing device according to an embodiment of the invention structural representation in the fabrication process.
Detailed description of the invention
In order to be more clearly understood that the above-mentioned purpose of the present invention, feature and advantage, with detailed description of the invention, the present invention is further described in detail below in conjunction with the accompanying drawings.It should be noted that in the case of not conflicting, the feature in embodiments herein and embodiment can be mutually combined.
Elaborate a lot of detail in the following description so that fully understanding the present invention; but; the present invention can implement to use other to be different from other modes described here, and therefore, protection scope of the present invention is not limited by following public specific embodiment.
Fig. 2 shows the schematic flow sheet of the manufacture method of integrated-type groove packet routing device according to an embodiment of the invention.
As in figure 2 it is shown, the manufacture method of the integrated-type groove packet routing device of embodiments of the invention, including: step 202, growth of doping silicon layer in silicon chip substrate；Step 204, grows the first mask material on described doped silicon layer, to form the first mask pattern；Step 206, performs etching the silicon chip forming the first mask pattern, to form multiple first groove；Step 208, fills silicon oxide in each first groove in the plurality of first groove；Step 210, removes the described mask material on the silicon chip of described formation the first mask pattern, and uses silicon oxide to perform etching described silicon chip as mask, to form multiple second groove；Step 212, carries out ion implanting to the silicon chip forming the plurality of second groove；Step 214, grown above silicon the second mask material after carrying out ion implanting, to form the second mask pattern；Step 216, performs etching the silicon chip forming the second mask pattern, to form multiple 3rd groove；Step 218, fills polysilicon in each described second groove and each described 3rd groove；Step 220, the grown above silicon dielectric layer after filling polysilicon；Step 222, growth regulation three mask material on dielectric layer, form the first contact hole with etching on the position of each described second groove corresponding on described dielectric layer, and on the position of corresponding each described 3rd groove, etching forms the second contact hole on described dielectric layer；Step 224, respectively filler metal material in each described first contact hole and described second contact hole, to obtain multiple first grommet and multiple second grommet；Step 226, the superficial growth dielectric layer of the silicon chip after filler metal material；Multiple described first grommet by multiple described second grommet short circuits, and are divided into two parts, respectively as the first input/output end port and the second input/output end port by step 228.
In this technical scheme, on the basis of conventional groove packet routing device, making two packet routing device be integrated together by process modification, device area is little, and technology difficulty is low, reduces device manufacturing cost.Packet routing device after improvement can realize bidirectional protective function, and protection feature and the reliability of device are obtained for lifting.
In technique scheme, it is preferable that described silicon chip substrate is N-type silicon chip substrate, described doped silicon layer is p-type doped silicon layer.
In technique scheme, it is preferable that described first mask material includes photoresist and/or dielectric layer.
In technique scheme, it is preferable that described second mask material and described 3rd mask material include photoresist.
In technique scheme, it is preferable that the bottom of described first groove is positioned in the range of described silicon chip substrate.
In technique scheme, it is preferable that the bottom of described second groove is positioned in the range of described doped silicon layer.
In technique scheme, it is preferable that described ion is N-type ion.
In technique scheme, it is preferable that when etching forms described second groove, lithographic method includes dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching etc., and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
In technique scheme, it is preferable that when etching forms described contact hole, lithographic method includes dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching etc., and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
Technical scheme is described in detail below in conjunction with Fig. 3 to Figure 13.
As it is shown on figure 3, integrated-type groove packet routing device makes two packet routing device be integrated together by process modification according to an embodiment of the invention, device area is little, and technology difficulty is low, reduces device manufacturing cost.Packet routing device after improvement can realize bidirectional protective function, and protection feature and the reliability of device are obtained for lifting.
The manufacture method of integrated-type groove packet routing device, specifically includes:
As shown in Figure 4, silicon chip 402 is prepared p-type doped silicon 404, it is possible to use extension, diffusion or injection mode are formed.
As it is shown in figure 5, make with photoresist or dielectric layer is as mask, silicon chip forms groove, in the range of channel bottom is positioned at N-type silicon substrate.
As shown in Figure 6, carry out using silicon oxide 406 to fill groove.
As it is shown in fig. 7, removal photoresist, using silicon oxide 406 as mask, dry etching forms groove, in the range of channel bottom is positioned at P-type silicon.
As shown in Figure 8, carry out N-type diffusion or ion implanting, in groove, form N-type diffusion/injection zone 408.
As it is shown in figure 9, make with photoresist as mask, etching forms groove.
As shown in Figure 10, in groove, polysilicon 410 is filled.
As shown in figure 11, preparing dielectric layer, make with photoresist as mask, dry etching forms contact hole, prepares metal material 412, filling contact hole.
As shown in figure 12, dielectric layer 414 is prepared on surface.
As shown in figure 13, the line schematic diagram of device is ultimately formed as shown in the figure.
Technical scheme is described in detail, by technical scheme, on the basis of conventional groove packet routing device above in association with accompanying drawing, two packet routing device are made to be integrated together by process modification, device area is little, and technology difficulty is low, reduces device manufacturing cost.Packet routing device after improvement can realize bidirectional protective function, and protection feature and the reliability of device are obtained for lifting.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (10)
1. the manufacture method of an integrated-type groove packet routing device, it is characterised in that bag
Include:
The silicon chip substrate of growth of doping silicon layer etches multiple first groove；
Silicon oxide is filled in each first groove in the plurality of first groove；
The silicon chip filling silicon oxide etches multiple second groove；
The silicon chip forming the plurality of second groove is carried out ion implanting, and etches multiple 3rd ditch
Groove；
Polysilicon somatomedin is filled in each described second groove and each described 3rd groove
Layer；
Described dielectric layer prepares the first grommet on the position of corresponding each described second groove,
The second grommet is prepared on the position of corresponding each described 3rd groove on described dielectric layer；
By multiple described second grommet short circuits, and multiple described first grommet are divided into two
Point, respectively as the first input/output end port and the second input/output end port.
The manufacturer of integrated-type groove packet routing device the most according to claim 1
Method, it is characterised in that described etch multiple first groove on the silicon chip of growth of doping silicon layer, bag
Include:
Growth of doping silicon layer in described silicon chip substrate；
Described doped silicon layer grows the first mask material, to form the first mask pattern；
The silicon chip forming the first mask pattern is performed etching, to form the plurality of first groove.
The manufacturer of integrated-type groove packet routing device the most according to claim 2
Method, it is characterised in that described fill silicon oxide silicon chip on etch multiple second groove, including:
Remove described first mask material on the silicon chip of described formation the first mask pattern, and use oxygen
Described silicon chip is performed etching by SiClx as mask, to form the plurality of second groove.
The manufacturer of integrated-type groove packet routing device the most according to claim 3
Method, it is characterised in that the described silicon chip to forming the plurality of second groove carries out ion implanting, and
Etch multiple 3rd groove, including:
The silicon chip forming the plurality of second groove is carried out ion implanting；
Grown above silicon the second mask material after carrying out ion implanting, to form the second mask figure
Shape；
The silicon chip forming the second mask pattern is performed etching, to form multiple 3rd groove.
The manufacturer of integrated-type groove packet routing device the most according to claim 4
Method, it is characterised in that described make on the position of corresponding each described second groove on described dielectric layer
Standby first grommet, prepares second on the position of corresponding each described 3rd groove on described dielectric layer
Grommet, including:
Growth regulation three mask material on dielectric layer, with on described dielectric layer corresponding each described second
On the position of groove, etching forms the first contact hole, and on described dielectric layer corresponding each described the
On the position of three grooves, etching forms the second contact hole；
Filler metal material in each described first contact hole and described second contact hole respectively, with
To multiple first grommet and multiple second grommet, and the surface of the silicon chip after filler metal material
Somatomedin is layer by layer.
The manufacturer of integrated-type groove packet routing device the most according to claim 2
Method, it is characterised in that described silicon chip substrate is N-type silicon chip substrate, described doped silicon layer is p-type
Doped silicon layer.
The manufacturer of integrated-type groove packet routing device the most according to claim 5
Method, it is characterised in that described first mask material includes photoresist and/or dielectric layer, described second
Mask material and described 3rd mask material include photoresist, when etching forms described second groove,
Lithographic method includes dry etching, and when etching forms described contact hole, lithographic method includes that dry method is carved
Erosion.
The manufacturer of integrated-type groove packet routing device the most according to claim 3
Method, it is characterised in that the bottom of described first groove is positioned in the range of described silicon chip substrate, described
The bottom of the second groove is positioned in the range of described doped silicon layer.
The manufacturer of integrated-type groove packet routing device the most according to claim 1
Method, it is characterised in that described ion is N-type ion.
10. an integrated-type groove packet routing device, it is characterised in that described integrated-type ditch
Groove packet routing device is by integrated-type groove transient state as claimed in any one of claims 1-9 wherein
The manufacture method of voltage suppressor device is made.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108063138A (en) * | 2017-12-14 | 2018-05-22 | 深圳市晶特智造科技有限公司 | Transient Voltage Suppressor and preparation method thereof |
| CN111584480A (en) * | 2020-04-17 | 2020-08-25 | 深圳方正微电子有限公司 | Semiconductor device and method for manufacturing the same |
| CN113937098A (en) * | 2021-09-22 | 2022-01-14 | 深圳市金誉半导体股份有限公司 | Electrostatic protection chip for rapid charging management system and preparation method thereof |
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| US20110212595A1 (en) * | 2010-02-26 | 2011-09-01 | Jerry Hu | Semiconductor device structure and methods of making |
| US20140167101A1 (en) * | 2012-12-19 | 2014-06-19 | Madhur Bobde | Tvs with low capacitance & forward voltage drop with depleted scr as steering diode |
| US20140319598A1 (en) * | 2013-04-24 | 2014-10-30 | Madhur Bobde | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) |
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| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| US20110212595A1 (en) * | 2010-02-26 | 2011-09-01 | Jerry Hu | Semiconductor device structure and methods of making |
| US20140167101A1 (en) * | 2012-12-19 | 2014-06-19 | Madhur Bobde | Tvs with low capacitance & forward voltage drop with depleted scr as steering diode |
| US20140319598A1 (en) * | 2013-04-24 | 2014-10-30 | Madhur Bobde | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108063138A (en) * | 2017-12-14 | 2018-05-22 | 深圳市晶特智造科技有限公司 | Transient Voltage Suppressor and preparation method thereof |
| CN108063138B (en) * | 2017-12-14 | 2020-12-22 | 嘉兴市龙锋市政建设有限公司 | Transient voltage suppressor and manufacturing method thereof |
| CN111584480A (en) * | 2020-04-17 | 2020-08-25 | 深圳方正微电子有限公司 | Semiconductor device and method for manufacturing the same |
| CN111584480B (en) * | 2020-04-17 | 2023-10-31 | 深圳方正微电子有限公司 | Semiconductor device and method for manufacturing the same |
| CN113937098A (en) * | 2021-09-22 | 2022-01-14 | 深圳市金誉半导体股份有限公司 | Electrostatic protection chip for rapid charging management system and preparation method thereof |
| CN113937098B (en) * | 2021-09-22 | 2023-03-24 | 深圳市金誉半导体股份有限公司 | Electrostatic protection chip for rapid charging management system and preparation method thereof |
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Effective date of registration: 20220720 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |