CN106298972A - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN106298972A CN106298972A CN201510306834.XA CN201510306834A CN106298972A CN 106298972 A CN106298972 A CN 106298972A CN 201510306834 A CN201510306834 A CN 201510306834A CN 106298972 A CN106298972 A CN 106298972A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 55
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 55
- 239000010703 silicon Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 230000001052 transient effect Effects 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 230000002457 bidirectional effect Effects 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 description 8
- 230000006872 improvement Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a kind of semiconductor device and manufacture method thereof, method includes: etch multiple groove in the silicon chip substrate of growth of doping silicon layer；The silicon chip forming the plurality of groove is carried out thermal oxide, in each described groove, fills silicon oxide, and prepare doped region；At the grown above silicon dielectric layer forming described doped region；Described dielectric layer is prepared multiple grommet, and on the lower surface of described silicon chip substrate, grows metal level；The plurality of grommet is divided into two parts, respectively as the first input/output end port and the second input/output end port, using described metal level as the 3rd input/output end port.By technical scheme, the manufacturing cost of packet routing device can be reduced while improving packet routing device performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of bidirectional transient voltage suppression
The manufacture method of device and a kind of semiconductor device.
Background technology
Transient Voltage Suppressor (TVS) is a kind of for protecting sensitive semiconductor device so that it is exempt from wink
State voltage surge destroys and specially designed solid-state semiconductor device, and it has clamp, and coefficient is little, volume
Little, response is fast, leakage current is little and high reliability, thus on voltage transient and carrying out surge protection
It is widely used.Low-capacitance TVS is applicable to the protection device of high-frequency circuit, because it can
To reduce the parasitic capacitance interference to circuit, reduce the decay of high-frequency circuit signal.Low di-cap
Need at highly dope p-type Grown high resistivity.
The transient voltage that static discharge (ESD) and some other voltage surge form occur at random,
It is typically found in various electronic device.Day by day tend to along with semiconductor device miniaturization, high density and
Multi-functional, electronic device becomes increasingly susceptible to the impact of voltage surge, even results in fatal wound
Evil.Various voltage surges can induce transient current spikes from static discharge to lightning etc., transient voltage
Suppressor (TVS) is commonly used to protect sensitive circuit to be impacted by surge.Should based on different
With, Transient Voltage Suppressor can play by changing surge discharge path and the clamp voltage of self
Circuit protection effect.In order to save chip area, and obtain higher Surge handling capability, groove
The concept of TVS has been suggested and studied.The junction of groove TVS is formed at the side of longitudinal groove
Wall, so, under identical chip area, it has more effectively junction area, the most higher electric discharge
Ability.The small package size of groove TVS is to being applied to protect high-end IC the most crucial.
The structural representation of at present conventional groove TVS is as shown in Figure 1: include P-type silicon sheet 102,
N-type diffusion/injection zone 104, polysilicon/metal 106.
The most conventional groove TVS can only realize unidirectional protection, needs if needing to carry out bidirectional protective
To increase device area and manufacturing cost by multiple TVS serial or parallel connections together.
Therefore, while improving device performance, how to reduce the manufacturing cost of device, become the most urgently
Problem to be solved.
Summary of the invention
The present invention is based on the problems referred to above, it is proposed that a kind of new technical scheme, is improving transient state electricity
The manufacturing cost of packet routing device is reduced while constraining device performance processed.
In view of this, the present invention proposes the manufacture method of a kind of semiconductor device, bag
Include: in the silicon chip substrate of growth of doping silicon layer, etch multiple groove；To forming the plurality of groove
Silicon chip carries out thermal oxide, fills silicon oxide, and prepare doped region in each described groove；In shape
Become the grown above silicon dielectric layer of described doped region；Described dielectric layer is prepared multiple grommet,
And on the lower surface of described silicon chip substrate, grow metal level；The plurality of grommet is divided into two
Point, respectively as the first input/output end port and the second input/output end port, described metal level is made
It it is the 3rd input/output end port.
In this technical scheme, on the basis of conventional groove packet routing device, changed by technique
Entering to make two packet routing device to be integrated together, device area is little, and technology difficulty is low, reduces
Device manufacturing cost.Packet routing device after improvement can realize two-path bidirectional defencive function,
Protection feature and the reliability of device are obtained for lifting.
In technique scheme, it is preferable that described etching in the silicon chip substrate of growth of doping silicon layer
Multiple grooves, including: growth of doping silicon layer on the upper surface of silicon chip substrate；At described doped silicon layer
Upper growth mask material, to form mask pattern；The silicon chip forming mask pattern is performed etching, with
Form multiple groove.
In technique scheme, it is preferable that described prepare multiple grommet on described dielectric layer,
Including: on described dielectric layer, grow mask material, form multiple medium holes with etching；Use metal
Each described medium holes filled by material, to obtain the plurality of grommet.
In technique scheme, it is preferable that use the mode of ion diffusion or ion implanting to prepare shape
Become described doped region.
In technique scheme, it is preferable that described silicon chip substrate is p-type silicon chip substrate, described in mix
Miscellaneous silicon layer is n-type doping silicon layer.
In technique scheme, it is preferable that described mask material includes photoresist.
In technique scheme, it is preferable that the bottom of described groove is positioned at the model of described silicon chip substrate
In enclosing.
In technique scheme, it is preferable that described ion is p-type ion.
In technique scheme, it is preferable that when etching forms described groove, lithographic method includes
Dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching
Deng, and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
In technique scheme, it is preferable that when etching forms described medium holes, lithographic method bag
Include dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching
Deng, and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
According to a further aspect in the invention, additionally provide a kind of semiconductor device, described
Semiconductor device is pressed down by the bidirectional transient voltage as according to any one of technique scheme
The manufacture method of device processed is made.
By above technical scheme, while improving packet routing device performance, reduce transient state electricity
The manufacturing cost of pressure suppression device.
Accompanying drawing explanation
Fig. 1 shows the structural representation of groove-shaped packet routing device in correlation technique；
Fig. 2 shows the manufacture of semiconductor device according to an embodiment of the invention
The schematic flow sheet of method；
Fig. 3 shows the equivalent circuit of semiconductor device according to an embodiment of the invention
Figure；
Fig. 4 to Figure 10 shows bidirectional transient voltage suppressor according to an embodiment of the invention
Part structural representation in the fabrication process.
Detailed description of the invention
In order to be more clearly understood that the above-mentioned purpose of the present invention, feature and advantage, below in conjunction with attached
The present invention is further described in detail by figure and detailed description of the invention.It should be noted that not
In the case of conflict, the feature in embodiments herein and embodiment can be mutually combined.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but,
The present invention can implement to use other to be different from other modes described here, therefore, and the present invention
Protection domain do not limited by following public specific embodiment.
Fig. 2 shows the manufacture of semiconductor device according to an embodiment of the invention
The schematic flow sheet of method.
As in figure 2 it is shown, the manufacture method of the semiconductor device of embodiments of the invention,
Including: step 202, the upper surface of silicon chip substrate grows the first doped silicon layer；Step 204,
Described doped silicon layer grows mask material, to form mask pattern；Step 206, covers formation
The silicon chip of film pattern performs etching, to form multiple groove；Step 208, to forming the plurality of ditch
The silicon chip of groove carries out thermal oxide, and fills silicon oxide in each described groove, removes and fills silicon oxide
After the silicon oxide of silicon chip surface；Step 210, uses the mode of ion diffusion or ion implanting to be formed
Doped region；Step 212, at the grown above silicon dielectric layer forming described doped region；Step
214, described dielectric layer grows mask material, forms multiple medium holes with etching；Step
216, use metal material to fill each described medium holes, to obtain multiple grommet, and described
Metal level is grown on the lower surface of silicon chip substrate；Step 218, is divided into two by the plurality of grommet
Part, respectively as the first input/output end port and the second input/output end port, by described metal level
As the 3rd input/output end port.
In this technical scheme, on the basis of conventional groove packet routing device, changed by technique
Entering to make two packet routing device to be integrated together, device area is little, and technology difficulty is low, reduces
Device manufacturing cost.Packet routing device after improvement can realize two-path bidirectional defencive function,
Protection feature and the reliability of device are obtained for lifting.
In technique scheme, it is preferable that described silicon chip substrate is p-type silicon chip substrate, described in mix
Miscellaneous silicon layer is n-type doping silicon layer.
In technique scheme, it is preferable that described mask material includes photoresist.
In technique scheme, it is preferable that the bottom of described groove is positioned at the model of described silicon chip substrate
In enclosing.
In technique scheme, it is preferable that described ion is p-type ion.
In technique scheme, it is preferable that when etching forms described groove, lithographic method includes
Dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching
Deng, and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
In technique scheme, it is preferable that when etching forms described medium holes, lithographic method bag
Include dry etching.
In this technical scheme, dry etching includes radiance, gaseous corrosion, plasma etching
Deng, and dry etching easily realizes automatization, processing procedure is not introduced into pollution, cleannes are high.
Fig. 3 shows the equivalent circuit of semiconductor device according to an embodiment of the invention
Figure.
As it is shown on figure 3, semiconductor device passes through technique according to an embodiment of the invention
Improvement makes five packet routing device be integrated together, and device area is little, and technology difficulty is low, subtracts
Little device manufacturing cost.Packet routing device after improvement can realize bidirectional protective function, device
Protection feature and the reliability of part are obtained for lifting.
The manufacture method of semiconductor device, specifically includes:
As shown in Figure 4, n-type doping silicon 404 is prepared in P-type silicon sheet 402 front, it is possible to use outer
Prolonging, diffusion or injection mode are formed.
As it is shown in figure 5, make with photoresist as mask, dry etching forms groove.
As shown in Figure 6, carrying out thermal oxide and use silicon oxide 408 to fill groove, etching removes surface
Silicon oxide, retains the silicon oxide in groove.
As it is shown in fig. 7, use diffusion or injection mode to form p-type doped region 406.
As shown in Figure 8, dielectric material 410 is prepared.
As it is shown in figure 9, make, with photoresist as mask, to form medium holes, filler metal on surface.
Metal level 412 is prepared at silicon chip back side.
Ultimately form the line schematic diagram of device as shown in Figure 10.
Technical scheme is described in detail, by the technical side of the present invention above in association with accompanying drawing
Case, on the basis of conventional groove packet routing device, makes five transient voltages by process modification
Suppression device is integrated together, and device area is little, and technology difficulty is low, reduces device manufacturing cost.
Packet routing device after improvement can realize two-path bidirectional defencive function, the protection feature of device and
Reliability is obtained for lifting.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for
For those skilled in the art, the present invention can have various modifications and variations.All essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. made, should be included in the present invention
Protection domain within.
Claims (10)
1. the manufacture method of a semiconductor device, it is characterised in that including:
The silicon chip substrate of growth of doping silicon layer etches multiple groove；
The silicon chip forming the plurality of groove is carried out thermal oxide, in each described groove, fills oxidation
Silicon, and prepare doped region；
At the grown above silicon dielectric layer forming described doped region；
Described dielectric layer is prepared multiple grommet, and grows on the lower surface of described silicon chip substrate
Metal level；
The plurality of grommet is divided into two parts, respectively as the first input/output end port and
Two input/output end ports, using described metal level as the 3rd input/output end port.
The manufacture method of semiconductor device the most according to claim 1, it is special
Levy and be, described in the silicon chip substrate of growth of doping silicon layer, etch multiple groove, including:
Growth of doping silicon layer on the upper surface of silicon chip substrate；
Described doped silicon layer grows mask material, to form mask pattern；
The silicon chip forming mask pattern is performed etching, to form multiple groove.
The manufacture method of semiconductor device the most according to claim 1, it is special
Levy and be, described on described dielectric layer, prepare multiple grommet, including:
Described dielectric layer grows mask material, forms multiple medium holes with etching；
Metal material is used to fill each described medium holes, to obtain the plurality of grommet.
The manufacture method of semiconductor device the most according to claim 1, it is special
Levy and be,
The mode using ion diffusion or ion implanting prepares the described doped region of formation.
The manufacture method of semiconductor device the most according to claim 1, it is special
Levying and be, described silicon chip substrate is p-type silicon chip substrate, and described doped silicon layer is n-type doping silicon
Layer.
The manufacture method of semiconductor device the most according to claim 1, it is special
Levying and be, described mask material includes photoresist.
The manufacture method of semiconductor device the most according to claim 1, it is special
Levying and be, the bottom of described groove is positioned in the range of described silicon chip substrate.
The manufacture method of semiconductor device the most according to claim 4, it is special
Levying and be, described ion is p-type ion.
The manufacture method of semiconductor device the most according to claim 3, it is special
Levying and be, when etching forms described groove, lithographic method includes dry etching, and
When etching forms described medium holes, lithographic method includes dry etching.
10. a semiconductor device, it is characterised in that described bidirectional transient voltage presses down
Device processed is by the manufacture of semiconductor device as claimed in any one of claims 1-9 wherein
Method is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510306834.XA CN106298972B (en) | 2015-06-05 | 2015-06-05 | Semiconductor device and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510306834.XA CN106298972B (en) | 2015-06-05 | 2015-06-05 | Semiconductor device and its manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| CN106298972A true CN106298972A (en) | 2017-01-04 |
| CN106298972B CN106298972B (en) | 2019-11-08 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109950326A (en) * | 2019-04-15 | 2019-06-28 | 深圳市槟城电子有限公司 | A kind of bilateral diode and preparation method thereof, overvoltage protection |
| CN109950326B (en) * | 2019-04-15 | 2024-05-17 | 马鞍山市槟城电子有限公司 | Bidirectional diode, manufacturing method thereof and overvoltage protection device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| CN103840013A (en) * | 2014-01-26 | 2014-06-04 | 上海韦尔半导体股份有限公司 | Bidirectional TVS and manufacturing method of bidirectional TVS |
| US20140167101A1 (en) * | 2012-12-19 | 2014-06-19 | Madhur Bobde | Tvs with low capacitance & forward voltage drop with depleted scr as steering diode |
-
2015
- 2015-06-05 CN CN201510306834.XA patent/CN106298972B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306649A (en) * | 2011-08-24 | 2012-01-04 | 浙江大学 | Bidirectional dual-channel transient voltage suppressor (TVS) |
| US20140167101A1 (en) * | 2012-12-19 | 2014-06-19 | Madhur Bobde | Tvs with low capacitance & forward voltage drop with depleted scr as steering diode |
| CN103840013A (en) * | 2014-01-26 | 2014-06-04 | 上海韦尔半导体股份有限公司 | Bidirectional TVS and manufacturing method of bidirectional TVS |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109950326A (en) * | 2019-04-15 | 2019-06-28 | 深圳市槟城电子有限公司 | A kind of bilateral diode and preparation method thereof, overvoltage protection |
| CN109950326B (en) * | 2019-04-15 | 2024-05-17 | 马鞍山市槟城电子有限公司 | Bidirectional diode, manufacturing method thereof and overvoltage protection device |
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| CN106298972B (en) | 2019-11-08 |
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Effective date of registration: 20220720 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |