CN108987389B - Current protection chip and manufacturing method thereof - Google Patents
Current protection chip and manufacturing method thereof Download PDFInfo
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- CN108987389B CN108987389B CN201810816967.5A CN201810816967A CN108987389B CN 108987389 B CN108987389 B CN 108987389B CN 201810816967 A CN201810816967 A CN 201810816967A CN 108987389 B CN108987389 B CN 108987389B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
The invention provides a current protection chip and a manufacturing method thereof, wherein the current protection chip comprises the following steps: a substrate of a first conductivity type; a first epitaxial layer of a second conductivity type; a first buried layer of a first conductivity type and a second buried layer of a second conductivity type formed in the first epitaxial layer; the second epitaxial layer of the first conduction type is formed on the surface of the first epitaxial layer; a first implantation region of a second conductivity type and a second implantation region of a first conductivity type formed on the surface of the second epitaxial layer, the second implantation region being located in the first implantation region; a polysilicon layer connected to the first implanted region and the first buried layer, respectively; the dielectric layer is formed on the upper surface of the second epitaxial layer; the first electrode comprises a first part penetrating through the dielectric layer and extending to the second injection region and a second part formed on the surface of the dielectric layer; and the second electrode is formed on the lower surface of the substrate and is connected with the substrate. The invention can improve the performance of the device and reduce the cost of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a current protection chip and a manufacturing method thereof.
Background
The current protection chip is a solid semiconductor device specially designed for protecting sensitive semiconductor devices from transient voltage surge damage, and has the advantages of small clamping coefficient, small volume, fast response, small leakage current, high reliability and the like, so that the current protection chip is widely applied to voltage transient and surge protection. The low-capacitance current protection chip is suitable for a protection device of a high-frequency circuit, because the interference of parasitic capacitance to the circuit can be reduced, and the attenuation of signals of the high-frequency circuit can be reduced.
Electrostatic discharge, and other transient voltages that occur randomly in the form of some voltage surge, are commonly present in a variety of electronic devices. As semiconductor devices increasingly tend to be miniaturized, high density, and multifunctional, electronic devices are increasingly susceptible to voltage surges, even fatal damage. The protection chip can induce transient current peak current from various voltage surges from static discharge to lightning and the like, and is generally used for protecting sensitive circuits from surge. Based on different applications, the current protection chip can play a circuit protection role by changing the surge discharge path and the clamping voltage of the current protection chip.
At present, if bidirectional protection is required, a plurality of current protection chips need to be connected in series or in parallel, so that the area of a device and the manufacturing cost are increased.
Disclosure of Invention
The invention provides a current protection chip and a manufacturing method thereof based on the above problems, so that the performance of the current protection chip is improved, and the manufacturing cost of the current protection chip is reduced.
In view of this, an aspect of the present invention provides a current protection chip, including:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type grown on the upper surface of the substrate;
the first buried layer of the first conductivity type and the second buried layer of the second conductivity type are formed in the first epitaxial layer, at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
the second epitaxial layer of the first conductivity type is formed on the upper surface of the first epitaxial layer;
a first implanted region of a second conductivity type and a second implanted region of the first conductivity type formed on the upper surface of the second epitaxial layer, the second implanted region being located within the first implanted region;
a polysilicon layer connected to the first implanted region and the first buried layer, respectively;
the dielectric layer is formed on the upper surface of the second epitaxial layer;
the first electrode comprises a first part penetrating through the dielectric layer and extending to the second injection region and a second part formed on the surface of the dielectric layer;
and the second electrode is formed on the lower surface of the substrate and is connected with the substrate.
Further, the doping concentration of the first buried layer is higher than the doping concentration of the second epitaxial layer.
Further, the second buried layer is located at a lower side of the first implanted region.
Furthermore, one end of the polysilicon layer penetrates through the second epitaxial layer and extends to the first buried layer, and the other end of the polysilicon layer extends from the surface of the second epitaxial layer to the first injection region through the dielectric layer.
Further, the first buried layer includes a first sub buried layer and a second sub buried layer respectively disposed at both sides of the second buried layer, and the polycrystalline silicon layer includes a first polycrystalline silicon layer connected to the first sub buried layer and a second polycrystalline silicon layer connected to the second sub buried layer.
Another aspect of the embodiments of the present invention provides a method for manufacturing a current protection chip, where the method includes:
growing a first epitaxial layer of a second conductivity type on the upper surface of a substrate of the first conductivity type;
forming a first buried layer of a first conductivity type and a second buried layer of a second conductivity type in the first epitaxial layer, wherein at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer;
forming a first trench penetrating the second epitaxial layer and extending to the first buried layer;
forming a first injection region of a second conductivity type and a second injection region of a first conductivity type on the upper surface of the second epitaxial layer, and forming the first injection region in the second injection region;
forming a polycrystalline silicon layer connected with the first buried layer in the first groove, and connecting the polycrystalline silicon layer with the first injection region;
forming a dielectric layer on the upper surface of the second epitaxial layer;
forming a first electrode, wherein the first electrode comprises a first part which penetrates through the dielectric layer and extends to the second injection region and a second part which is formed on the surface of the dielectric layer;
and forming a second electrode connected with the substrate on the lower surface of the substrate.
Further, the doping concentration of the first buried layer is higher than the doping concentration of the second epitaxial layer.
Further, the second buried layer is disposed at a lower side of the first implantation region.
Furthermore, one end of the polysilicon layer penetrates through the second epitaxial layer and extends to the first buried layer, and the other end of the polysilicon layer extends from the surface of the second epitaxial layer to the first injection region through the dielectric layer.
Further, the first buried layer includes a first sub buried layer and a second sub buried layer respectively disposed at both sides of the second buried layer, and the polycrystalline silicon layer includes a first polycrystalline silicon layer connected to the first sub buried layer and a second polycrystalline silicon layer connected to the second sub buried layer.
The technical scheme of the embodiment of the invention is that a first epitaxial layer of a second conduction type is grown on the upper surface of a substrate of a first conduction type; forming a first buried layer of a first conductivity type and a second buried layer of a second conductivity type in the first epitaxial layer, wherein at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer; forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer; forming a first trench penetrating the second epitaxial layer and extending to the first buried layer; forming a first injection region of a second conductivity type and a second injection region of a first conductivity type on the upper surface of the second epitaxial layer, and forming the first injection region in the second injection region; forming a polycrystalline silicon layer connected with the first buried layer in the first trench, and connecting the polycrystalline silicon layer with the first injection region; forming a dielectric layer on the upper surface of the second epitaxial layer; forming a first electrode, wherein the first electrode comprises a first part which penetrates through the dielectric layer and extends to the second injection region and a second part which is formed on the surface of the dielectric layer; forming a second electrode connected with the substrate on the lower surface of the substrate; the technical scheme of the invention reduces the difficulty of the device manufacturing process, greatly reduces the parasitic capacitance and improves the protection characteristic and the reliability of the device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for manufacturing a current protection chip according to an embodiment of the present invention;
fig. 2 to fig. 8 are schematic structural diagrams illustrating steps of a method for manufacturing a current protection chip according to an embodiment of the present invention;
fig. 9 is an equivalent circuit diagram of a current protection chip structure according to an embodiment of the present invention;
in the figure: 1. a substrate; 2. a first epitaxial layer; 3. a first buried layer; 4. a second buried layer; 5. a second epitaxial layer; 6. a first trench; 7. a first implanted region; 8. a second implanted region; 9. a polysilicon layer; 10. a dielectric layer; 11. a first electrode; 111. a first portion; 112. a second portion; 12. a second electrode; a1, a first diode; b1, a second diode; c1, a third diode; d1, fourth diode; a2, fifth diode; b2, sixth diode; c2, a seventh diode.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing methods and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The following describes the manufacturing method of the current protection chip in detail with reference to the accompanying drawings.
A current protection chip and a method for manufacturing the same according to an embodiment of the present invention are described in detail with reference to fig. 1 to 8.
An embodiment of the present invention provides a method for manufacturing a current protection chip, and as shown in fig. 1, a flow diagram of the method for manufacturing the current protection chip provided in the embodiment of the present invention includes:
step S01: a first epitaxial layer 2 of a second conductivity type is grown on the upper surface of a substrate 1 of a first conductivity type.
Step S02: forming a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type in the first epitaxial layer 2, wherein at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2.
Step S03: a second epitaxial layer 5 of the first conductivity type is formed on the upper surface of the first epitaxial layer 2.
Step S04: a first trench 6 is formed through the second epitaxial layer 5 and extending to the first buried layer 3.
Step S05: a first implanted region 7 of the second conductivity type and a second implanted region 8 of the first conductivity type are formed on the upper surface of the second epitaxial layer 5, and the first implanted region 7 is formed in the second implanted region 8.
Step S06: a polysilicon layer 9 connected to the first buried layer 3 is formed in the first trench 6, and the polysilicon layer 9 is connected to the first implanted region 7.
Step S07: a dielectric layer 10 is formed on the upper surface of the second epitaxial layer 5.
Step S08: forming a first electrode 11, wherein the first electrode 11 comprises a first part 111 penetrating through the dielectric layer 10 and extending to the second injection region 8 and a second part 112 formed on the surface of the dielectric layer 10; a second electrode 12 connected to the substrate 1 is formed on the lower surface of the substrate 1.
Specifically, the first conductive type is one of P-type doping and N-type doping, and the second conductive type is the other of P-type doping and N-type doping.
For convenience of description, it is specifically stated herein that: the first conductivity type may be N-type doped, such that the second conductivity type is P-type doped; the first conductivity type may also be P-type doped, whereby the second conductivity type is N-type doped. It is to be understood that, when the first conductivity type is N-type doping and the second conductivity type is P-type doping, the substrate 1, the second epitaxial layer 5, the first buried layer 3 and the second implanted region 8 are all N-type doping, and the first epitaxial layer 2, the second buried layer 4 and the first implanted region 7 are all P-type epitaxial layers. When the first conductivity type is P-type doping and the second conductivity type is N-type doping, the substrate 1, the second epitaxial layer 5, the first buried layer 3 and the second implanted region 8 are all P-type doping, and the first epitaxial layer 2, the second buried layer 4 and the first implanted region 7 are all N-type epitaxial layers. In the following embodiments, the first conductive type is an N-type doping, and the second conductive type is a P-type doping, which are not limited to the above description.
Specifically, the P-type substrate 1 and the P-type epitaxy belong to a P-type semiconductor, and the N-type substrate 1 and the N-type epitaxy belong to an N-type semiconductor. The P-type semiconductor is a silicon wafer doped with trivalent elements, such as boron elements, indium elements, aluminum elements or any combination of the three. The N-type semiconductor is a silicon wafer doped with pentavalent elements, such as phosphorus or arsenic or any combination of the phosphorus and the arsenic.
Referring to fig. 2, step S01 is executed, specifically: a first epitaxial layer 2 of a second conductivity type is grown on the upper surface of a substrate 1 of a first conductivity type. It should be noted that the substrate 1 is a carrier in an integrated circuit, the substrate 1 plays a role of support, and the substrate 1 also participates in the operation of the integrated circuit. The substrate 1 may be a silicon substrate, a sapphire substrate, a silicon carbide substrate, or even a silicon substrate, and preferably, the substrate 1 is a silicon substrate because the silicon substrate has the characteristics of low cost, large size, and electrical conductivity, so that the edge effect is avoided, and the yield can be greatly improved. The method for growing the first epitaxial layer 2 of the second conductivity type on the upper surface of the substrate 1 of the first conductivity type is not limited to a fixed method, and the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by using epitaxial growth, or the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by ion implantation and/or diffusion. Further, the epitaxial growth may be used to form the first epitaxial layer 2 on the upper surface of the substrate 1, and the first epitaxial layer 2 may also be formed on the upper surface of the substrate 1 by ion implantation and/or diffusion of phosphorus or arsenic or any combination of the two. In particular, the method of epitaxy or diffusion comprises a deposition process. In some embodiments of the present invention, the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by using a deposition process, for example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, and sputtering. Preferably, the first epitaxial layer 2 is formed on said substrate 1 using chemical vapor deposition, which comprises a vapor phase epitaxy process. In production, chemical vapor deposition mostly uses a vapor phase epitaxy process, the first epitaxial layer 2 is formed on the upper surface of the substrate 1 by using the vapor phase epitaxy process, and the vapor phase epitaxy process can improve the perfection of a silicon material, improve the integration level of a device, prolong the minority carrier lifetime and reduce the leakage current of a storage unit.
Referring to fig. 3, step S02 is executed, specifically: forming a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type in the first epitaxial layer 2, wherein at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2. The first buried layer 3 and the second buried layer 4 may be formed by epitaxial growth, and may also be formed by ion implantation and/or diffusion. Further, the first buried layer 3 may be formed by epitaxial growth, and may be formed by ion implantation and/or diffusion of phosphorus or arsenic or any combination of the two. Similarly, the second buried layer 4 may be formed by epitaxial growth, or may be formed by ion implantation and/or diffusion of a boron element, an indium element, an aluminum element, or any combination thereof. Preferably, the first buried layer 3 and the second buried layer 4 may be formed using an ion implantation method, and the formation of the first buried layer 3 and the second buried layer 4 by ion implantation enables precise control of the total dose, depth distribution, and surface uniformity of impurities, prevents re-diffusion of original impurities, and the like, and may implement a self-aligned technique to reduce a capacitive effect. In some embodiments of the present invention, at least a portion of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed to the upper surface of the first epitaxial layer 2, that is, the upper surfaces of the first buried layer 3 and the second buried layer 4 are exposed to the first epitaxial layer 2.
Referring to fig. 4, step S03 is executed, specifically: a second epitaxial layer 5 of the first conductivity type is formed on the upper surface of the first epitaxial layer 2. The manner of forming the second epitaxial layer 5 of the first conductivity type on the upper surface of the first epitaxial layer 2 is not limited to a fixed manner, and the second epitaxial layer 5 may be formed by using an epitaxy, diffusion and/or implantation method, and specifically, the epitaxy or diffusion method includes a deposition process. Further, the second epitaxial layer 5 may be formed using methods of epitaxy, diffusion and/or implantation of elemental phosphorus or elemental arsenic or any combination of the two. In some embodiments of the present invention, the second epitaxial layer 5 is formed on the upper surface of the first epitaxial layer 2 using a deposition process, for example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering. The chemical vapor deposition comprises a vapor phase epitaxy process, preferably, the second epitaxial layer 5 is formed on the upper surface of the first epitaxial layer 2 by using the vapor phase epitaxy process, the perfectness of the silicon material can be improved by the vapor phase epitaxy process, the integration level of a device is improved, the minority carrier lifetime is prolonged, and the leakage current of the storage unit is reduced. The second epitaxial layer 5 covers the upper surface of the first epitaxial layer 2 and has a certain thickness.
Further, the doping concentration of the first buried layer 3 is different from the doping concentration of the second epitaxial layer 5. Preferably, the doping concentration of the first buried layer 3 is higher than that of the second epitaxial layer 5, and the first buried layer 3 is heavily doped, so that the resistivity of the first buried layer 3 is lower than that of the second epitaxial layer 5, and current flows along the buried layer with low resistivity to the lower side of the first epitaxial layer 2 without overflowing into the second epitaxial layer 5, thereby forming parallel branches.
Referring to fig. 5, step S04 is executed to specifically: a first trench 6 is formed through the second epitaxial layer 5 and extending to the first buried layer 3. In some embodiments of the present invention, a mask material, specifically, a first photoresist, is prepared on the upper surface of the second epitaxial layer 5, a first trench 6 extending through the second epitaxial layer 5 to the first buried layer 3 is formed on the first photoresist layer by etching, and then the first photoresist is removed. The etching method comprises dry etching and wet etching, preferably, the used etching method is dry etching, the dry etching comprises light volatilization, gas phase corrosion, plasma corrosion and the like, and the dry etching is easy to realize automation, pollution is not introduced in the treatment process, and the cleanliness is high. In some embodiments of the present invention, the bottom surface of the first trench 6 is connected to the first buried layer 3, for example, the bottom surface of the first trench 6 may extend into the first buried layer 3, and the bottom surface of the first trench 6 may also be connected to the upper surface of the first buried layer 3, so as to ensure that the bottom surface of the first trench 6 is in contact with the first buried layer 3. Regarding the shape of the first trench 6, those skilled in the art can select trenches with different shapes according to the electrical performance of the device, and the shape of the first trench 6 may be a rectangular trench, a square trench, a U-shaped trench, or even a ball bottom trench, etc.
Referring to fig. 6, step S05 is executed to specifically: a first implanted region 7 of the second conductivity type and a second implanted region 8 of the first conductivity type are formed on the upper surface of the second epitaxial layer 5, and the first implanted region 7 is formed in the second implanted region 8. In some embodiments of the present invention, a mask material, specifically a second photoresist, is prepared on the upper surface of the second epitaxial layer 5, and a first implanted region 7 of the second conductivity type and the second implanted region 8 of the first conductivity type are respectively formed in the second epitaxial layer 5 by a photolithography method on the second photoresist layer, where the first implanted region 7 is located in the second implanted region 8. And forming a first implanted region 7 of the second conductivity type and a second implanted region 8 of the first conductivity type on the upper surface of the second photoresist layer by using an ion implantation and/or diffusion method, and removing the second photoresist layer. Further, a first implanted region 7 of the second conductivity type is formed on the upper surface of the second photoresist layer by ion implantation and/or diffusion of boron element, indium element, aluminum element, or any combination of the three; and simultaneously, forming a second implanted region 8 of the first conductivity type on the upper surface of the second photoresist layer by using ion implantation and/or diffusion of phosphorus element or arsenic element or any combination of the phosphorus element and the arsenic element, and finally removing the second photoresist layer.
Further, the second buried layer 4 is disposed on the lower side of the first implanted region 7. Preferably, the second buried layer 4 is disposed directly below the first implanted region 7, and the second implanted region 8 is disposed in the middle of the first implanted region 7, so as to form a conductive path for current to flow in order from the second implanted region 8, the first implanted region 7, the second epitaxial layer 5, and the second buried layer 4. The doping concentration of the second implanted region 8 is different from the doping concentration of the second epitaxial layer 5. In some embodiments of the present invention, the doping concentration of the second implanted region 8 is higher than the doping concentration of the second epitaxial layer 5.
Referring to fig. 7, step S06 is executed to specifically: a polysilicon layer 9 connected to the first buried layer 3 is formed in the first trench 6, and the polysilicon layer 9 is connected to the first implanted region 7. The polysilicon layer 9 is formed in the first trench 6 by means of epitaxy, diffusion and/or injection, preferably, the polysilicon in the polysilicon layer 9 is doped polysilicon, the doped polysilicon reduces the on-voltage under large current, and the effect of improving the breakdown voltage can be achieved by adjusting the doping concentration of the polysilicon. And filling polycrystalline silicon in the first trench 6, so that the polycrystalline silicon layer 9 forms conductive channels which penetrate through the second epitaxial layer 5 and are electrically connected with the first buried layer 3 and the first injection region 7 respectively. Further, the polysilicon layer 9 is formed by doping phosphorus ions or boron ions into intrinsic polysilicon, and those skilled in the art can select different doped polysilicon types according to the structure of the device, and the polysilicon in the polysilicon layer 9 may be P-type polysilicon or N-type polysilicon. In the process of forming the doped polysilicon layer 9, neutral atoms in the doped polysilicon layer 9 serve to prevent the dopant ions from condensing, and the dopant ions serve to have an adsorption effect on silicon atoms. In particular, the method of epitaxy, diffusion and/or implantation comprises a deposition process. In some embodiments of the present invention, the first epitaxial layer 2 may be formed on the upper surface of the substrate 1 by using a deposition process, for example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, and sputtering. Preferably, the polysilicon layer 9 is formed on the substrate 1 by Low Pressure Chemical Vapor Deposition (LPCVD), and the formed polysilicon layer 9 has high purity and good uniformity.
Referring to fig. 7, step S07 is executed to specifically: a dielectric layer 10 is formed on the upper surface of the second epitaxial layer 5. The dielectric layer 10 is made of silicon oxide, silicon nitride or silicon oxynitride, and the dielectric layer 10 may be formed by sputtering, thermal oxidation or chemical vapor deposition. Preferably, the dielectric layer 10 is a silicon oxide layer formed by thermal oxidation, and in the subsequent doping step, the silicon oxide layer serves as a protective layer and will serve as an interlayer insulating layer of the final device. In addition, the dielectric layer 10 is provided with a certain thickness, so that the dielectric layer 10 plays a role in isolating current and insulating.
Further, one end of the polysilicon layer 9 penetrates through the second epitaxial layer 5 and extends to the first buried layer 3, and the other end extends from the surface of the second epitaxial layer 5 to the first implantation region 7 through the dielectric layer 10. The steps S06 and S07 specifically include: a first contact hole (not shown) is formed through the dielectric layer 10. In some embodiments of the present invention, the first contact hole is located at an upper side of the first trench 6 such that the first contact hole is in communication with the first trench 6, and an inner diameter of the first contact hole is larger than an inner diameter of the first trench 6. After the first contact hole is formed, doped polysilicon is formed into the first contact hole and the first trench 6, specifically, the top end of the formed doped polysilicon is located in the middle of the first contact hole. And doping polysilicon in the dielectric layer 10 on the sidewall of the first contact hole to form a lateral channel, wherein the lateral channel is connected with the top end of the doped polysilicon formed in the first contact hole and the first trench 6. Further, step S07 includes: and etching to form a second trench (not shown) with the bottom connected with the first implanted region 7, extending the second trench into the dielectric layer 10 and connecting with the transverse channel, and forming doped polysilicon in the second trench to form a polysilicon layer 9 spanning the dielectric layer and respectively connecting with the first buried layer 3 and the first implanted region 7. In an embodiment of the present invention, the bottom of the second trench is connected to the first implantation region 7, and may extend into the first implantation region 7, or may extend to the upper surface of the first implantation region 7, so as to ensure that the bottom of the second trench is in contact with the first implantation region 7. After forming the polysilicon layer 9 extending from the surface of the second epitaxial layer 5 to the first implantation region 7 through the dielectric layer 10, a filling dielectric layer flush with the upper surface of the dielectric layer 10 is formed in a blank region of the first contact hole not filled with the doped polysilicon. Preferably, the inner diameter of the second trench is smaller than that of the first trench 6, so that the contact area between the doped polysilicon formed in the second trench and the first implantation region 7 is greatly reduced, thereby reducing the parasitic capacitance.
Referring to fig. 8, step S08 is executed: forming a first electrode 11, wherein the first electrode 11 comprises a first part 111 penetrating through the dielectric layer 10 and extending to the second injection region 8 and a second part 112 formed on the surface of the dielectric layer 10; a second electrode 12 connected to the substrate 1 is formed on the lower surface of the substrate 1. First, a second contact hole (not shown) is formed through the dielectric layer 10 and extends to the second implantation region 8 by etching. Preferably, the second contact hole is formed by dry etching, the dry etching comprises light volatilization, gas phase corrosion, plasma corrosion and the like, and the dry etching is easy to realize automation, has no pollution introduced in the treatment process and has high cleanliness. And filling a metal material into the second contact hole to form a first part 111, and covering the upper surface of the dielectric layer 10 with the metal material to form a second part 112. The first portion 111 and the second portion 112 form a first metal layer, i.e. a first electrode 11, which is in communication with each other. The first electrode 11 is electrically connected to the second implant region 8 through the first portion 111 so that a current flows to a path formed by the second implant region 8 and the first implant region 7 to form a PN junction. In addition, a second metal layer is formed by metallizing the lower surface of the substrate 1, thereby forming a second electrode 12 electrically connected to the substrate 1. The current flows through the substrate 1 along the second electrode 12 to an external circuit.
Further, the first buried layer 3 includes a first sub buried layer and a second sub buried layer which are respectively arranged on two sides of the second buried layer 4, the polycrystalline silicon layer 9 includes a first polycrystalline silicon layer connected with the first sub buried layer and a second polycrystalline silicon layer connected with the second sub buried layer, so that the current protection chip forms a symmetrical device structure, and branches symmetrical on the left and right sides are respectively formed outside a conductive path formed by the first electrode 11, the second injection region 8, the first injection region 7, the second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2, the substrate 1 and the second electrode 12, wherein current sequentially passes through the first electrode 11, the second injection region 8, the first injection region 7, the second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2 and the second. It is understood that the first trench 6 is a deep trench, and the polysilicon layer 9 forms a conductive channel for conducting by forming the polysilicon layer 9 in the first trench 6 to be electrically connected to the first buried layer 3 and the first implanted region 7, respectively, and electrically connecting the first implanted region 7 to the first buried layer 3 to form a conductive path in parallel. In addition, the first buried layer 3 and the polysilicon layer 9 are symmetrically distributed to form a 3-way bidirectional parallel equivalent circuit, and due to the unidirectional conductivity of the diode and the small section capacitance, the access capacitance is effectively reduced, so that the parasitic capacitance of the device can be reduced in a high-frequency circuit.
A current protection chip is described in detail below with reference to the accompanying drawings.
Further, a current protection chip and an equivalent circuit thereof according to an embodiment of the present invention are described in detail below with reference to fig. 1 to 9.
As shown in the equivalent circuit diagram of fig. 9, the present invention provides a current protection chip, including:
a substrate 1 of a first conductivity type;
a first epitaxial layer 2 of a second conductivity type grown on the upper surface of the substrate 1;
a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type formed in the first epitaxial layer 2, wherein at least part of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2;
a second epitaxial layer 5 of the first conductivity type formed on the upper surface of the first epitaxial layer 2;
a first implanted region 7 of a second conductivity type and a second implanted region 8 of a first conductivity type formed on the upper surface of the second epitaxial layer 5, wherein the second implanted region 8 is located in the first implanted region 7;
a polysilicon layer 9 connected to the first implanted region 7 and the first buried layer 3, respectively;
a dielectric layer 10 formed on the upper surface of the second epitaxial layer 5;
a first electrode 11 including a first portion 111 penetrating the dielectric layer 10 and extending to the second implantation region 8 and a second portion 112 formed on the surface of the dielectric layer 10;
and a second electrode 12 formed on a lower surface of the substrate 1 and connected to the substrate 1.
Specifically, the first conductive type is one of P-type doping and N-type doping, and the second conductive type is the other of P-type doping and N-type doping.
For convenience of description, it is specifically stated herein that: the first conductivity type may be N-type doped, such that the second conductivity type is P-type doped; the first conductivity type may also be P-type doped, whereby the second conductivity type is N-type doped. It is to be understood that, when the first conductivity type is N-type doping and the second conductivity type is P-type doping, the substrate 1, the second epitaxial layer 5, the first buried layer 3 and the second implanted region 8 are all N-type doping, and the first epitaxial layer 2, the second buried layer 4 and the first implanted region 7 are all P-type epitaxial layers. When the first conductivity type is P-type doping and the second conductivity type is N-type doping, the substrate 1, the second epitaxial layer 5, the first buried layer 3 and the second implanted region 8 are all P-type doping, and the first epitaxial layer 2, the second buried layer 4 and the first implanted region 7 are all N-type epitaxial layers. In the following embodiments, the first conductive type is an N-type doping, and the second conductive type is a P-type doping, which are not limited to the above description.
Specifically, the P-type substrate 1 and the P-type epitaxy belong to a P-type semiconductor, and the N-type substrate 1 and the N-type epitaxy belong to an N-type semiconductor. The P-type semiconductor is a silicon wafer doped with trivalent elements, such as boron elements, indium elements, aluminum elements or any combination of the three. The N-type semiconductor is a silicon wafer doped with pentavalent elements, such as phosphorus or arsenic or any combination of the phosphorus and the arsenic.
In some embodiments of the present invention, as shown in fig. 2, the current protection chip includes a substrate 1 of a first conductivity type and a first epitaxial layer 2 of a second conductivity type, and the first epitaxial layer 2 is grown on an upper surface of the substrate 1. The first epitaxial layer 2 of the second conductivity type grows on the upper surface of the substrate 1 of the first conductivity type, and reacts at the same time, and when current sequentially passes through the first epitaxial layer 2 and the substrate 1, a PN junction is formed. Preferably, the first epitaxial layer 2 and the substrate 1 are made of silicon material, so that the substrate 1 and the first epitaxial layer 2 have silicon surfaces with the same crystal structure, thereby maintaining control over impurity type and concentration. In addition, the first epitaxial layer 2 reduces series resistance while optimizing the breakdown voltage of the PN junction, and improves the device speed under moderate current intensity.
In some embodiments of the present invention, as shown in fig. 3, the current protection chip further includes a first buried layer 3 of a first conductivity type and a second buried layer 4 of a second conductivity type, where the first buried layer 3 and the second buried layer 4 are both formed in the first epitaxial layer 2, at least a portion of the surfaces of the first buried layer 3 and the second buried layer 4 are exposed on the upper surface of the first epitaxial layer 2, and a doping concentration of the second buried layer 4 is higher than a doping concentration of the first epitaxial layer 2. Further, the first buried layer 3 and the second buried layer 4 are adjacent, and the first buried layer 3 and the second buried layer 4 may be spaced apart from each other or may be connected to each other. In addition, the first buried layer 3 and the second buried layer 4 are both heavily doped, thereby reducing the resistivity of the first buried layer 3 and the second buried layer 4. Preferably, the doping concentration of the second buried layer 4 is higher than that of the first epitaxial layer 2, and current flows along the second buried layer 4 with low resistivity to the lower side of the first epitaxial layer 2, so that a current path is changed, which is equivalent to reduction of series resistance.
In some embodiments of the present invention, as shown in fig. 4, the current protection chip further includes a second epitaxial layer 5 of the first conductivity type, and the second epitaxial layer 5 is formed on the upper surface of the first epitaxial layer 2. The thickness of the first epitaxial layer 2 and the second epitaxial layer 5 depends on the physical size of the semiconductor device to be realized and on the silicon loss during the device manufacturing process. The second epitaxial layer 5 grows on the upper surface of the first epitaxial layer 2, and plays a role in reducing the leakage current of PN junctions in the semiconductor device.
In some embodiments of the present invention, as shown in fig. 5 and 6, the current protection chip further includes a first implanted region 7 of a second conductivity type and a second implanted region 8 of a first conductivity type, the first implanted region 7 and the second implanted region 8 are formed on the upper surface of the second epitaxial layer 5, and the second implanted region 8 is located in the first implanted region 7. In some embodiments of the present invention, the first injection region 7 and the second injection region 8 are both heavily doped, and since the conductivity types of the first injection region 7 and the second injection region 8 are different, the first injection region 7 and the second injection region 8 react to form a PN junction with a high doping concentration. It should be noted that at least partial surfaces of the first implantation region 7 and the second implantation region 8 are exposed on the upper surface of the second epitaxial layer 5, and other surfaces of the first implantation region 7 except the exposed surface are all covered by the second implantation region 8, so that a contact area between the first implantation region 7 and the second implantation region 8 is obtained as much as possible, thereby improving the reaction efficiency of the PN junction, increasing the current flow rate, and further increasing the discharge capability of the current protection chip.
In some embodiments of the present invention, as shown in fig. 7, the current protection chip further includes a polysilicon layer 9, and the polysilicon layer 9 is connected to the first implanted region 7 and the first buried layer 3, respectively. The current protection chip, even a semiconductor device, is mostly made of single crystal silicon, the polysilicon layer 9 is electrically connected to the first implanted region 7 and the first buried layer 3, respectively, and current directly flows into the first buried layer 3 after passing through the first implanted region 7, so that discharge efficiency is higher. In particular, the polysilicon layer 9 has high compatibility in single crystal silicon.
In some embodiments of the present invention, as shown in fig. 7, the current protection chip further includes a dielectric layer 10, and the dielectric layer 10 is formed on the upper surface of the second epitaxial layer 5. The dielectric layer 10 is used to isolate the second epitaxial layer 5.
Further, one end of the polysilicon layer 9 penetrates through the second epitaxial layer 5 and extends to the first buried layer 3, and the other end extends from the surface of the second epitaxial layer 5 to the first implantation region 7 through the dielectric layer 10. One end of the polysilicon layer 9 penetrates through the second epitaxial layer 5 and extends to the first buried layer 3, and one end of the polysilicon layer 9 penetrates through the second epitaxial layer 5 and extends into the first buried layer 3, or one end of the polysilicon layer 9 penetrates through the second epitaxial layer 5 and extends to the upper surface of the first buried layer 3, so that one end of the polysilicon layer is in contact with the first buried layer 3. More specifically, the other end of the polysilicon layer 9 extends from the upper surface of the second epitaxial layer 5 into the dielectric layer 10, and the other end of the polysilicon layer 9 forms a bent channel in the dielectric layer 10 to extend to the first implantation region 7. Further, the lateral channel connects the first implantation region 7, and may extend into the first implantation region 7, or may extend to the upper surface of the first implantation region 7, so as to ensure that the lateral channel is in contact with the first implantation region 7. In addition, the other end of the polysilicon surrounds the dielectric layer 10 in a partial region inside a curved channel formed in the dielectric layer 10, so as to form a closed region, so that the region other than the other end of the polysilicon is isolated from the second epitaxial layer 5 by the dielectric layer 10.
In some embodiments of the present invention, as shown in fig. 8, the current protection chip further includes a first electrode 11, where the first electrode 11 includes a first portion 111 penetrating through the dielectric layer 10 and extending to the second implantation region 8, and a second portion 112 formed on the surface of the dielectric layer 10; the current protection chip further comprises a second electrode 12, wherein the second electrode 12 is formed on the lower surface of the substrate 1 and is connected with the substrate 1. In some embodiments of the present invention, the first portion 111 penetrates through the dielectric layer 10 and extends to the second implantation region 8, the first portion 111 may penetrate through the dielectric layer 10 and extend into the second implantation region 8, or the first portion 111 penetrates through the dielectric layer 10 and extends to an upper surface of the second implantation region 8, so as to ensure that the first portion 111 contacts the second implantation region 8. The first electrode 11 is specifically a first metal layer, the second electrode 12 is specifically a second metal layer, the first portion 111 and the second portion 112 are filled with a metal material, and the first portion 111 and the second portion 112 are communicated and form the first metal layer together. The first metal layer and the second metal layer are provided with a certain thickness. The second metal layer is in electrically connected relationship with the substrate 1.
Further, the first buried layer 3 includes a first sub buried layer and a second sub buried layer respectively disposed at both sides of the second buried layer 4, and the polycrystalline silicon layer 9 includes a first polycrystalline silicon layer connected to the first sub buried layer and a second polycrystalline silicon layer connected to the second sub buried layer. The whole current protection chip is a first primitive cell.
Please refer to the equivalent circuit diagram of the current protection chip structure shown in fig. 9. When electricity is applied to the first electrode 11 and the second electrode 12, the current flows from the first electrode 11 to the second electrode 12. Note that, the forward direction and the reverse direction of the PN junction formed below are determined by setting the first conductivity type to be N-type and setting the second conductivity type to be P-type, which is an embodiment of the present invention, but the present invention is not limited thereto. The current sequentially passes through the first electrode 11, the second injection region 8, the first injection region 7, the second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2, the substrate 1 and the second electrode 12 to form a main circuit. The second implant region 8 and the first implant region 7 form an inverted PN junction and thus an inverted first diode a 1. The first implanted region 7 and the second epitaxial layer 5 form a PN junction in the forward direction, thus forming a second diode b1 in the forward direction. The second epitaxial layer 5 and the second buried layer 4 form an inverted PN junction, thus forming an inverted third diode c 1. The first epitaxial layer 2 and the substrate 1 form a forward PN junction, thus forming a forward fourth diode d 1. The main circuit forms an equivalent circuit consisting of four diodes. When current passes through the first electrode 11, the second injection region 8 and the first injection region 7 in sequence, the current is shunted to the polysilicon layer 9 after passing through the second injection region 8 and the first injection region in sequence due to the action of the polysilicon layer 9, and then passes through the polysilicon layer 9, the first buried layer 3, the first epitaxial layer 2, the substrate 1 and the second electrode 12 in sequence to form a parallel first shunt circuit. The second implant region 8 and the first implant region 7 form an inverted PN junction, thus forming an inverted fifth diode a 2. The first buried layer 3 forms an inverted PN junction with the first epitaxial layer 2, thus forming an inverted sixth diode b 2. The first epitaxial layer 2 forms a forward PN junction with the substrate 1, thus forming a forward seventh diode c 2. The first sub-circuit forms an equivalent circuit consisting of three diodes. Because the number of the first buried layer 3 and the number of the polysilicon layer 9 are two and are respectively symmetrical, the current protection chip has a structure that a first sub-circuit and a second sub-circuit are symmetrically distributed in addition to a main circuit. In summary, the current protection chip to be protected in the present invention forms an equivalent circuit with 3 groups of diodes connected in parallel, and because the diodes have unidirectional conductivity and have a smaller capacitance, the access capacitance is effectively reduced, so that the parasitic capacitance of the device can be reduced in the high frequency circuit.
The technical scheme of the invention is described in detail in the above with reference to the accompanying drawings, 3 groups of current protection chips are integrated together through the improvement of the technical scheme of the invention, and the area of the device is reduced by introducing the buried layer 3 process, so that the process difficulty is reduced, and the manufacturing cost of the device is reduced. Three groups of diodes are connected in parallel, parasitic capacitance is reduced, and the protection characteristic and reliability of the improved current protection chip are improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A current protection chip, comprising:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type grown on the upper surface of the substrate;
the first buried layer of the first conductivity type and the second buried layer of the second conductivity type are formed in the first epitaxial layer, at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
the second epitaxial layer of the first conductivity type is formed on the upper surface of the first epitaxial layer;
a first implanted region of a second conductivity type and a second implanted region of the first conductivity type formed on the upper surface of the second epitaxial layer, the second implanted region being located within the first implanted region;
a polysilicon layer connected to the first implanted region and the first buried layer, respectively;
the dielectric layer is formed on the upper surface of the second epitaxial layer;
the first electrode comprises a first part penetrating through the dielectric layer and extending to the second injection region and a second part formed on the surface of the dielectric layer;
the second electrode is formed on the lower surface of the substrate and is connected with the substrate;
wherein a doping concentration of the first buried layer is higher than a doping concentration of the second epitaxial layer.
2. The current protection chip of claim 1, wherein said second buried layer is located below said first implanted region.
3. The current protection chip of claim 1, wherein one end of the polysilicon layer extends through the second epitaxial layer and to the first buried layer, and the other end extends from the surface of the second epitaxial layer through the dielectric layer to the first implanted region.
4. The current protection chip of claim 1, wherein the first buried layer comprises a first sub buried layer and a second sub buried layer respectively disposed at both sides of the second buried layer, and the polysilicon layer comprises a first polysilicon layer connected to the first sub buried layer and a second polysilicon layer connected to the second sub buried layer.
5. A method for manufacturing a current protection chip comprises the following steps:
growing a first epitaxial layer of a second conductivity type on the upper surface of a substrate of the first conductivity type;
forming a first buried layer of a first conductivity type and a second buried layer of a second conductivity type in the first epitaxial layer, wherein at least part of the surfaces of the first buried layer and the second buried layer are exposed on the upper surface of the first epitaxial layer, and the doping concentration of the second buried layer is higher than that of the first epitaxial layer;
forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer;
forming a first trench penetrating the second epitaxial layer and extending to the first buried layer;
forming a first injection region of a second conductivity type and a second injection region of a first conductivity type on the upper surface of the second epitaxial layer, and forming the first injection region in the second injection region;
forming a polycrystalline silicon layer connected with the first buried layer in the first trench, and connecting the polycrystalline silicon layer with the first injection region;
forming a dielectric layer on the upper surface of the second epitaxial layer;
forming a first electrode, wherein the first electrode comprises a first part which penetrates through the dielectric layer and extends to the second injection region and a second part which is formed on the surface of the dielectric layer;
forming a second electrode connected with the substrate on the lower surface of the substrate;
wherein a doping concentration of the first buried layer is higher than a doping concentration of the second epitaxial layer.
6. The method as claimed in claim 5, wherein the second buried layer is disposed under the first implanted region.
7. The method as claimed in claim 5, wherein one end of the polysilicon layer extends through the second epitaxial layer and to the first buried layer, and the other end extends from the surface of the second epitaxial layer to the first implanted region through the dielectric layer.
8. The method as claimed in claim 5, wherein the first buried layer comprises a first sub buried layer and a second sub buried layer respectively disposed at two sides of the second buried layer, and the polysilicon layer comprises a first polysilicon layer connected to the first sub buried layer and a second polysilicon layer connected to the second sub buried layer.
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| CN102637725A (en) * | 2012-04-26 | 2012-08-15 | 杭州士兰集成电路有限公司 | Device accomplished by adopting Bipolar low-pressure process and manufacturing method thereof |
| CN105702674A (en) * | 2016-03-18 | 2016-06-22 | 江苏艾伦摩尔微电子科技有限公司 | Novel electrostatic discharge protection apparatus |
| CN106449633A (en) * | 2016-09-23 | 2017-02-22 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method therefor |
| CN108063137A (en) * | 2017-12-11 | 2018-05-22 | 深圳迈辽技术转移中心有限公司 | Transient Voltage Suppressor and preparation method thereof |
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