CN109148292A - A kind of Transient Voltage Suppressor and preparation method thereof - Google Patents
A kind of Transient Voltage Suppressor and preparation method thereof Download PDFInfo
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- CN109148292A CN109148292A CN201810934180.9A CN201810934180A CN109148292A CN 109148292 A CN109148292 A CN 109148292A CN 201810934180 A CN201810934180 A CN 201810934180A CN 109148292 A CN109148292 A CN 109148292A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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Abstract
The present invention relates to a kind of Transient Voltage Suppressors, comprising: substrate；It is formed in the first injection region of the second conduction type of the substrate surface area；The first epitaxial layer being formed on the substrate；It is formed in the second epitaxial layer of the first conduction type on first epitaxial layer；It is formed in the first groove in second epitaxial layer and being located above the first part, and forms the second groove in the second epitaxial layer and being located above the second part, the first groove and second groove run through second epitaxial layer；It is respectively formed in the third epitaxial layer of the first conduction type in the first groove and the second groove and the fourth epitaxial layer of the first conduction type, the third epitaxial layer is connect with the first part and its height is less than the depth of the first groove, and the fourth epitaxial layer is connect with the second part and its height is less than the depth of the second groove；It is formed in the second injection region of the fourth epitaxial layer surface area.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a transient voltage suppressor and a manufacturing method thereof.
Background
The transient voltage suppressor is a solid semiconductor device specially designed for protecting sensitive semiconductor device from transient voltage surge damage, and has the advantages of small clamping coefficient, small volume, quick response, small leakage current, high reliability and the like, so that it is widely used in voltage transient and surge protection. The existing transient voltage suppressor is usually used for protecting a sensitive circuit from surge impact, but when a plurality of different circuits need to be protected at present, a plurality of different transient voltage suppressors need to be adopted for protection, so that the area of a chip is wasted, the cost is not saved, and the market demand cannot be met.
Disclosure of Invention
The embodiment of the invention provides a triode and a manufacturing method thereof, which can enable the amplification factor of the triode to be more stable and improve the performance of a device.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a transient voltage suppressor, where the method includes: forming a first implanted region of a second conductivity type in a surface region of a substrate of a first conductivity type; forming a first epitaxial layer on the substrate, wherein the first epitaxial layer comprises a first part of a first conductive type and a second part of a second conductive type, and the second part covers the first injection region; forming a second epitaxial layer of the first conductivity type on the first epitaxial layer; forming a first trench in the second epitaxial layer above the first portion, forming a second trench in the second epitaxial layer above the second portion, the first and second trenches both penetrating the second epitaxial layer; forming a side wall on the side wall of the first groove; forming a third epitaxial layer of the first conductivity type and a fourth epitaxial layer of the first conductivity type in the first trench and the second trench, respectively, wherein the third epitaxial layer is connected with the first portion and has a height smaller than the depth of the first trench, and the fourth epitaxial layer is connected with the second portion and has a height smaller than the depth of the second trench; forming a second implantation region of a second conductivity type in an upper surface region of the fourth epitaxial layer; forming a fifth epitaxial layer of a second conductivity type and a sixth epitaxial layer of the second conductivity type on the third epitaxial layer and the fourth epitaxial layer, respectively, so as to fill the first trench and the second trench fully; activating the impurities of the first injection region and the second injection region through a rapid thermal annealing process, and simultaneously diffusing the impurities of the sixth epitaxial layer into the second epitaxial layers on the two sides to form shallow junctions 13 of the first conductivity type; and respectively forming a dielectric layer, a first front electrode, a second front electrode and a back electrode.
In a second aspect, an embodiment of the present invention provides a transient voltage suppressor, including: a substrate of a first conductivity type; a first injection region of the second conductivity type formed in the substrate surface region; a first epitaxial layer formed on the substrate, the first epitaxial layer including a first portion of a first conductivity type and a second portion of a second conductivity type, the second portion overlying the first implanted region; a second epitaxial layer of the first conductivity type formed on the first epitaxial layer; a first trench formed in the second epitaxial layer and above the first portion, and a second trench formed in the second epitaxial layer and above the second portion, the first and second trenches penetrating the second epitaxial layer; a side wall formed on the side wall of the first groove; a third epitaxial layer of the first conductivity type and a fourth epitaxial layer of the first conductivity type formed in the first trench and the second trench, respectively, the third epitaxial layer being connected to the first portion and having a height less than the depth of the first trench, the fourth epitaxial layer being connected to the second portion and having a height less than the depth of the second trench; a second implantation region formed in an upper surface region of the fourth epitaxial layer; a fifth epitaxial layer of a second conductivity type and a sixth epitaxial layer of a second conductivity type formed on the third epitaxial layer and the fourth epitaxial layer, the upper surfaces of the fifth epitaxial layer and the sixth epitaxial layer being aligned with the upper surface of the second epitaxial layer; a dielectric layer 14, a first front electrode, a second front electrode, and a back electrode.
It can be understood that, in the embodiment of the present invention, the first portion and the second portion, and the first trench and the second trench respectively located above the first portion and the second portion, and the first injection region is further formed in the first epitaxial layer below the first portion, so as to form two protection paths with different inhibit voltages, which can conveniently protect different circuits, save the cost, and meet the market demand.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. The accompanying drawings, which form a part hereof, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention without undue limitation to the invention.
The invention is further illustrated with reference to the following figures and examples.
Fig. 1 is a schematic flow chart illustrating a method for fabricating a transient voltage suppressor according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of a transient voltage suppressor according to an embodiment of the present invention;
fig. 3 to 13 are schematic cross-sectional views illustrating a method for fabricating a tvs according to an embodiment of the present invention;
fig. 14 is an equivalent circuit diagram of the transient voltage suppressor according to the embodiment of the invention.
Description of reference numerals: 1. a substrate; 2. a first implanted region; a. an epitaxial layer; 3. a first epitaxial layer; 4. a second epitaxial layer; 5. a first trench; 6. a second trench; 7. a side wall; 8. a third epitaxial layer; 9. a fourth epitaxial layer; 10. a second implanted region; 11. a fifth epitaxial layer; 12. a sixth epitaxial layer; 13. a shallow junction 13; 14. a dielectric layer 14; 15. a first front electrode; 16. a second front electrode; 17. and a back electrode.
Detailed Description
In order to make the objects, technical solutions and advantageous technical effects of the present invention more clearly and completely apparent, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing methods and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Referring to fig. 1 and fig. 2, the present invention provides a method for manufacturing a transient voltage suppressor, including:
step S01: a first implanted region 2 of a second conductivity type is formed in a surface region of the substrate 1 of the first conductivity type.
Step S02: a first epitaxial layer 3 is formed on the substrate 1, the first epitaxial layer 3 comprising a first portion 31 of a first conductivity type and a second portion 32 of a second conductivity type, the second portion 32 covering the first implanted region 2.
Step S03: a second epitaxial layer 4 of the first conductivity type is formed on the first epitaxial layer 3.
Step S04: a first trench 5 is formed in the second epitaxial layer 4 above the first portion 31 and a second trench 6 is formed in the second epitaxial layer 4 above the second portion 32, the first and second trenches 5, 6 both penetrating the second epitaxial layer 4.
Step S05: and forming a side wall 7 on the side wall of the first groove 5.
Step S06: a third epitaxial layer 8 of the first conductivity type and a fourth epitaxial layer 9 of the first conductivity type are respectively formed in the first trench 5 and the second trench 6, the third epitaxial layer 8 is connected with the first portion 31 and has a height smaller than the depth of the first trench 5, and the fourth epitaxial layer 9 is connected with the second portion 32 and has a height smaller than the depth of the second trench 6.
Step S07: a second implanted region 10 of the second conductivity type is formed in the upper surface region of the fourth epitaxial layer 9.
Step S08: a fifth epitaxial layer 11 of the second conductivity type and a sixth epitaxial layer 12 of the second conductivity type are formed on the third epitaxial layer 8 and the fourth epitaxial layer 9, respectively, and the upper surfaces of the fifth epitaxial layer 11 and the sixth epitaxial layer 12 are aligned with the upper surface of the second epitaxial layer 4.
Step S09: a dielectric layer 14, a first front electrode 15, a second front electrode 16 and a back electrode 17 are formed, respectively.
It can be understood that, in the embodiment of the present invention, the first portion 31 and the second portion 32, and the first trench 5 and the second trench 6 respectively located above the first portion 31 and the second portion 32, and the first implantation region 2 is further formed in the first epitaxial layer 3 below the first portion 31, so as to form two protection paths with different suppression voltages, which can conveniently protect different circuits, save cost, and meet market requirements.
The above-described method of forming the transient voltage suppressor is explained in detail with reference to the accompanying drawings.
For convenience of the following description, it is specifically noted that: the technical scheme of the invention relates to the design and manufacture of semiconductor devices, wherein a semiconductor refers to a material with controllable conductivity and variable conductivity range from an insulator to a conductor, common semiconductor materials comprise silicon, germanium, gallium arsenide and the like, and silicon is the most influential of various semiconductor materials and is the most widely applied one. The semiconductor is divided into an intrinsic semiconductor, a P-type semiconductor and an N-type semiconductor, the semiconductor without impurities and without lattice defects is called an intrinsic semiconductor, trivalent elements (such as boron, indium, gallium and the like) are doped into a pure silicon crystal to replace the bits of silicon atoms in the crystal lattice to form a P-type semiconductor, pentavalent elements (such as phosphorus, arsenic and the like) are doped into a pure silicon crystal to replace the positions of the silicon atoms in the crystal lattice to form an N-type semiconductor, the conductivity types of the P-type semiconductor and the N-type semiconductor are different, in the embodiment of the invention, the first conductivity type is N-type, the second conductivity type is P-type, in the embodiment of the invention, if not specifically stated, the preferred doped ions of each conductivity type can be replaced by ions with the same conductivity type, and the description is omitted below.
Referring to fig. 3, step S01 is executed: a first implanted region 2 of a second conductivity type is formed in a surface region of the substrate 1 of the first conductivity type. In particular, the substrate 1 serves as a carrier, host, for the deviceTo serve as a support. In general, the material of the substrate 1 may be a silicon substrate, a silicon carbide substrate, a silicon nitride substrate, etc., in this embodiment, the silicon substrate is a silicon substrate, silicon is the most common, cheap and stable semiconductor material, and in this embodiment, the substrate 1 is a heavily doped substrate with a doping concentration of 5E16-3E17/cm3The resistivity is between 0.02m omega cm and 0.1m omega cm. In this embodiment, the dopant ions of the substrate 1 are phosphorus ions, but in other embodiments, other pentavalent ions such as arsenic or antimony may be used. Specifically, the first implantation region 2 is formed by ion implantation and/or diffusion on the surface of the substrate 1, and the concentration of implanted ions is 1E15-2E15/cm3Meanwhile, in the present embodiment, the ion type of the first implantation region 2 is boron ion, and in other embodiments, trivalent ions such as indium and gallium may be used. Further, the first injection region 2 is located in a partial upper surface region of the substrate 1, and an upper surface of the first injection region 2 is partially overlapped with an upper surface of the substrate 1, in this embodiment, the first injection region 2 includes a plurality of injection sub-regions distributed at intervals, the first injection region 2 and the substrate 1 form a PN junction, and the ion concentration of the first injection region 2 can be conveniently adjusted through the plurality of injection sub-regions at intervals, so that the breakdown voltage of a path where the first injection region 2 is located can be adjusted. In this embodiment, the first implantation region 2 specifically includes 3 implantation sub regions distributed at intervals.
Referring to fig. 4 and 5, step S02 is executed: a first epitaxial layer 3 is formed on the substrate 1, the first epitaxial layer 3 comprising a first portion 31 of the second conductivity type and a second portion 32 of the first conductivity type, the second portion 32 covering the first implanted region 2. Further, the forming of the first epitaxial layer 3 on the substrate 1 specifically includes: growing an epitaxial layer a of a first conduction type on the surface of the substrate 1; and injecting ions of a second conductivity type into a partial region of the epitaxial layer a to form the first portion 31, wherein the other region of the first epitaxial layer 3 except the first portion 31 is the second portion 32. Wherein,before the first portion 31 is formed, for the sake of convenience of distinction, the first epitaxial layer 3 before the first portion 31 is formed is referred to as an epitaxial layer a, which is a heavily doped epitaxial layer having a doping concentration of 3E15-3E16/cm3And the thickness is between 0.5 and 1.5 um. In this embodiment, the epitaxial layer a is formed by a homoepitaxy process with a simple process, that is, the material of the epitaxial layer a is the same as that of the substrate 1, and when the material of the substrate 1 is silicon, the material of the epitaxial layer a is also silicon. The epitaxial layer a may be formed on the first surface of the substrate 1 by an epitaxial growth method, in this embodiment, the doping ions of the epitaxial layer a are specifically phosphorus ions, and in other embodiments, the doping ions of the epitaxial layer a may also be other pentavalent ions such as arsenic or antimony. More specifically, the epitaxial growth method is preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method), which is a process of reacting a gaseous reaction raw material on the surface of a solid substrate and depositing the solid substrate into a solid thin layer or a thin film, and is a relatively mature epitaxial growth method, wherein silicon and doping elements are sprayed on the substrate 1, so that the uniformity and the repeatability are good, and the step coverage is excellent. Further, the first portion 31 is formed by implanting ions of a second conductivity type in a partial region of the epitaxial layer a, wherein the implantation concentration of the ions of the second conductivity type is 3E15-4E15/cm3In the present embodiment, the ions implanted to form the first portion 31 are specifically boron ions, but may be trivalent ions such as indium and gallium in other embodiments. And inverting a partial region of the epitaxial layer to a second conductivity type by implanting the boron ions. It should also be noted that the first portion 31 at least entirely covers the first implanted region 2, and in order to achieve better device performance, it is preferable that the first epitaxial layer 3 includes the first portion 31 on one side and the second portion 32 on the other side, and the first portion 31 is connected to the second portion 32 but not connected to the second portion 32There are mutually included portions, and the widths of the first portion 31 and the second portion 32 are substantially the same.
Referring to fig. 6, step S03 is executed: forming a second epitaxial layer 4 of the first conductivity type on the first epitaxial layer 3; in this embodiment, the second epitaxial layer 4 is made of silicon and has a doping concentration of 5E14-8E14/cm3Meanwhile, the thickness is 7-8um, more specifically, the doping ions of the second epitaxial layer 4 are specifically phosphorus ions, in other embodiments, the doping ions of the second epitaxial layer 4 may also be other pentavalent ions such as arsenic or antimony, and more specifically, the second epitaxial layer 4 may be formed on the first epitaxial layer 3 by an epitaxial growth method, which is preferably a chemical vapor deposition method (or vapor phase epitaxial growth method), the chemical vapor deposition method is a process of reacting a gaseous reaction raw material on a solid substrate surface and depositing a solid thin layer or a thin film, and is a relatively mature epitaxial growth method, in which silicon and doping elements are sprayed on the first epitaxial layer 3, uniformity and repeatability are good, step coverage is good, and meanwhile, the chemical vapor deposition method can improve the perfectness of a silicon material, the integration level of the device is improved, the minority carrier lifetime is prolonged, and the leakage current of the storage unit is reduced.
Referring to fig. 7, step S04 is executed: forming a first trench 5 in the second epitaxial layer 4 above the first portion 31 and a second trench 6 in the second epitaxial layer 4 above the second portion 32, the first and second trenches 5 and 6 both extending through the second epitaxial layer 4; specifically, the first groove 5 and the second groove 6 may be formed together or sequentially, which is not limited to this. In the present embodiment, the process of forming the first trench 5 or the second trench 6 is: forming an etching barrier layer (not shown) on the second epitaxial layer 4, then forming a photoresist layer (not shown) on the etching barrier layer, then exposing the photoresist layer by using a mask having the first trench 5 or the second trench 6 pattern, and then developing to obtain the photoresist layer having the first trench 5 or the second trench 6 pattern. And etching the etching barrier layer by using the photoresist layer having the first trench 5 and the second trench 6 as a mask and using an etching method such as a reactive ion etching method to form a pattern opening (not shown) of the first trench 5 or the second trench 6. And then, removing the second epitaxial layer 4 which is not covered by the etching barrier layer by using the etching barrier layer with the first trench 5 or the second trench 6 pattern opening as a mask and adopting methods such as wet etching or dry etching, and forming the first trench 5 or the second trench 6 in the second epitaxial layer 4. The photoresist layer and the etch stop layer may be removed thereafter by chemical cleaning or the like. In the above process, an anti-reflection layer (not shown) may be further formed between the photoresist layer and the etch stopper layer in order to ensure the exposure accuracy. More specifically, the first trench 5 and the second trench 6 are preferably etched by a dry etching method, the dry etching method includes light volatilization, vapor phase etching, plasma etching and the like, and the dry etching method is easy to realize automation, has no pollution introduced in the processing process, and has high cleanliness. In the present embodiment, the width of the second trench 6 is greater than the width of the first trench 5, and more specifically, the width of the first trench 5 is between 2-3um, and the width of the second trench 6 is between 6-8 um.
Referring to fig. 8, step S05 is executed: forming a side wall 7 on the side wall of the first trench 5; the side wall 7 is formed in the groove, and one end of the side wall is in contact with the first part 31; specifically, the step of forming the side wall 7 specifically includes: depositing an insulating layer (not shown) on the upper surface of the second epitaxial layer 4, and on the bottom surface and sidewalls of the first trench 5; and etching the insulating layer to form the side wall 7. More specifically, the insulating layer is deposited on the side wall and the bottom surface of the first trench 5 and the upper surface of the second epitaxial layer 4, and the insulating layer on the bottom surface of the first trench 5 and the upper surface of the second epitaxial layer 4 is removed by etching, so as to form the sidewall 7, where the insulating layer (the sidewall 7) is made of one or a combination of any one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride, and in this embodiment, the width of the sidewall 7 is between 5000 and 8000A, and the sidewall 7 is made of silicon oxide. In other embodiments, the sidewall spacers 7 may also be formed by a high temperature oxidation process, which is a conventional technique of those skilled in the art and will not be described in detail herein.
Referring to fig. 9, step S06 is executed: a third epitaxial layer 8 of the first conductivity type and a fourth epitaxial layer 9 of the first conductivity type are respectively formed in the first trench 5 and the second trench 6, the third epitaxial layer 8 is connected with the first portion 31 and has a height smaller than the depth of the first trench 5, and the fourth epitaxial layer 9 is connected with the second portion 32 and has a height smaller than the depth of the second trench 6. Specifically, the third epitaxial layer 8 and the fourth epitaxial layer 9 are formed in the first trench 5 and the second trench 6 respectively by using an epitaxial growth method, which is a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method) that has been described in detail above and will not be described again in detail. It should also be understood that the third epitaxial layer 8 and the fourth epitaxial layer 9 may be formed simultaneously or sequentially, and the heights of the third epitaxial layer 8 and the fourth epitaxial layer 9 may be the same or different, and are not limited herein. In this embodiment, the third epitaxial layer 8 and the fourth epitaxial layer 9 have the same height, and the height is between 3 to 4 um. Further, the material of the third epitaxial layer 8 and the fourth epitaxial layer 9 is also silicon, and they are both heavily doped materials, with a specific doping concentration between 2E15-5E15/cm 3.
Referring to fig. 10, step S07 is executed: a second implanted region 10 of the second conductivity type is formed in the upper surface region of the fourth epitaxial layer 9. Specifically, the second implantation region 10 is formed by performing ion implantation and/or diffusion on the surface of the fourth epitaxial layer 9, and the concentration of implanted ions is 4E15-5E15/cm 3. Further, the second injection region 10 is located in the upper surface region of the fourth epitaxial layer 9, and the upper surface of the second injection region 10 is partially overlapped with the upper surface of the fourth epitaxial layer 9, in this embodiment, the second injection region 10 includes a plurality of injection sub-regions distributed at intervals, the second injection region 10 and the fourth epitaxial layer 9 form a PN junction, and the ion concentration of the second injection region 10 can be conveniently adjusted through the injection sub-regions of the plurality of intervals, so that the breakdown voltage of a path where the second injection region 10 is located can be adjusted. In this embodiment, the second implantation region 10 specifically includes 3 implantation sub regions distributed at intervals.
Referring to fig. 11 and 12, step S08 is executed: a fifth epitaxial layer 11 of the second conductivity type and a sixth epitaxial layer 12 of the second conductivity type are formed on the third epitaxial layer 8 and the fourth epitaxial layer 9, respectively, to fill the first trench 5 and the second trench 6, respectively. Specifically, the third epitaxial layer 8 and the fourth epitaxial layer 9 are formed in the first trench 5 and the second trench 6 respectively by using an epitaxial growth method, which is a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method) that has been described in detail above and will not be described again in detail. It should also be understood that the fifth epitaxial layer 11 and the sixth epitaxial layer 12 may be formed simultaneously or sequentially, and the heights of the fifth epitaxial layer 11 and the sixth epitaxial layer 12 may be the same or different, which is not limited herein. Further, the material of the fifth epitaxial layer 11 and the sixth epitaxial layer 12 is also silicon, and they are both heavily doped materials, with a specific doping concentration between 4E15-6E15/cm 3. Further, in order to obtain a complete plane and fill the first trench 5 and the second trench 6 with the fifth epitaxial layer 11 and the sixth epitaxial layer 12, respectively, after forming the fifth epitaxial layer 11 and the sixth epitaxial layer 12, the method further includes: the planarization operation is performed on the upper surfaces of the fifth epitaxial layer 11, the sixth epitaxial layer 12 and the second epitaxial layer 4, specifically, a chemical mechanical polishing manner is adopted, and the chemical mechanical polishing is a conventional means for those skilled in the art, and is not described herein again. Further, after forming the fifth epitaxial layer 11 and the sixth epitaxial layer 12, the method further includes: and activating the impurities of the first implantation region 2, the second implantation region 10 and other doped regions through a rapid thermal annealing process, and simultaneously diffusing the impurities of the sixth epitaxial layer 12 into the second epitaxial layers 4 at two sides to form shallow junctions 1313 of the second conductivity type.
Referring to fig. 13, step S09 is executed: a dielectric layer 14, a first front electrode 15, a second front electrode 16 and a back electrode 17 are formed, respectively. Specifically, the first front electrode 15 penetrates through the dielectric layer 14 to be electrically connected with the fifth epitaxial layer 11, and the second front electrode 16 penetrates through the dielectric layer 14 to be electrically connected with the sixth epitaxial layer 12. The first front electrode 15, the second front electrode 16 and the back electrode 17 may be formed simultaneously or sequentially, and if they are formed sequentially, the forming sequence therebetween is not limited. More specifically, the dielectric layer 14 is formed on the upper surface of the second epitaxial layer 4, and a first contact hole and a second contact hole are formed on the dielectric layer 14, wherein the first contact hole is located above the fifth epitaxial layer 11, and the second contact hole is located above the sixth epitaxial layer 12; a first front electrode 15 connected with the fifth epitaxial layer 11 and a second front electrode 16 connected with the sixth epitaxial layer 12 are deposited on the first contact hole, the second contact hole and the dielectric layer 14. The dielectric layer 14 is made of an insulating material and may be formed by sputtering or thermal oxidation.
Referring to fig. 2 and fig. 14, wherein fig. 14 is an equivalent circuit diagram of a transient voltage suppressor according to an embodiment of the invention, as shown, the fifth epitaxial layer 11 and the third epitaxial layer 8 form a first diode with a fixed breakdown voltage, the first diode the first implanted region 2 and the second diode with variable breakdown voltage formed between the first portion 31 and the first epitaxial layer 3 are connected in series, the first front surface electrode 15, the first diode, the second diode and the back surface electrode 17 form a voltage-resistant circuit, the second implanted region 10 and the sixth epitaxial layer 12 form with the fourth epitaxial layer 9 a third diode with a variable breakdown voltage, the second front electrode 16, the third diode, and the back electrode 17 form another voltage-resistant circuit.
Referring to fig. 2, an embodiment of the invention provides a transient voltage suppressor, including: a substrate 1 of a first conductivity type;
a first implantation region 2 of a second conductivity type formed in a surface region of the substrate 1;
a first epitaxial layer 3 formed on said substrate 1, said first epitaxial layer 3 comprising a first portion 31 of a second conductivity type and a second portion 32 of a first conductivity type, said first portion 31 covering said first implanted region 2;
a second epitaxial layer 4 of the first conductivity type formed on the first epitaxial layer 3;
a first trench 5 formed in the second epitaxial layer 4 above the first portion 31 and a second trench 6 formed in the second epitaxial layer 4 above the second portion 32, the first and second trenches 5, 6 extending through the second epitaxial layer 4;
a side wall 7 formed on the side wall of the first trench 5;
a third epitaxial layer 8 of the first conductivity type and a fourth epitaxial layer 9 of the first conductivity type formed in the first trench 5 and the second trench 6, respectively, the third epitaxial layer 8 being connected to the first portion 31 and having a height less than the depth of the first trench 5, the fourth epitaxial layer 9 being connected to the second portion 32 and having a height less than the depth of the second trench 6;
a second implanted region 10 formed in an upper surface region of the fourth epitaxial layer 9;
a fifth epitaxial layer 11 of the second conductivity type and a sixth epitaxial layer 12 of the second conductivity type formed on the third epitaxial layer 8 and the fourth epitaxial layer 9, wherein upper surfaces of the fifth epitaxial layer 11 and the sixth epitaxial layer 12 are aligned with an upper surface of the second epitaxial layer 4;
a dielectric layer 14, a first front electrode 15, a second front electrode 16 and a back electrode 17.
It can be understood that, in the embodiment of the present invention, the first portion 31 and the second portion 32, and the first trench 5 and the second trench 6 respectively located above the first portion 31 and the second portion 32, and the first implantation region 2 is further formed in the first epitaxial layer 3 below the first portion 31, so as to form two protection paths with different suppression voltages, which can conveniently protect different circuits, save cost, and meet market requirements.
Further, the substrate 1 serves as a carrier of the device, and mainly plays a role of supporting. In general, the material of the substrate 1 may be a silicon substrate, a silicon carbide substrate, a silicon storage substrate, etc., in this embodiment, the silicon substrate is a silicon substrate, silicon is the most common, cheap and stable semiconductor material, and in this embodiment, the substrate 1 is a heavily doped substrate with a doping concentration of 5E16-3E17/cm3The resistivity is between 0.02m omega cm and 0.1m omega cm. In this embodiment, the dopant ions of the substrate 1 are phosphorus ions, but in other embodiments, other pentavalent ions such as arsenic or antimony may be used. Specifically, the first implantation region 2 is formed by ion implantation and/or diffusion on the surface of the substrate 1, and the concentration of implanted ions is 1E15-2E15/cm3Meanwhile, in the present embodiment, the ion type of the first implantation region 2 is boron ion, and in other embodiments, trivalent ions such as indium and gallium may be used. Further, the first implantation region 2 is located in a partial upper surface region of the substrate 1, and an upper surface of the first implantation region 2 is partially overlapped with the upper surface of the substrate 1, in this embodiment, the first implantation region 2 includes a plurality of implantation sub-regions distributed at intervals, the first implantation region 2 forms a PN junction with the substrate 1, and implantation through the plurality of intervals is performedThe sub-region can facilitate adjustment of the ion concentration of the first injection region 2, and further can adjust the breakdown voltage of a path where the first injection region 2 is located. In this embodiment, the first implantation region 2 specifically includes 3 implantation sub regions distributed at intervals.
Further, the forming of the first epitaxial layer 3 on the substrate 1 specifically includes: growing an epitaxial layer a of a first conduction type on the surface of the substrate 1; and injecting ions of a second conductivity type into a partial region of the epitaxial layer a to form the first portion 31, wherein the other region of the first epitaxial layer 3 except the first portion 31 is the second portion 32. Wherein, before the first portion 31 is formed, for the sake of convenience of distinction, the first epitaxial layer 3 before the first portion 31 is formed is referred to as an epitaxial layer a, and the epitaxial layer a is a heavily doped epitaxial layer with a doping concentration of 3E15-3E16/cm3And the thickness is between 0.5 and 1.5 um. In this embodiment, the epitaxial layer a is formed by a homoepitaxy process with a simple process, that is, the material of the epitaxial layer a is the same as that of the substrate 1, and when the material of the substrate 1 is silicon, the material of the epitaxial layer a is also silicon. The epitaxial layer a may be formed on the first surface of the substrate 1 by an epitaxial growth method, in this embodiment, the doping ions of the epitaxial layer a are specifically phosphorus ions, and in other embodiments, the doping ions of the epitaxial layer a may also be other pentavalent ions such as arsenic or antimony. More specifically, the epitaxial growth method is preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method), which is a process of reacting a gaseous reaction raw material on the surface of a solid substrate and depositing the solid substrate into a solid thin layer or a thin film, and is a relatively mature epitaxial growth method, wherein silicon and doping elements are sprayed on the substrate 1, so that the uniformity and the repeatability are good, and the step coverage is excellent. Further, the first portion 31 is formed by implanting ions of the second conductive type into a partial region of the epitaxial layer a, wherein the first portionThe implantation concentration of the ions of the two conductivity types is 3E15-4E15/cm3In the present embodiment, the ions implanted to form the first portion 31 are specifically boron ions, but may be trivalent ions such as indium and gallium in other embodiments. And inverting a partial region of the epitaxial layer to a second conductivity type by implanting the boron ions. It should be noted that the first portion 31 at least entirely covers the first implantation region 2, and in order to achieve better device performance, it is preferable that the first epitaxial layer 3 includes the first portion 31 on one side and the second portion 32 on the other side, the first portion 31 is connected to the second portion 32 but does not include a mutual portion, and widths of the first portion 31 and the second portion 32 are substantially the same.
Furthermore, the second epitaxial layer 4 is made of silicon, and the doping concentration thereof is 5E14-8E14/cm3The thickness of the second epitaxial layer 4 is 7-8um, more specifically, the doping ions of the second epitaxial layer 4 are phosphorus ions, and in other embodiments, the doping ions of the second epitaxial layer 4 may also be other pentavalent ions such as arsenic or antimony. The second epitaxial layer 4 may be formed on the first surface of the first epitaxial layer 3 by an epitaxial growth method, and more specifically, the second epitaxial layer 4 may be formed on the first epitaxial layer 3 by an epitaxial growth method, and the epitaxial growth method is preferably a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method), and the chemical vapor deposition method is a process of reacting a gaseous reaction material on a surface of a solid substrate and depositing the solid thin layer or the thin film, and is a mature epitaxial growth method, and the method sprays silicon and a doping element on the first epitaxial layer 3, so that the uniformity, the repeatability and the step coverage are good, and meanwhile, the chemical vapor deposition method can improve the perfection of the silicon material, improve the integration level of the device, and achieve the improvement of the minority carrier lifetime and the reduction of the leakage current of the storage unit.
Further, the first groove 5 and the second groove 6 may be formed together or sequentially, which is not limited to this. In the present embodiment, the process of forming the first trench 5 or the second trench 6 is: forming an etching barrier layer (not shown) on the second epitaxial layer 4, then forming a photoresist layer (not shown) on the etching barrier layer, then exposing the photoresist layer by using a mask having the first trench 5 or the second trench 6 pattern, and then developing to obtain the photoresist layer having the first trench 5 or the second trench 6 pattern. And etching the etching barrier layer by using the photoresist layer having the first trench 5 and the second trench 6 as a mask and using an etching method such as a reactive ion etching method to form a pattern opening (not shown) of the first trench 5 or the second trench 6. And then, removing the second epitaxial layer 4 which is not covered by the etching barrier layer by using the etching barrier layer with the first trench 5 or the second trench 6 pattern opening as a mask and adopting methods such as wet etching or dry etching, and forming the first trench 5 or the second trench 6 in the second epitaxial layer 4. The photoresist layer and the etch stop layer may be removed thereafter by chemical cleaning or the like. In the above process, an anti-reflection layer (not shown) may be further formed between the photoresist layer and the etch stopper layer in order to ensure the exposure accuracy. More specifically, the first trench 5 and the second trench 6 are preferably etched by a dry etching method, the dry etching method includes light volatilization, vapor phase etching, plasma etching and the like, and the dry etching method is easy to realize automation, has no pollution introduced in the processing process, and has high cleanliness. In the present embodiment, the width of the second trench 6 is greater than the width of the first trench 5, and more specifically, the width of the first trench 5 is between 2-3um, and the width of the second trench 6 is between 6-8 um.
Further, the forming step of the side wall 7 specifically includes: depositing an insulating layer (not shown) on the upper surface of the second epitaxial layer 4, and on the bottom surface and sidewalls of the first trench 5; and etching the insulating layer to form the side wall 7. More specifically, the insulating layer is deposited on the side wall and the bottom surface of the first trench 5 and the upper surface of the second epitaxial layer 4, and the insulating layer on the bottom surface of the first trench 5 and the upper surface of the second epitaxial layer 4 is removed by etching, so as to form the sidewall 7, where the insulating layer (the sidewall 7) is made of one or a combination of any one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride, and in this embodiment, the width of the sidewall 7 is between 5000 and 8000A, and the sidewall 7 is made of silicon oxide. In other embodiments, the sidewall spacers 7 may also be formed by a high temperature oxidation process, which is a conventional technique of those skilled in the art and will not be described in detail herein.
Further, the third epitaxial layer 8 and the fourth epitaxial layer 9 are formed in the first trench 5 and the second trench 6 respectively by using an epitaxial growth method, which is a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method) that has been described in detail above and will not be described herein repeatedly. It should also be understood that the third epitaxial layer 8 and the fourth epitaxial layer 9 may be formed simultaneously or sequentially, and the heights of the third epitaxial layer 8 and the fourth epitaxial layer 9 may be the same or different, and are not limited herein. In this embodiment, the third epitaxial layer 8 and the fourth epitaxial layer 9 have the same height, and the height is between 3 to 4 um. Further, the material of the third epitaxial layer 8 and the fourth epitaxial layer 9 is also silicon, and they are both heavily doped materials, with a specific doping concentration between 2E15-5E15/cm 3.
Further, the second implantation region 10 is formed by ion implantation and/or diffusion on the surface of the fourth epitaxial layer 9, and the concentration of implanted ions is 4E15-5E15/cm 3. Further, the second injection region 10 is located in the upper surface region of the fourth epitaxial layer 9, and the upper surface of the second injection region 10 is partially overlapped with the upper surface of the fourth epitaxial layer 9, in this embodiment, the second injection region 10 includes a plurality of injection sub-regions distributed at intervals, the second injection region 10 and the fourth epitaxial layer 9 form a PN junction, and the ion concentration of the second injection region 10 can be conveniently adjusted through the injection sub-regions of the plurality of intervals, so that the breakdown voltage of a path where the second injection region 10 is located can be adjusted. In this embodiment, the second implantation region 10 specifically includes 3 implantation sub regions distributed at intervals.
Further, the third epitaxial layer 8 and the fourth epitaxial layer 9 are formed in the first trench 5 and the second trench 6 respectively by using an epitaxial growth method, which is a chemical vapor deposition method (or referred to as a vapor phase epitaxial growth method) that has been described in detail above and will not be described herein repeatedly. It should also be understood that the fifth epitaxial layer 11 and the sixth epitaxial layer 12 may be formed simultaneously or sequentially, and the heights of the fifth epitaxial layer 11 and the sixth epitaxial layer 12 may be the same or different, which is not limited herein. Further, the material of the fifth epitaxial layer 11 and the sixth epitaxial layer 12 is also silicon, and they are both heavily doped materials, with a specific doping concentration between 4E15-6E15/cm 3. Further, in order to obtain a complete plane and fill the first trench 5 and the second trench 6 with the fifth epitaxial layer 11 and the sixth epitaxial layer 12, respectively, after forming the fifth epitaxial layer 11 and the sixth epitaxial layer 12, the method further includes: the planarization operation is performed on the upper surfaces of the fifth epitaxial layer 11, the sixth epitaxial layer 12 and the second epitaxial layer 4, specifically, a chemical mechanical polishing manner is adopted, and the chemical mechanical polishing is a conventional means for those skilled in the art, and is not described herein again. Further, after forming the fifth epitaxial layer 11 and the sixth epitaxial layer 12, the method further includes: and activating the impurities of the first injection region 2, the second injection region 10 and other doped regions through a rapid thermal annealing process, and simultaneously diffusing the impurities of the sixth epitaxial layer 12 into the second epitaxial layers 4 at two sides to form shallow junctions 13 of the second conductivity type.
Further, specifically, the first front electrode 15 is electrically connected to the fifth epitaxial layer 11 through the dielectric layer 14, and the second front electrode 16 is electrically connected to the sixth epitaxial layer 12 through the dielectric layer 14. The first front electrode 15, the second front electrode 16 and the back electrode 17 may be formed simultaneously or sequentially, and if they are formed sequentially, the forming sequence therebetween is not limited. More specifically, the dielectric layer 14 is formed on the upper surface of the second epitaxial layer 4, and a first contact hole and a second contact hole are formed on the dielectric layer 14, wherein the first contact hole is located above the fifth epitaxial layer 11, and the second contact hole is located above the sixth epitaxial layer 12; a first front electrode 15 connected with the fifth epitaxial layer 11 and a second front electrode 16 connected with the sixth epitaxial layer 12 are deposited on the first contact hole, the second contact hole and the dielectric layer 14. The dielectric layer 14 is made of an insulating material and may be formed by sputtering or thermal oxidation.
Referring to fig. 2 and fig. 14 again, wherein fig. 14 is an equivalent circuit diagram of the transient voltage suppressor according to the embodiment of the invention, as shown, the fifth epitaxial layer 11 and the third epitaxial layer 8 form a first diode D1 with a fixed breakdown voltage, the first diode the first implanted region 2 and the second diode D2 with variable breakdown voltage formed between the first portion 31 and the first epitaxial layer 3 are connected in series, the first front electrode 15, the first diode D1, the second diode D2, and the back electrode 17 form a voltage-resistant circuit, the second implanted region 10 and the sixth epitaxial layer 12 form with the fourth epitaxial layer 9 a third diode D3 with a variable breakdown voltage, the second front electrode 16, the third diode D3, and the back electrode 17 form another voltage-resistant circuit.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of making a transient voltage suppressor, the method comprising:
forming a first implanted region of a second conductivity type in a surface region of a substrate of a first conductivity type;
forming a first epitaxial layer on the substrate, wherein the first epitaxial layer comprises a first part of a second conduction type and a second part of a first conduction type, and the first part covers the first injection region;
forming a second epitaxial layer of the first conductivity type on the first epitaxial layer;
forming a first trench in the second epitaxial layer above the first portion, forming a second trench in the second epitaxial layer above the second portion, the first and second trenches both penetrating the second epitaxial layer;
forming a side wall on the side wall of the first groove;
forming a third epitaxial layer of the first conductivity type and a fourth epitaxial layer of the first conductivity type in the first trench and the second trench, respectively, wherein the third epitaxial layer is connected with the first portion and has a height smaller than the depth of the first trench, and the fourth epitaxial layer is connected with the second portion and has a height smaller than the depth of the second trench;
forming a second implantation region of a second conductivity type in an upper surface region of the fourth epitaxial layer;
forming a fifth epitaxial layer of a second conductivity type and a sixth epitaxial layer of the second conductivity type on the third epitaxial layer and the fourth epitaxial layer, respectively, wherein the upper surfaces of the fifth epitaxial layer and the sixth epitaxial layer are aligned with the upper surface of the second epitaxial layer;
respectively forming a dielectric layer, a first front electrode, a second front electrode and a back electrode.
2. The method of claim 1, wherein forming a first epitaxial layer on the substrate specifically comprises:
growing an epitaxial layer of a first conductivity type on the surface of the substrate;
and injecting ions of a second conductive type into a partial region of the epitaxial layer to form the first part, wherein the other region of the epitaxial layer except the first part is the second part.
3. The method of claim 1, wherein the forming the dielectric layer, the first front electrode, the second front electrode, and the back electrode respectively comprises:
depositing the dielectric layer on the second epitaxial layer;
forming a first contact hole and a second contact hole on the dielectric layer, wherein the first contact hole is positioned above the fifth epitaxial layer, and the second contact hole is positioned above the sixth epitaxial layer;
depositing and forming a first front electrode connected with the fifth epitaxial layer and a second front electrode connected with the sixth epitaxial layer on the first contact hole, the second contact hole and the dielectric layer;
and forming a back electrode on the surface of the substrate far away from the first epitaxial layer.
4. The method of claim 1, wherein the first implant region is spaced apart from the top surface of the substrate.
5. The method of claim 1, wherein the second implanted region is spaced apart from the upper surface of the first epitaxial layer.
6. A transient voltage suppressor, comprising:
a substrate of a first conductivity type;
a first injection region of the second conductivity type formed in the substrate surface region;
a first epitaxial layer formed on the substrate, the first epitaxial layer including a first portion of a second conductivity type and a second portion of a first conductivity type, the first portion overlying the first implanted region;
a second epitaxial layer of the first conductivity type formed on the first epitaxial layer;
a first trench formed in the second epitaxial layer and above the first portion, and a second trench formed in the second epitaxial layer and above the second portion, the first and second trenches penetrating the second epitaxial layer;
a side wall formed on the side wall of the first groove;
a third epitaxial layer of the first conductivity type and a fourth epitaxial layer of the first conductivity type formed in the first trench and the second trench, respectively, the third epitaxial layer being connected to the first portion and having a height less than the depth of the first trench, the fourth epitaxial layer being connected to the second portion and having a height less than the depth of the second trench;
a second implantation region formed in an upper surface region of the fourth epitaxial layer;
a fifth epitaxial layer of a second conductivity type and a sixth epitaxial layer of a second conductivity type formed on the third epitaxial layer and the fourth epitaxial layer, the upper surfaces of the fifth epitaxial layer and the sixth epitaxial layer being aligned with the upper surface of the second epitaxial layer;
the device comprises a dielectric layer, a first front electrode, a second front electrode and a back electrode.
7. The transient voltage suppressor of claim 6, wherein said dielectric layer is formed on an upper surface of a second epitaxial layer, said dielectric layer having a first contact hole and a second contact hole formed therein, wherein said first contact hole is located above said fifth epitaxial layer and said second contact hole is located above said sixth epitaxial layer; and a first front electrode connected with the fifth epitaxial layer and a second front electrode connected with the sixth epitaxial layer are deposited on the first contact hole, the second contact hole and the dielectric layer.
8. The transient voltage suppressor of claim 6, wherein said first epitaxial layer further comprises said isolation layer, said isolation layer being formed between said first portion and said second portion.
9. The method of claim 6, wherein the first implant region is spaced apart from the top surface of the substrate.
10. The method of claim 6, wherein the second implanted region is spaced apart from the upper surface of the first epitaxial layer.
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