CN113130633B

CN113130633B - Groove type field effect transistor structure and preparation method thereof

Info

Publication number: CN113130633B
Application number: CN201911400665.0A
Authority: CN
Inventors: 姚鑫; 焦伟; 骆菲; 冉英
Original assignee: China Resources Microelectronics Chongqing Ltd
Current assignee: China Resources Microelectronics Chongqing Ltd
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2022-11-22
Anticipated expiration: 2039-12-30
Also published as: CN113130633A

Abstract

The invention provides a field effect transistor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, growing an epitaxial layer, forming a first groove and a second groove, preparing a shielding dielectric layer, a shielding grid isolating layer, a grid dielectric layer, a grid layer, a leading-out grid first dielectric layer, a first leading-out grid layer, a leading-out grid isolating layer, a leading-out grid second dielectric layer and a second grid layer, forming a body region and a source electrode, preparing a source electrode contact hole and a leading-out grid contact hole, and preparing a source electrode metal leading-out structure and a leading-out grid electrode structure. According to the invention, the grid lead-out structure is prepared in the region outside the device region, a wider second groove can be prepared, a light shield does not need to be added, and a thicker second lead-out grid layer (such as grid polycrystalline silicon) and a second medium layer (such as an oxide layer) of the lead-out grid between the epitaxial layer can be prepared, so that the breakdown voltage requirement of the device is met.

Description

Groove type field effect transistor structure and preparation method thereof

Technical Field

The invention belongs to the technical field of power semiconductors, and particularly relates to a trench type field effect transistor structure and a preparation method thereof.

Background

In the Field of medium and low voltage power MOSFETs (Metal Oxide Semiconductor Field Effect transistors), a shielded gate trench MOSFET has the advantages of lower on-resistance, faster switching speed and the like than a conventional trench MOSFET, has lower conduction loss and lower switching loss in system application, and has higher conversion and transmission efficiency. Because the shielding grid trench MOSFET introduces a shielding oxide layer and a shielding grid structure, and the shielding grid is required to be at the same potential as the source electrode of the device, the layout of the grid BUS and the shielding grid BUS is required to be considered during layout design, and the process manufacturing is complex.

However, in some shielded gate trench MOSFET devices, especially for low voltage (20V-60V) shielded gate trench MOSFET devices, if the gate lead-out structure is disposed in the cell region in the device terminal structure, the width of the cell region trench is small (0.3-0.4 um), the photolithography machine used in power device production in China can expose about 0.25um in minimum size, and the alignment accuracy of the photolithography machine is 70nm, then the gate contact hole is easily connected to the nearby source region, resulting in failure of the gate and source short device. And the device is in a blocking mode (the source electrode is in short circuit with the grid electrode and is connected with a low potential, and the drain electrode is connected with a high potential), the high potential of the drain electrode is directly added on the oxide layer between the grid electrode polycrystalline silicon and the epitaxial layer, and the thickness of the oxide layer between the grid electrode polycrystalline silicon and the epitaxial layer is required to be thickened structurally so as to meet the breakdown voltage requirement of the device. Therefore, how to prepare an effective gate lead-out structure becomes a manufacturing difficulty of the shielded gate trench MOSFET (particularly, a low-voltage shielded gate trench MOSFET) process.

Therefore, it is desirable to provide a trench field effect transistor structure and a method for fabricating the same to solve the above-mentioned problems in the prior art.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a trench field effect transistor structure and a manufacturing method thereof, which are used to solve the problem in the prior art that the thickness of an oxide layer between a pull-out gate layer and an epitaxial layer is difficult to meet the requirement.

In order to achieve the above and other related objects, the present invention provides a method for manufacturing a trench type field effect transistor structure, the method comprising:

providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate, wherein the epitaxial layer comprises a device region and a grid electrode leading-out region;

forming a first groove and a second groove, wherein the first groove is positioned in the device region, the second groove is positioned in the grid electrode leading-out region, and the opening size of the second groove is larger than that of the first groove;

forming a shielding grid dielectric layer, a shielding grid layer, a first lead-out grid dielectric layer and a first lead-out grid layer, wherein the shielding grid layer at least fills the bottom of the first groove, the shielding grid dielectric layer is formed between the inner wall of the first groove and the shielding grid layer, the first lead-out grid layer at least fills the bottom of the second groove, and the first lead-out grid dielectric layer is formed between the inner wall of the second groove and the first lead-out grid layer;

forming a shielding gate insulating layer on the shielding gate layer, wherein the shielding gate insulating layer is filled in the first groove, a lead-out gate insulating layer is formed on the first lead-out gate layer, and the lead-out gate insulating layer is filled in the second groove;

removing part of the shielding gate insulating layer to expose the side wall of the first groove, taking the rest shielding gate insulating layer on the shielding gate layer as a shielding gate isolating layer, removing part of the extraction gate insulating layer, and forming an extraction gate isolating layer on the first extraction gate layer and an extraction gate second dielectric layer on the side wall of the second groove, wherein the thickness of the extraction gate second dielectric layer is greater than or equal to that of the extraction gate first dielectric layer;

forming a gate dielectric layer on the exposed side wall of the first groove;

filling the first groove with a gate layer, and filling the second groove with a second extraction gate layer;

forming a body region between the adjacent first trenches and between the adjacent second trenches, and forming a source electrode in the body region, wherein the source electrode is adjacent to the first trenches;

and forming a gate layer metal leading-out structure, a second leading-out gate layer metal leading-out structure, a source electrode metal leading-out structure and a drain electrode metal leading-out structure.

Optionally, the removing a portion of the shielding gate insulating layer to expose the sidewall of the first trench, and the remaining shielding gate insulating layer on the shielding gate layer is used as a shielding gate isolation layer, and the removing a portion of the extraction gate insulating layer forms an extraction gate isolation layer on the first extraction gate layer and an extraction gate second dielectric layer on the sidewall of the second trench, and further includes:

forming a first opening in the shielding grid insulating layer, and forming a second opening in the leading-out grid insulating layer;

and removing part of the shielding grid insulating layer based on the first opening and removing part of the extraction grid insulating layer based on the second opening.

Optionally, forming the first opening and the second opening by using a dry etching process; and removing part of the shielding grid insulating layer and part of the leading-out grid insulating layer by adopting a wet etching process.

Optionally, the thickness of the second dielectric layer of the extraction gate is 1 to 1.5 times that of the first dielectric layer of the extraction gate; and/or the width of the second groove is between 2 and 4 times of the width of the first groove.

Optionally, the epitaxial layer further forms a termination region, the termination region is at least located between the device region and the gate lead-out region, a termination protection structure is formed in the termination region, and forming the termination protection structure includes:

forming a terminal groove;

forming a terminal first dielectric layer and a terminal shielding grid layer, wherein the terminal shielding grid layer is at least filled at the bottom of the terminal groove, and the terminal first dielectric layer is formed between the inner wall of the terminal groove and the terminal shielding grid layer;

forming a terminal isolation layer and a terminal second dielectric layer on the terminal shielding gate layer, wherein the terminal second dielectric layer is also positioned on the side wall of the terminal groove, and the thickness of the terminal second dielectric layer is greater than or equal to that of the terminal first dielectric layer;

forming a terminal gate layer on the surface of the terminal isolation layer and the surface of the terminal second dielectric layer, wherein the terminal gate layer is filled in the terminal groove;

and forming a terminal gate layer metal lead-out structure.

The invention also provides a trench field effect transistor structure, wherein the trench field effect transistor structure is preferably prepared by the preparation method of the trench field effect transistor structure provided by the invention, and certainly can also be prepared by other methods, wherein the trench field effect transistor structure comprises:

the semiconductor device comprises a semiconductor substrate, wherein an epitaxial layer is arranged on the semiconductor substrate and comprises a device region and a grid electrode leading-out region;

the first groove is arranged in the device region, the second groove is arranged in the grid electrode leading-out region, and the opening size of the second groove is larger than that of the first groove;

the shielding gate layer is at least arranged at the bottom of the first groove, and the shielding gate dielectric layer is arranged between the shielding gate layer and the inner wall of the first groove;

the grid layer is arranged in the first groove and positioned on the shielding grid layer, a shielding grid isolation layer is arranged between the grid layer and the shielding grid layer, and a grid dielectric layer is arranged between the grid layer and the side wall of the first groove;

the first extraction gate layer is at least arranged at the bottom of the second groove, and the first extraction gate dielectric layer is arranged between the first extraction gate layer and the inner wall of the second groove;

the second extraction grid layer is arranged in the second groove and positioned on the first extraction grid layer, an extraction grid isolation layer is arranged between the second extraction grid layer and the first extraction grid layer, and an extraction grid second dielectric layer is arranged between the second extraction grid layer and the side wall of the second groove;

the body region is arranged between the adjacent first trenches and between the adjacent second trenches, and the source electrode is formed in the body region and is adjacent to the first trenches;

the source metal lead-out structure is electrically connected with the body region and the source electrode, the lead-out gate metal lead-out structure is electrically connected with the second lead-out gate layer, and the drain metal lead-out structure is electrically connected with the semiconductor substrate.

Optionally, the width of the first opening is between 0.4 and 0.6 times the width of the first trench; the width of the second opening is between 0.4 and 0.6 times the width of the first trench.

Optionally, the depth of the first opening is 0.6 to 0.8 times the distance between the upper surface of the shield gate isolation layer and the upper surface of the epitaxial layer; the depth of the second opening is 0.6 to 0.8 times the distance between the upper surface of the extraction grid isolation layer and the upper surface of the epitaxial layer.

Optionally, the thickness of the second dielectric layer of the extraction gate is between 1 and 1.5 times of the thickness of the first dielectric layer of the extraction gate; the width of the second trench is between 2 to 4 times the width of the first trench.

Optionally, the epitaxial layer further includes a termination region, the termination region is at least located between the device region and the gate lead-out region, and the termination region is provided with a termination protection structure.

Optionally, the terminal protection structure includes:

a terminal groove, wherein a terminal shielding grid layer is at least arranged at the bottom of the terminal groove, and a terminal first dielectric layer is arranged between the terminal shielding grid layer and the inner wall of the terminal groove;

a terminal gate layer which is arranged in the terminal groove and positioned on the terminal shielding gate layer, wherein a terminal isolation layer is arranged between the terminal gate layer and the terminal shielding gate layer, a terminal second dielectric layer is arranged between the terminal gate layer and the side wall of the terminal groove, and the thickness of the terminal second dielectric layer is larger than or equal to that of the terminal first dielectric layer;

and the terminal gate layer metal lead-out structure is electrically connected with the terminal gate layer.

As described above, according to the trench field effect transistor structure and the manufacturing method thereof of the present invention, the gate lead-out structure is manufactured in the region outside the device region, so that the second trench with a wider width can be manufactured, a photomask does not need to be added, and the second dielectric layer (e.g., oxide layer) of the lead-out gate between the second lead-out gate layer (e.g., gate polysilicon) and the epitaxial layer with a thicker thickness can be manufactured, thereby meeting the breakdown voltage requirement of the device.

Drawings

FIG. 1 is a flow chart of a process for fabricating a trench field effect transistor structure according to the present invention.

Fig. 2 is a layout diagram of a trench field effect transistor structure according to an embodiment of the present invention.

Fig. 3-15 are schematic cross-sectional views of devices obtained at steps associated with a method of fabricating a trench fet structure in accordance with an embodiment of the present invention.

Description of the element reference numerals

100. Semiconductor substrate

101. Epitaxial layer

101a device region

101b gate lead-out region

101c terminal region

102. First trench

103. Second trench

104. Terminal trench

105. Dielectric material layer

106. Layer of shielding grid material

107. Shielding gate layer

108. First lead-out gate layer

109. Terminal shielding grid layer

110. Shielding dielectric layer

111. First medium layer of extraction grid

112. Terminal first dielectric layer

113. Shielding gate insulating layer

114. Lead-out gate insulating layer

115. Terminal gate insulating layer

116. First mask layer

117. Second mask layer

118. Shielding gate isolation layer

119. Extraction grid isolation layer

120. Lead-out grid second dielectric layer

121. Terminal isolation layer

122. Terminal second dielectric layer

123. Gate dielectric layer

124. Layer of gate material

125. Grid layer

126. Second extraction grid layer

127. Terminal gate layer

128. Source implantation mask

129. Body region

130. Source electrode

131. Isolation dielectric layer

131a source contact hole

131b leading-out gate contact hole

131c terminal gate contact hole

132. Source metal leading-out structure

133. Second lead-out grid metal lead-out structure

134. Drain metal leading-out structure

S1 to S9

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Spatially relative terms, such as "under," "below," "lower," "below," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 1 to 15, the present invention provides a method for manufacturing a trench field effect transistor structure, comprising the steps of:

forming a gate dielectric layer on the exposed side wall of the first groove;

forming body regions between the adjacent first trenches and between the adjacent second trenches, and forming source electrodes in the body regions, wherein the source electrodes are adjacent to the first trenches;

and forming a gate layer metal lead-out structure, a second lead-out gate layer metal lead-out structure, a source electrode metal lead-out structure and a drain electrode metal lead-out structure.

The following describes the preparation of the trench fet structure according to the present invention in detail with reference to the drawings. Wherein FIG. 3 is shown as; forming a schematic diagram of a first groove, a second groove and a terminal groove; FIG. 4 is a schematic diagram illustrating the formation of a dielectric material layer and a shielding gate material layer; FIG. 5 is a schematic diagram of forming a shield gate layer, a first extraction gate layer, and a termination shield gate layer; FIG. 6 is a schematic diagram of a shield dielectric layer, a first dielectric layer of a lead-out gate, and a first dielectric layer of a terminal; FIG. 7 is a schematic view showing the formation of a shield gate insulating layer, a lead-out gate insulating layer, and a terminal gate insulating layer; FIG. 8 is a schematic diagram of forming a first etch opening, a second etch opening, and a third etch opening; FIG. 9 is a schematic view illustrating the formation of a first opening, a second opening, and a third opening; FIG. 10 is a schematic view showing the formation of a shield gate isolation layer, a lead-out gate second dielectric layer, a terminal isolation layer, and a terminal second dielectric layer; FIG. 11 illustrates a schematic diagram of forming a gate material layer; FIG. 12 is a schematic diagram showing the formation of a gate layer, a second extraction gate layer, and a termination gate layer; FIG. 13 is a schematic diagram illustrating the formation of a body region and a source region; FIG. 14 is a schematic view showing the formation of source contact holes, lead-out gate contact holes, and terminal contact holes; fig. 15 is a schematic diagram showing the formation of a second extraction gate layer metal extraction structure, a source metal extraction structure, and a drain metal extraction structure.

As shown in S1 and S2 of fig. 1 and fig. 2-3, providing a semiconductor substrate 100, and forming an epitaxial layer 101 on the semiconductor substrate 100, wherein the epitaxial layer 101 includes a device region 101a and a gate lead-out region 101b; and forming a first trench 102 in the device region, and forming a second trench 103 in the gate lead-out region, wherein the opening size of the second trench 103 is larger than that of the first trench 102.

Specifically, the semiconductor substrate 100 may be a substrate of a first doping type, where the first doping type (i.e., the first conductivity type) may be P-type doping or N-type doping, and may be the semiconductor substrate 100 formed by implanting ions of the first doping type (P-type or N-type) into an intrinsic semiconductor substrate by an ion implantation process, where the specific type is set according to actual device requirements, in this example, the first doping type is selected to be an N-type doping substrate, and in addition, in one example, the first doping type may be a heavily doped substrate, for example, the concentration of the ions of the first doping type doped in the semiconductor substrate 100 may be greater than or equal to 1 × 10 ¹⁹ /cm ³ . Note that the semiconductor substrate 100 may be a silicon substrate or a silicon germanium substrateA base, a silicon carbide substrate, etc., in this example, the semiconductor substrate 100 is selected to be N ⁺⁺ A type-doped silicon substrate, such as may be 0.001-0.003ohm cm. The first doping type and the subsequently mentioned second doping type (i.e. the second conductivity type) are opposite doping (conductivity) types, and when the first doping type (the first conductivity type) semiconductor is an N-type semiconductor and the second doping type (the second conductivity type) semiconductor is a P-type semiconductor, the trench MOSFET device of the present invention is an N-type device; conversely, the trench MOSFET device of the present invention is a P-type device.

In addition, in an example, a doping type of the epitaxial layer 101 is the same as a doping type of the semiconductor substrate 100, and in an optional example, a doping concentration of the epitaxial layer 101 is lower than a doping concentration of the semiconductor substrate 100, wherein an epitaxial process may be first used to form a characteristic epitaxial layer on an upper surface of the semiconductor substrate 100 of the first doping type, and then ions of the first doping type are implanted into the intrinsic epitaxial layer through an ion implantation process to form the epitaxial layer 101 of the first doping type; in another example, the epitaxial layer 101 of the first doping type may also be epitaxially formed directly on the upper surface of the semiconductor substrate 100 of the first doping type using an epitaxial process. In this example, the epitaxial layer 101 is selected to be an N-type single crystal silicon epitaxial layer.

Specifically, the first trench 102 and the second trench 103 may be formed by photolithography and etching processes, and optionally, both may be prepared based on the same mask, wherein the second trench 103 is prepared in the gate lead-out region 101b, that is, in a region outside the device region 101a, so that the width of the trench of the gate lead-out structure may be increased without being limited by charge balance limitation in a cell region, so as to match with exposure capability of a photolithography machine and alignment precision of a photolithography machine, if the gate lead-out structure is arranged in the cell region in a device termination structure, the width of the trench of the cell region is small (0.3-0.4 um), the photolithography machine can expose a minimum size of about 0.25um, and the alignment precision of the photolithography machine is 70nm, so that a gate contact hole is easily connected to a nearby source region, which may cause failure of a gate and source shorting device, and the second trench 103 (used for subsequently preparing the gate lead-out structure) is prepared in the region outside the device region 101a, so that the second trench 103 may be made wide, and it may be beneficial to further increase the thickness of an oxide layer between the gate lead-out layer and the epitaxial layer. In an alternative example, the width of the second trench 103 is between 2 and 4 times the width of the first trench 102, and may be selected to be 2.5 times, 3 times or 3.5 times. In addition, the number and the arrangement relationship of the first trenches 102 and the second trenches 103 are set according to practical situations, for example, the number may be a plurality of first stripe-shaped trenches 102 arranged in parallel at intervals and a plurality of second stripe-shaped trenches 103 arranged in parallel at intervals.

As shown in S3 in fig. 1 and fig. 4-6, a shielding gate dielectric layer 110, a shielding gate layer 107, a first extraction gate dielectric layer 111, and a first extraction gate layer 108 are formed, where the shielding gate dielectric layer 110 is formed on an inner wall of the first trench 102, the shielding gate layer 107 is formed on a surface of the shielding gate dielectric layer 110, and the shielding gate layer 107 at least fills a bottom of the first trench 102, that is, the shielding gate dielectric layer 110 is formed between the inner wall of the first trench 102 and the shielding gate layer 107; forming a first extraction gate dielectric layer 111 on the inner wall of the second trench 103, forming a first extraction gate layer 108 on the surface of the first extraction gate dielectric layer 111, wherein the first extraction gate layer 108 at least fills the bottom of the second trench 103, that is, the first extraction gate dielectric layer 111 is formed between the inner wall of the second trench 103 and the first extraction gate layer 108.

As an example, the steps of forming the shielding gate dielectric layer 110, the shielding gate layer 107, the extraction gate first dielectric layer 111, and the first extraction gate layer 108 include:

as shown in fig. 4, a continuous dielectric material layer 105 is formed on the inner walls of the first trench 102, the inner walls of the second trench 103, and the epitaxial layer 101 around the first trench 102 and the second trench 103. In an optional example, the dielectric material layer 105, that is, the thicknesses of the obtained shielding dielectric layer 110 and the first dielectric layer 111 of the extraction gate may be between 800 angstroms and 9000 angstroms to achieve a good shielding effect, such as 1000 angstroms, 2000 angstroms, 8000 angstroms, and the like.

With continued reference to fig. 4, a continuous shielding gate material layer 106 is formed on the surface of the dielectric material layer 105, and the shielding gate material layer 106 fills the first trench 102 and the second trench 103. The shielding gate material layer 106 may be formed by filling the trench formed on the surface of the dielectric material layer 105 with a physical vapor deposition process, a chemical vapor deposition process, and the like, where the material of the shielding gate material layer 106 may include, but is not limited to, polysilicon.

As shown in fig. 5, the shielding gate material layer 106 is etched back to form the shielding gate layer 107 in the first trench 102 and the first extraction gate layer 108 in the second trench 103. The back etching may be performed on the shielding gate material layer 106 by using a dry etching process or a wet etching process, and the depth of the etched shielding gate material layer 106, that is, the heights of the obtained shielding gate layer 107 and the first extraction gate layer 108 may be set according to actual requirements. As shown in fig. 6, the dielectric material layer 105 on the outer wall of the shielding gate layer 107 forms the shielding gate dielectric layer 110, and the dielectric material layer 105 on the outer wall of the first extraction gate layer 108 forms the extraction gate first dielectric layer 111.

As shown in S4 in fig. 1 and fig. 6 to 7, a shielding gate insulating layer 113 is formed on the shielding gate layer 107, the shielding gate insulating layer 113 is filled in the first trench 102, an extraction gate insulating layer 114 is formed on the first extraction gate layer 108, and the extraction gate insulating layer 114 is filled in the second trench 103. Wherein, in an example, a layer of insulating material, including but not limited to silicon oxide, may be deposited in and around the first trench 102 on the shield gate layer 107 and in and around the second trench 103 on the first pull-out gate layer 108 by a process including but not limited to High Density Plasma (HDP) deposition. And forming the shielding gate insulating layer 113 and the extraction gate insulating layer 114 by chemical mechanical polishing, in an example, upper surfaces of the shielding gate insulating layer 113 and the extraction gate insulating layer 114 are flush with an upper surface of the epitaxial layer 101.

As shown in S5 in fig. 1 and fig. 7 to 10, removing a portion of the shielding gate insulating layer 113 to expose a portion of the sidewall of the first trench 102, and using the remaining shielding gate insulating layer 113 on the shielding gate layer 107 as a shielding gate isolation layer 118, removing a portion of the extraction gate insulating layer 114, and forming an extraction gate isolation layer 119 on the first extraction gate layer 108 and an extraction gate second dielectric layer 120 on the sidewall of the second trench 103, where the thickness of the extraction gate second dielectric layer 120 is greater than or equal to the thickness of the extraction gate first dielectric layer 108.

As shown in fig. 9 to 10, the step of forming the shielding gate isolation layer 118, the extraction gate isolation layer 119, and the extraction gate second dielectric layer 120 includes, for example:

forming a first opening 113a in the shielding gate insulating layer 113, and forming a second opening 114a in the extraction gate insulating layer 114; and removing a portion of the shielding gate insulating layer 113 based on the first opening 113a, and removing a portion of the extraction gate insulating layer 114 based on the second opening 114a. In an example, the first opening 113a and the second opening 114a are formed by a dry etching process; and removing part of the shielding gate insulating layer 113 and part of the extraction gate insulating layer 114 by adopting a wet etching process.

In a specific embodiment, the specific steps may include: first, as shown in fig. 9, a first opening 113a is formed in the shielding gate insulating layer 113, and a second opening 114a is formed in the lead-out gate insulating layer 114;

then, as shown in fig. 10, the shield gate insulating layer 113 is etched based on the first opening 113a to form the shield gate isolation layer 118, the extraction gate insulating layer 114 is etched based on the second opening 114a to form the extraction gate isolation layer 119 and the extraction gate second dielectric layer 120, wherein a gate trench is formed on the surfaces of the extraction gate isolation layer 119 and the extraction gate second dielectric layer 120, wherein the shield gate isolation layer 118, the extraction gate isolation layer 119 and the extraction gate second dielectric layer 120 may be formed by a wet etching process based on the first opening 113a and the second opening 114a, in an example, the material layer on the sidewall of the first trench 102 is completely removed, meanwhile, the extraction gate insulating layer 114 on the sidewall of the second trench 103 is partially retained during the wet etching process to form the extraction gate second dielectric layer 120, in an example, the thickness of the extraction gate second dielectric layer 120 is greater than the thickness of the extraction gate first trench 108, as an example, the extraction gate second dielectric layer 120 is thickened to form a high-potential extraction gate device with a thickness that is 1.5 times the thickness required for forming a gate structure between the source electrode layer and the drain electrode layer, and the high-drain electrode layer, thereby increasing the thickness of the extraction gate oxide layer formed by a high-drain electrode structure The scheme of the invention can effectively solve the problem of thickening of the oxide layer.

As an example, the width of the first opening 113a is between 0.4 and 0.6 times, may be 0.4 times, 0.45 times, 0.5 times, etc. of the width of the first trench 102, and the width of the second opening 114a is between 0.4 and 0.6 times, may be 0.4 times, 0.45 times, 0.5 times, etc. of the width of the first trench 102, and preferably, the widths of the first opening 113a and the second opening 114a are equal, so as to facilitate obtaining the shield gate isolation layer 118, the extraction gate isolation layer 119, and the extraction gate second dielectric layer 120.

As shown in fig. 7 to 9, the step of forming the first opening 113a and the second opening 114a includes, as an example:

as shown in fig. 7, a first mask layer 116 is formed on the surface of the structure where the shielding gate insulating layer 113 and the extraction gate insulating layer 114 are formed, where the first mask layer 116 may be a hard mask dielectric layer, such as a silicon nitride or polysilicon material layer.

With reference to fig. 7, a second mask layer 117 having a first opening 117a and a second opening 117b is formed on the first mask layer 116, the first opening 117a and the second opening 117b both expose the first mask layer 116, the first opening 117a correspondingly exposes a portion of the shielding gate insulating layer 113, and the second opening 117b correspondingly exposes a portion of the extraction gate insulating layer 114, where correspondingly exposing means that the exposed portion of the first opening 117a corresponds to a region of the shielding gate insulating layer 113 where the first opening 113a needs to be formed, and the exposed portion of the second opening 117b corresponds to a region of the extraction gate insulating layer 114 where the second opening 114a needs to be formed, where the second mask layer 117 may be a photoresist layer and may be formed on the first mask layer 116 by an exposure and development process.

As shown in fig. 8, the first opening 117a and the second opening 117b are transferred onto the first mask layer 116, so as to form a first etching opening 116a and a second etching opening 116b on the first mask layer 116, wherein the first etching opening 116a and the second etching opening 116b can be formed by using a dry etching process.

As shown in fig. 9, the first opening 113a is formed in the shielding gate insulating layer 113 based on the first etching opening 116a, and the second opening 114a is formed in the extraction gate insulating layer 114 based on the second etching opening 116b. The first opening 113a and the second opening 114a may be formed by a dry etching process, and the etching depth may be designed according to the requirement of the device. As an example, the distance between the bottom of the first opening 113a and the upper surface of the epitaxial layer 101 (the depth of the first opening 113 a) is 0.6-0.8 times, and may be 0.65 times, 0.7 times, 0.75 times, etc., the distance between the upper surface of the shield gate isolation layer 118 and the upper surface of the epitaxial layer; the distance between the bottom of the second opening 114a and the upper surface of the epitaxial layer 101 (the depth of the second opening 114 a) is between the upper surface of the extraction gate isolation layer 119, that is, the bottom of the extraction gate trench is 0.6-0.8 times, which may be 0.65 times, 0.7 times, 0.75 times, etc. the distance between the bottom of the extraction gate trench and the upper surface of the epitaxial layer 101 may be controlled by controlling the wet etching conditions, in one example, the shielding gate isolation layer 118 is flush with the upper surface of the extraction gate isolation layer 119, and the distance between the upper surface of the isolation dielectric layer 118 and the upper surface of the epitaxial layer 101 is 5000-10000 angstroms, which may be 6000 angstroms or 8000 angstroms, etc. Based on the above process of the present invention, the first opening 113a and the second opening 114a are formed by transferring based on the second mask layer 117, so that a mask is not required to be added, and the first mask layer 116 is formed and selected as a hard mask, thereby being beneficial to protecting the material layer on the top from being damaged in the wet etching process based on the first opening 113a and the second opening 114a, and being beneficial to obtaining a stable structure.

As shown in S6 and S7 in fig. 1 and fig. 11 to 12, a gate dielectric layer 123 is formed on the shielding gate isolation layer 118 and on the exposed sidewall of the first trench 102, in an example, the thickness of the gate dielectric layer is smaller than the thickness of the shielding gate dielectric layer, a gate layer 125 is formed by filling the first trench 102, and a second extraction gate layer 126 is formed by filling the second trench 103, wherein the gate dielectric layer 123 may be grown by a thermal oxidation process, of course, an oxide layer may be formed on the extraction gate isolation layer 119 and the inner wall of the gate trench formed by the extraction gate second dielectric layer 120 based on the thermal oxidation process, the gate dielectric layer 123 includes, but is not limited to, a silicon oxide layer, in an example, the first mask layer 116 may be etched by a dry or wet etching process before forming the gate dielectric layer 123, in addition, a gate material layer including, but not limited to, may be deposited on the surface of the gate dielectric layer 123 and in the gate trench by a chemical vapor deposition process, and then etched back to form the gate layer 125 and the extraction gate layer 126, and optionally, the surface of the extraction gate layer 125 and the surface of the extraction gate layer 126 are lower than the gate layer 101.

As shown in S8 of fig. 1 and fig. 13, a body region 129 is formed between the adjacent first trenches 102 and between the adjacent second trenches 103, and a source 130 is formed in the body region 129, wherein the source 130 is adjacent to the first trenches 102; the body region 129 is adjacent to both the first trench 102 and the second trench 103, in an example, the doping type of the body region 129 is opposite to the doping types of the epitaxial layer 101 and the semiconductor substrate 100, the body region 129 has the second doping type, and in this example, the body region 129 is selected to be P-type lightly doped. In an example, after the gate layer 125 and the second extraction gate layer 126 are formed, ion implantation may be directly performed to form the body region 129, so that a mask layer does not need to be prepared, in an alternative example, the lower surface of the body region 129 is higher than the bottoms of the first trench 102 and the second trench 103, a height difference exists between the bottom of the body region 129 and the bottoms of the two trenches, and in addition, in an example, a step of performing high temperature annealing after the ion implantation is further included to form the body region 129, where an implantation dose may be adjusted according to performance parameters of a device, such as a threshold voltage, a breakdown voltage, and the like. In addition, after the body region 129 is formed, a source implantation mask 128 is further prepared on the epitaxial layer 101, the source implantation mask 128 may shield a position where a source is not required to be formed, in an example, the source implantation mask 128 shields the gate lead-out region 101b, in addition, a terminal structure region of a device may also be shielded, and an active region is exposed, so that the source 130 is obtained by performing ion implantation based on the active region, in addition, an ion doping type of the source 130 may be the same as a doping type of the epitaxial layer 101 and the semiconductor substrate 100, and is opposite to a doping type of the body region 129, in this example, the source 129 is selected to be N + type doped silicon. In one example, the lower surface of the source 130 is lower than the upper surface of the gate layer 125.

As shown in S9 in fig. 1 and fig. 14 to 15, a gate layer metal extraction structure (not shown), a second extraction gate layer metal extraction structure 133, a source metal extraction structure 132, and a drain metal extraction structure 134 are formed.

In a specific example, the forming of the metal lead-out structure includes:

at least a source contact hole 131a is formed in the source 130, the source contact hole 131a penetrates through the source 130 and exposes the body region 129, and an extraction gate contact hole 131b exposing the second extraction gate layer 126 is formed in the second extraction gate layer 126; the source contact hole 131a also extends into the body region 129, so as to facilitate electrical extraction of the body region 129.

As an example, the forming of the source 130 further includes: forming an isolation dielectric layer 131 on the epitaxial layer 101, and forming a window on the isolation dielectric layer 131, wherein the window defines positions of the source contact hole 131a and the extraction gate contact hole 131b, the source contact hole 131a and the extraction gate contact hole 131b are formed based on the window, and the source metal extraction structure 132 and the extraction gate electrode structure 133 are formed on the surface of the isolation dielectric layer 131. The isolation dielectric layer 131 may be formed by using processes such as chemical vapor deposition, the isolation dielectric layer 131 may be made of a material including, but not limited to, silicon oxide, and the isolation dielectric layer 131 may be etched first and then etched to form the subsequent source contact holes 131a and 131b based on two etching processes.

As an example, the forming of the source contact hole 131a further includes: the body region 129 is ion implanted based on the source contact hole 131a to form a doped contact region in the body region 129, as shown by the dotted area below the source contact hole 131a in fig. 15, the doping type of the doped contact region is the same as that of the body region 129, and the doped contact region is in contact with the source metal extraction structure 132. In an example, ion implantation is performed based on the source contact hole 131a, the doped contact region is formed on the surface of the body 129 region exposed to the source contact hole 131a, the doping type of the doped contact region is consistent with the doping type of the body region 129, in an example, the doping concentration of the doped contact region is greater than the doping concentration of the body region 129, and in this embodiment, P + type doping is selected to reduce contact resistance.

After the source contact hole 131a and the extraction gate contact hole 131b are formed, a source metal extraction structure 132 electrically connected to both the source 130 and the body 129 is formed at least in the source contact hole 131a so as to be electrically extracted therefrom, and a second extraction gate metal extraction structure 133 electrically connected to the second extraction gate layer 126 is formed at least in the extraction gate contact hole 131b so as to electrically extract the second extraction gate layer 126 and connect the second extraction gate layer 126 to a gate pad through a gate BUS, and a drain metal extraction structure 134 electrically connected to the semiconductor substrate 100 is formed on a side of the semiconductor substrate 100 away from the epitaxial layer 101 so as to serve as a drain extraction terminal, and the semiconductor substrate 100 serves as a drain. The material of the source metal lead-out structure 132, the second lead-out gate electrode structure 133, and the drain metal lead-out structure 134 may be aluminum, or may be formed by depositing ALCU (aluminum copper) or AISICU (aluminum silicon copper), but is not limited thereto.

In addition, as shown in fig. 3 to 15, the epitaxial layer 101 further forms a termination region 101c, where the termination region 101c is at least located between the device region 101a and the gate lead-out region 101c, and the forming of the termination protection structure in the termination region 101c includes:

forming a termination trench 104, in one example, forming the first trench 102 and the second trench 103 while forming a termination trench 104 in the termination region 101c, in an alternative example, an opening size of the termination trench 104 is larger than an opening size of the first trench 102, and an opening size of the termination trench 104 is equal to an opening size of the second trench 103; in another example, the opening size of the second trench 103 is larger than the opening size of the terminal trench 104 and larger than the opening size of the first trench 102;

forming a terminal first dielectric layer 112 and a terminal shielding gate layer 109, forming the terminal first dielectric layer 112 on the inner wall of the terminal trench 104, forming the terminal shielding gate layer 109 on the surface of the terminal first dielectric layer 112, filling the terminal shielding gate layer 109 at least at the bottom of the terminal trench 104, and preparing the terminal shielding gate layer 109 and the shielding gate dielectric layer 110 based on the same process;

forming a terminal isolation layer 121 and a terminal second dielectric layer 122 on the terminal shielding gate layer 109, where the thickness of the terminal second dielectric layer 122 is greater than or equal to the thickness of the terminal first dielectric layer 112, and the terminal second dielectric layer 122 is also located on the sidewall of the terminal trench 104, and may be prepared based on the same process as the extraction gate isolation layer 119 and the extraction gate second dielectric layer 120, including a step of forming a terminal insulating layer 115, a third opening 117c, a third etching opening 116c, and a third opening 115 a;

forming a terminal gate layer 127 on the surfaces of the terminal isolation layer 121 and the terminal second dielectric layer 122, wherein the terminal gate layer 127 is filled in the terminal trench 104, and can be prepared on the basis of the same process as the second extraction gate layer 126; forming a terminal lead-out hole 131c in the terminal gate layer 127, which may be prepared on the same process as the lead-out gate contact hole 131b;

a terminal gate layer metal lead-out structure is formed, in an example, the terminal gate layer metal lead-out structure may share the same metal lead-out structure with the source metal lead-out structure 132, and optionally, a terminal gate metal lead-out structure electrically connected to the terminal gate layer 127 is formed at least in the terminal lead-out hole 131c, where the terminal gate metal lead-out structure may be prepared based on the same process as the source metal lead-out structure 132, and may be prepared based on the same process as the lead-out gate electrode structure 133 to form the same metal lead-out structure layer, and in an example, the terminal gate metal lead-out structure and the source metal lead-out structure 132 are insulated from the second lead-out gate metal lead-out structure 133 by an etching process.

As shown in fig. 15, referring to fig. 1 to 14, the present invention further provides a trench field effect transistor structure, wherein the trench field effect transistor structure is preferably prepared by using the preparation method of the trench field effect transistor structure provided by the present invention, and of course, may also be prepared by using other methods, and the description of the related structure of the present invention may refer to the above description of this embodiment, where the trench field effect transistor structure includes:

a semiconductor substrate 100, wherein the semiconductor substrate 100 may be a substrate of a first doping type, and the first doping type (i.e. the first conductivity type) may be a P-type doping or an N-type doping, and in this example, is selected to be an N-type doping substrate, and in addition, in an example, may be a heavily doped substrate, such as a substrate in which the concentration of the ions of the first doping type doped in the semiconductor substrate 100 is 1 × 10 or more ¹⁹ /cm ³ . The semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or the like.

An epitaxial layer 101 formed on the semiconductor substrate 100, in an example, a doping type of the epitaxial layer 101 is the same as a doping type of the semiconductor substrate 100, in an optional example, a doping concentration of the epitaxial layer 101 is lower than a doping concentration of the semiconductor substrate 100, wherein the epitaxial layer 101 includes a device region 101a and a gate lead-out region 101b, a first trench 102 is formed in the device region 101a, a second trench 103 is formed in the gate lead-out region 101c, and a width of the second trench 103 is greater than a width of the first trench;

the second trench 103 is prepared in the gate lead-out region 101b, that is, in the region outside the device region 101a, so that the limitation of charge balance in the cell region is not limited, the width of the trench of the gate lead-out structure can be increased to match the exposure capability of the lithography machine and the alignment precision of the lithography machine, if the gate lead-out structure is arranged in the cell region in the device terminal structure, the width of the trench of the cell region is small (0.3-0.4 um), the minimum exposure size of the lithography machine is about 0.25um, and the alignment precision of the lithography machine is 70nm, the gate contact hole is easily connected to the nearby source region to cause the failure of the gate and source short-circuit device, the second trench 103 (used for subsequently preparing the gate lead-out structure) is prepared in the region outside the device region 101a, the second trench 103 can be made wide, and the subsequent increase of the thickness of the oxide layer between the lead-out gate and the epitaxial layer can be facilitated. In an alternative example, the width of the second trench 103 is between 2 and 4 times the width of the first trench 102, and may be selected to be 2.5 times, 3 times or 3.5 times. In addition, the number and the arrangement relationship of the first trenches 102 and the second trenches 103 are set according to actual situations, for example, the number and the arrangement relationship may be a plurality of strip-shaped first trenches 102 arranged in parallel at intervals and a plurality of strip-shaped second trenches 103 arranged in parallel at intervals.

A shielding gate dielectric layer 110 and a leading-out gate first dielectric layer 111, which are made of materials including but not limited to silicon oxide layers, are respectively formed on the inner walls of the first trench 102 and the second trench 103; the thickness of the shielding layer can be between 800 angstroms and 9000 angstroms to achieve good shielding effect, such as 1000 angstroms, 2000 angstroms, 8000 angstroms, etc.

A shielding gate layer 107 and a first extraction gate layer 108, which are made of materials including but not limited to polysilicon, are respectively formed on the surfaces of the shielding gate dielectric layer 110 and the extraction gate first dielectric layer 111, the shielding gate layer 107 is filled at the bottom of the first trench 102, and the first extraction gate layer 108 is filled at the bottom of the second trench 103;

a shield gate isolation layer 118 formed on the shield gate layer 107 exposing sidewalls of the first trench 102 above the shield gate layer 107, and the material thereof includes but is not limited to silicon oxide.

In an example, the extraction gate isolation layer 119 and the extraction gate second dielectric layer 120 are integrated and formed on the same material layer, the material of the extraction gate isolation layer 119 and the extraction gate second dielectric layer 120 includes but is not limited to silicon oxide, and the thickness of the extraction gate second dielectric layer 120 is larger than that of the extraction gate first dielectric layer 108, so that the material layer can be thickened based on the scheme of the invention, that is, the thickness of the oxide layer between the subsequent second extraction gate layer formed in the extraction gate trench and the epitaxial layer is increased, so that the thickness of the oxide layer is increased under the condition that the gate extraction structure is prepared outside a device region, wherein the device is in a blocking mode (a source electrode is in short circuit with a gate electrode and is connected with a low potential, a drain electrode is connected with a high potential), the high potential is directly added on the gate oxide layer between the gate electrode and the high potential, and the polysilicon oxide layer is thickened to meet the requirement of the device for effective voltage breakdown of the device. As an example, the thickness of the extraction gate second dielectric layer 120 is between 1 to 1.5 times the thickness of the extraction gate first dielectric layer 108, and may be 1.2 times.

A gate dielectric layer 123 formed on the shielding isolation layer 118 and the exposed sidewall of the first trench 102, wherein the thickness of the gate dielectric layer 123 is smaller than that of the shielding gate dielectric layer 107;

a gate layer 125 and a second extraction gate layer 126, which are made of materials including but not limited to polysilicon, wherein the gate layer 125 is formed on the surface of the gate dielectric layer 123 and filled in the first trench 102, the second extraction gate layer 126 is filled in the extraction gate trench, and an extraction gate contact hole 131b exposing the second extraction gate layer is formed in the second extraction gate layer 126;

a body region 129 and a source electrode 130, wherein the body region 129 is formed between the adjacent first trenches 102 and between the adjacent second trenches 103, the source electrode 130 is formed in the body region 129 between the first trenches 102 and adjacent to the first trenches 102, and a source contact hole 131a penetrating through the source electrode 130 and exposing the body region 129 is formed in the source electrode 130; in an example, the doping type of the body region 129 is opposite to the doping types of the epitaxial layer 101 and the semiconductor substrate 100, the body region 129 has the second doping type, and in this example, the body region 129 is selected to be P-type lightly doped. In addition, the ion doping type of the source 130 may be the same as the doping type of the epitaxial layer 101 and the semiconductor substrate 100, and is opposite to the doping type of the body region 129, in this example, the source 129 is selected to be N + -doped silicon.

The source metal leading-out structure 132, the second leading-out gate metal leading-out structure 133 and the drain metal leading-out structure 134 are arranged in the source contact hole 131a, the source metal leading-out structure 132 is at least filled in the source contact hole 131a and is electrically connected with the source 130 and the body region 120, the second leading-out gate metal leading-out structure 133 is at least filled in the leading-out gate contact hole 131b and is electrically connected with the second leading-out gate layer 126, the drain metal leading-out structure 134 is formed on one side, away from the epitaxial layer, of the semiconductor substrate and is electrically connected with the semiconductor substrate 100, and the semiconductor substrate 100 serves as a drain of a device.

As an example, an isolation dielectric layer 131 is further formed on the epitaxial layer 101, a window corresponding to the source contact hole 131a and the extraction gate contact hole 131b is formed in the isolation dielectric layer 131, the source metal extraction structure 132 is filled in the source contact hole and extends to be formed on the surface of the isolation dielectric layer 131, and the extraction gate electrode structure 133 is filled in the extraction gate contact hole 131b and extends to be formed on the surface of the isolation dielectric layer 131.

As an example, the trench fet structure further includes a doped contact region, which is formed at the bottom of the source contact hole 131a and contacts the source metal lead-out structure 132, and the doping type of the doped contact region is consistent with that of the body region 129.

As an example, the width of the second trench is between 2-4 times the width of the first trench, and may be selected to be 2.5 times, 3 times, or 3.5 times.

As an example, the epitaxial layer 101 further includes a termination region 101c, where the termination region 101c is at least located between the device region 101a and the gate lead-out region 101c, and the termination region is provided with a termination protection structure.

In an optional example, the terminal protection structure includes: a termination trench 104, where at least a bottom of the termination trench 104 is provided with a termination shielding gate layer 109, and a termination first dielectric layer 112 is provided between the termination shielding gate layer 109 and an inner wall of the termination trench 104, where the termination trench 104 is located in the termination region 101c, in an optional example, an opening size of the termination trench 104 is larger than an opening size of the first trench 102, and an opening size of the termination trench 104 is equal to an opening size of the second trench 103; in another example, the opening size of the second trench 103 is larger than the opening size of the terminal trench 104 and larger than the opening size of the first trench 102;

a terminal gate layer 127 disposed in the terminal trench 104 and on the terminal shielding gate layer 112, wherein a terminal isolation layer 121 is disposed between the terminal gate layer 127 and the terminal shielding gate layer 109, a terminal second dielectric layer 122 is disposed between the terminal gate layer 127 and a sidewall of the terminal trench 104, and a thickness of the terminal second dielectric layer 122 is greater than or equal to a thickness of the terminal first dielectric layer 112;

a terminal gate layer metal lead-out structure electrically connected to the terminal gate layer 127 in one example, the terminal gate layer metal lead-out structure may share the same metal lead-out structure as the source metal lead-out structure 132, optionally, a terminal lead-out hole 131c is formed in the terminal gate layer 127; a terminal gate electrode structure electrically connected to the terminal gate electrode layer 127 is formed in the terminal lead-out hole 131c, wherein the terminal gate metal lead-out structure may be prepared based on the same process as the source metal lead-out structure 132, and may be prepared based on the same process as the second lead-out gate metal lead-out structure 133 to form the same metal lead-out structure layer, and in an example, the terminal gate metal lead-out structure and the source metal lead-out structure 132 are insulated from the second lead-out gate electrode structure 133 by an etching process.

In summary, according to the trench field effect transistor structure and the manufacturing method thereof of the present invention, the gate lead-out structure is manufactured in the region outside the device region, so that the second trench with a wider width can be manufactured, a photomask does not need to be added, and the second dielectric layer (e.g., an oxide layer) of the lead-out gate between the second lead-out gate layer (e.g., the gate polysilicon) and the epitaxial layer with a thicker thickness can be manufactured, thereby meeting the breakdown voltage requirement of the device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A preparation method of a trench type field effect transistor structure is characterized by comprising the following steps:

forming a gate dielectric layer on the exposed side wall of the first groove;

2. The method according to claim 1, wherein the step of removing a portion of the shield gate insulating layer to expose the sidewalls of the first trench, and using the remaining shield gate insulating layer on the shield gate layer as a shield gate isolation layer, and removing a portion of the extraction gate insulating layer to form an extraction gate isolation layer on the first extraction gate layer and an extraction gate second dielectric layer on the sidewalls of the second trench further comprises:

and removing part of the shielding gate insulating layer based on the first opening, and removing part of the extraction gate insulating layer based on the second opening.

3. The method of claim 2, wherein the first opening and the second opening are formed by a dry etching process; and removing part of the shielding grid insulating layer and part of the leading-out grid insulating layer by adopting a wet etching process.

4. The method of claim 1, wherein the thickness of the second dielectric layer of the extraction gate is between 1 and 1.5 times the thickness of the first dielectric layer of the extraction gate; and/or the width of the second groove is between 2 and 4 times of the width of the first groove.

5. The method of any one of claims 1-4, wherein the epitaxial layer further forms a termination region, the termination region is at least located between the device region and the gate lead-out region, and a termination protection structure is formed in the termination region, and the forming the termination protection structure comprises:

forming a terminal trench;

and forming a terminal gate layer metal lead-out structure.

6. A trench field effect transistor structure, comprising:

the second extraction grid layer is arranged in the second groove and positioned on the first extraction grid layer, an extraction grid isolation layer is arranged between the second extraction grid layer and the first extraction grid layer, and an extraction grid second medium layer is arranged between the second extraction grid layer and the side wall of the second groove;

the body region is arranged between the adjacent first grooves and between the adjacent second grooves, and the source electrode is formed in the body region and is adjacent to the first grooves;

the source metal leading-out structure is electrically connected with the body region and the source electrode, the leading-out gate metal leading-out structure is electrically connected with the second leading-out gate layer, and the drain metal leading-out structure is electrically connected with the semiconductor substrate.

7. The trench fet structure of claim 6, wherein the width of the first opening is between 0.4 and 0.6 times the width of the first trench; the width of the second opening is between 0.4 and 0.6 times the width of the first groove.

8. The trench fet structure of claim 6, wherein the depth of the first opening is between 0.6 and 0.8 times the distance between the upper surface of the shield gate isolation layer and the upper surface of the epitaxial layer; the depth of the second opening is 0.6 to 0.8 times of the distance between the upper surface of the extraction grid isolation layer and the upper surface of the epitaxial layer.

9. The trench field effect transistor structure of claim 6 wherein the thickness of the extraction gate second dielectric layer is between 1 and 1.5 times the thickness of the extraction gate first dielectric layer; the width of the second trench is between 2 to 4 times the width of the first trench.

10. The trench fet structure of any of claims 6-9, wherein the epitaxial layer further comprises a termination region, the termination region being located at least between the device region and the gate lead-out region, the termination region being provided with a termination protection structure.

11. The trench fet structure of claim 10, wherein the termination protection structure comprises:

a terminal gate layer arranged in the terminal trench and on the terminal shielding gate layer, wherein a terminal isolation layer is arranged between the terminal gate layer and the terminal shielding gate layer, a terminal second dielectric layer is arranged between the terminal gate layer and the side wall of the terminal trench, and the thickness of the terminal second dielectric layer is greater than or equal to that of the terminal first dielectric layer;