CN107316863A - Transient Voltage Suppressor and preparation method thereof - Google Patents
Transient Voltage Suppressor and preparation method thereof Download PDFInfo
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- CN107316863A CN107316863A CN201710564685.6A CN201710564685A CN107316863A CN 107316863 A CN107316863 A CN 107316863A CN 201710564685 A CN201710564685 A CN 201710564685A CN 107316863 A CN107316863 A CN 107316863A
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- 230000001052 transient effect Effects 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 238000000407 epitaxy Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 3
- 239000010410 layer Substances 0.000 description 35
- 238000004519 manufacturing process Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract
The present invention relates to a kind of Transient Voltage Suppressor and preparation method thereof.The Transient Voltage Suppressor includes N-type substrate, it is formed at the N-type epitaxy layer in the N-type substrate, it is formed at the p-well on the N-type epitaxy layer surface, it is formed at spaced first groove and second groove in the p-well, it is formed at the first groove and the n-type doping region in the second groove and N-type polycrystalline silicon, it is formed at the first input electrode in the N-type polycrystalline silicon in the first groove, it is formed at the second input electrode in the N-type polycrystalline silicon in the second groove, and it is formed at the output electrode in the p-well between the first groove and the second groove, the p-well constitutes the first Zener diode with the n-type doping region in first groove and the N-type polycrystalline silicon, the p-well constitutes the second Zener diode with the n-type doping region in second groove and the N-type polycrystalline silicon.
Description
【Technical field】
The present invention relates to semiconductor chip manufacturing technology field, especially, it is related to a kind of Transient Voltage Suppressor and its system
Make method.
【Background technology】
Transient Voltage Suppressor (TVS) is a kind of for protecting sensitive semiconductor device, it is exempted from transient voltage surge
Destruction and specially designed solid-state semiconductor device, it has a clamp, and coefficient is small, small volume, response are fast, leakage current is small and reliable
The advantages of property is high, thus be widely used on voltage transient and carrying out surge protection.Static discharge (ESD) and other one
The transient voltage that a little voltage surge forms occur at random, is typically found in various electronic devices.With semiconductor devices increasingly
Tend to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to the influence of voltage surge, even results in fatal
Injury.Various voltage surges can induce transient current spikes from static discharge to lightning etc., and Transient Voltage Suppressor is generally used
To protect sensitive circuit to be impacted by surge.However, the manufacturing cost for how improving device performance and reduction device is industry
Important topic.
【The content of the invention】
The present invention proposes a kind of Transient Voltage Suppressor and its manufacture method, improves device performance, reduces device
Manufacturing cost.
A kind of Transient Voltage Suppressor, it includes N-type substrate, the N-type epitaxy layer being formed in the N-type substrate, formed
P-well in the N-type epitaxy layer surface, it is formed at spaced first groove and second groove in the p-well, is formed at institute
State first groove and the n-type doping region in the second groove and N-type polycrystalline silicon, the N-type being formed in the first groove
The first input electrode on polysilicon, the second input electrode in the N-type polycrystalline silicon being formed in the second groove and formed
The output electrode in p-well between the first groove and the second groove, the p-well is mixed with the N-type in first groove
Miscellaneous region and the N-type polycrystalline silicon constitute the first Zener diode, the p-well and the n-type doping region in second groove and institute
State N-type polycrystalline silicon and constitute the second Zener diode.
In one embodiment, the n-type doping region is formed uniformly in the first groove and the second groove
The n-type doping region in surface, the first groove be sandwiched in the first groove with its in the N-type polycrystalline silicon it
Between, the n-type doping region in the second groove is sandwiched between the second groove and the N-type polycrystalline silicon in it.
In one embodiment, the first groove is identical with the size of the second groove.
In one embodiment, top surface of the p-well away from the N-type substrate, the n-type doping region are away from described
The either flush of the top surface of N-type substrate and the N-type polycrystalline silicon away from the N-type substrate.
In one embodiment, the thickness of first input electrode, second input electrode and the output electrode
Degree is equal.
A kind of preparation method of Transient Voltage Suppressor, it comprises the following steps：
N-type substrate is provided, N-type epitaxy layer is formed in the N-type substrate, prepares and aoxidizes on the N-type epitaxy layer surface
Layer, first time photoetching, two injection windows of dry etching formation are carried out to the oxide layer；
The p-type ion note of at least three times different-energies is carried out in the corresponding N-type epitaxy layer of described two injection windows
Enter；
High annealing is carried out, the p-type ion of described two injection window injections diffuses to form p-well；
Using the oxide layer as mask, dry etching is carried out using described two injection windows, is formed and is located at the P
First groove and second groove in trap, bottom of the bottom away from the p-well of the first groove and the second groove have
Preset distance；
Carry out N-type thermal diffusion so that the first groove forms n-type doping region with the second groove surface；
Remove the oxide layer；
In the first groove and the second groove and n-type doping region surface formation N-type polycrystalline silicon；And
The first input electrode is formed in the N-type polycrystalline silicon of the first groove, in the N-type polycrystalline silicon of the second groove
Output electrode is formed in the second input electrode of upper formation, the p-well between the first groove and the second groove,
Wherein, the p-well constitutes the pole of the first Zener two with the n-type doping region in first groove and the N-type polycrystalline silicon
Pipe, the p-well constitutes the second Zener diode with the n-type doping region in second groove and the N-type polycrystalline silicon.
In one embodiment, the energy of three p-type ion implantings gradually increases.
In one embodiment, the step of removal oxide layer includes carrying out the wet etching removal oxidation
Layer.
In one embodiment, methods described also includes：In the N-type epitaxy layer, the p-well, the n-type doping area
N-type polycrystalline silicon layer is formed on domain, dry etching is carried out and removes the N-type epitaxy layer, the p-well, the n-type doping region surface
Part N-type polycrystalline silicon, the N-type polycrystalline silicon in the first groove and the second groove retains many so as to form the N-type
Crystal silicon.
In one embodiment, methods described also includes：In the N-type epitaxy layer, the p-well, the n-type doping area
Domain and the N-type polycrystalline silicon surface prepare metal level, carry out second of photoetching to the metal level, dry or wet etch and fast
Speed heat is annealed, and forms first input electrode, the second input electrode and output electrode.
Compared to prior art, in Transient Voltage Suppressor proposed by the present invention and preparation method thereof, it is only necessary to carry out two
Secondary photoetching can be prepared by the Transient Voltage Suppressor, and technique is simple, reduces manufacturing cost, two Zener diodes
P-well is formed by the ion implanting of more than three times different-energies, and doping concentration is uniform, the stable breakdown voltage of device with it is consistent
Property is good.The N areas of two Zener diodes can increase machining area by being diffuseed to form after etching groove, improve
Device original area, reduces device cost.The Transient Voltage Suppressor of methods described formation is inputted with least two-way, side
Just multiple circuits are protected simultaneously in application process, reduces the application cost of device.
【Brief description of the drawings】
Technical scheme in order to illustrate the embodiments of the present invention more clearly, embodiment will be described below used in
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, on the premise of not paying creative work, it can also be obtained according to these accompanying drawings other attached
Figure, wherein：
Fig. 1 is the structural representation of Transient Voltage Suppressor of the present invention.
Fig. 2 is the schematic equivalent circuit of Transient Voltage Suppressor shown in Fig. 1.
Fig. 3 is the flow chart of the preparation method of Transient Voltage Suppressor shown in Fig. 1.
Fig. 4-Figure 12 is the structural representation of each step of preparation method shown in Fig. 3.
【Main element symbol description】
Transient Voltage Suppressor 100；N-type substrate 101；N-type epitaxy layer 102；P-well 103；First groove 104；Second groove
105；N-type doping region 106；N-type polycrystalline silicon 107；First input electrode 108；Second input electrode 109；Output electrode 110；
First Zener diode 111；Second Zener diode 112；Oxide layer 113；Inject window 114；Step S1~S8
【Embodiment】
The technical scheme in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
All other embodiment that technical staff is obtained under the premise of creative work is not made, belongs to the model that the present invention is protected
Enclose.
Big to solve prior art Transient Voltage Suppressor area, technology difficulty is high, and the technology such as device manufacturing cost height is asked
Topic, the present invention provides the Transient Voltage Suppressor after a kind of improvement, and it is transient voltage suppression of the present invention to refer to Fig. 1 and Fig. 2, Fig. 1
The structural representation of device 100 processed, Fig. 2 is the schematic equivalent circuit of Transient Voltage Suppressor 100 shown in Fig. 1.The transient state electricity
Pressure suppressor 100 includes N-type substrate 101, the N-type epitaxy layer 102 being formed in the N-type substrate 101, is formed at the N-type
The p-well 103 on the surface of epitaxial layer 102, it is formed at spaced first groove 104 and second groove 105, shape in the p-well 103
N-type doping region 106 and N-type polycrystalline silicon 107 in first groove 104 described in Cheng Yu and the second groove 105, it is formed at institute
State the first input electrode 108 in the N-type polycrystalline silicon 107 in first groove 104, the N-type being formed in the second groove 105
The second input electrode 109 on polysilicon 107 and the P being formed between the first groove 104 and the second groove 105
Output electrode 110 on trap 103, the p-well 103 and the n-type doping region 106 in the first groove 104 and the N-type are more
Crystal silicon 107 constitute n-type doping region 106 in the first Zener diode 111, the p-well 103 and the second groove 105 and
The N-type polycrystalline silicon 108 constitutes the second Zener diode 112.
Specifically, the n-type doping region 106 is formed uniformly in the first groove 104 and the table of second groove 105
The n-type doping region 106 in face, the first groove 104 be sandwiched in the first groove 104 with its in the N-type it is many
Between crystal silicon 107, the n-type doping region 106 in the second groove 105 is sandwiched in the second groove 105 and its
Between the N-type polycrystalline silicon 107.In present embodiment, the bottom of the first groove 104 and the second groove 105 is away from institute
Stating the bottom of p-well 103 has preset distance, i.e., described first groove 104 can not run through the p-well with the second groove 105
103.The size of the first groove 104 and the second groove 105 is essentially identical, the first groove 104 and described second
The thickness in the n-type doping region 106 in groove 105 is equal.Top surface of the p-well 103 away from the N-type substrate 101, the N
Top surface and the N-type polycrystalline silicon 107 of the type doped region 106 away from the N-type substrate 101 are away from the N-type substrate 101
Either flush.The thickness of first input electrode 108, second input electrode 109 and the output electrode 110 is homogeneous
Deng.
Fig. 3-Figure 12 is referred to, Fig. 3 is the flow chart of the preparation method of Transient Voltage Suppressor 100 shown in Fig. 1, Fig. 4-figure
12 be the structural representation of each step of preparation method shown in Fig. 3.The preparation method of the Transient Voltage Suppressor 100 include with
Lower step S1~S8.
Step S1, referring to Fig. 4, providing N-type substrate 101, forms N-type epitaxy layer 102 in the N-type substrate 101,
The surface of N-type epitaxy layer 102 prepares oxide layer 113, and first time photoetching is carried out to the oxide layer 113, and dry etching is formed
Two injection windows 114.Specifically, in one embodiment, the N-type substrate 101 is N-type silicon chip, the N-type epitaxy layer
102 form from N-type substrate growth, and the oxide layer 111 is silicon dioxide layer, in the step S1, can be by institute
State the surface thermal oxide of N-type epitaxy layer 102 and prepare the silicon dioxide layer.
Step S2, referring to Fig. 5, entering 102 rows at least in the corresponding N-type epitaxy layer of described two injection windows 114
The p-type ion implanting of three different-energies.In the step S2, the energy of three p-type ion implantings strengthens successively.
Step S3, referring to Fig. 6, high annealing is carried out, the p-type ion divergent contour that described two injection windows 114 inject
Into p-well 103.
Step S4, referring to Fig. 7, using the oxide layer 113 as mask, being entered using described two injection windows 114
Row dry etching, forms the first groove 104 being located in the p-well 103 and second groove 105, the first groove 104 and institute
Stating bottom of the bottom away from the p-well 103 of second groove 105 has preset distance.
Step S5, referring to Fig. 8, carrying out N-type thermal diffusion in the first groove 104 and the second groove 105 so that
The first groove 104 forms n-type doping region 106 with the surface of second groove 105；
Step S6, referring to Fig. 9, removing the oxide layer 113；Specifically, in the step S3, wet method can be carried out rotten
Etching off removes the oxide layer 113.
Step S7, refers to Figure 10 and 11, the first groove 104 with the second groove 105 and the N-type is mixed
The miscellaneous surface of region 106 forms N-type polycrystalline silicon 107.Specifically, in the step S7, referring to Fig. 10, in the N-type epitaxy layer
102nd, the p-well 103, N-type polycrystalline silicon layer is formed on the n-type doping region 106；Figure 11 is referred to, dry etching is carried out and goes
Except the N-type epitaxy layer 102, the p-well 103, the part N-type polycrystalline silicon on the surface of n-type doping region 106, described first
Groove 104 retains to form the N-type polycrystalline silicon 107 with the N-type polycrystalline silicon in the second groove 105.
Step S8, refers to Figure 11, and the first input electrode is formed in the N-type polycrystalline silicon 107 of the first groove 104
108, the second input electrode 109 is formed in the N-type polycrystalline silicon 107 of the second groove 105, the first groove 104 with
Output electrode 110 is formed in p-well 103 between the second groove 105.Specifically, in the step S8：Outside the N-type
Prolong layer 102, the p-well 103, the n-type doping region 106 and the surface of the N-type polycrystalline silicon 107 and prepare metal level, to described
Metal level carries out second of photoetching, dry or wet etch and rapid thermal annealing, forms first input electrode 108, second
Input electrode 109 and output electrode 110.
Compared to prior art, in Transient Voltage Suppressor 100 proposed by the present invention and preparation method thereof, it is only necessary to carry out
Twi-lithography can be prepared by the Transient Voltage Suppressor 100, and technique is simple, reduces manufacturing cost, two Zeners two
The p-well of pole pipe 111,112 is formed by the ion implanting of more than three times different-energies, and doping concentration is uniform, the breakdown potential of device
Press stability and uniformity good.The pole 111 of two Zeners two, the N areas of 112 pipes can pass through divergent contour after etching groove
Into increasing machining area, improve device original area, reduce device cost.The transient voltage suppression of methods described formation
Device 100 processed is inputted with least two-way, facilitates in application process and multiple circuits are protected simultaneously, reduce being applied to for device
This.
Above-described is only embodiments of the present invention, it should be noted here that for one of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
Enclose.
Claims (10)
1. a kind of Transient Voltage Suppressor, it is characterised in that：The Transient Voltage Suppressor includes N-type substrate, is formed at the N
N-type epitaxy layer on type substrate, it is formed at the p-well on the N-type epitaxy layer surface, is formed at spaced in the p-well
One groove and second groove, the n-type doping region being formed in the first groove and the second groove and N-type polycrystalline silicon,
The first input electrode in the N-type polycrystalline silicon being formed in the first groove, the N-type polycrystalline being formed in the second groove
The second input electrode on silicon and the output electrode in the p-well being formed between the first groove and the second groove, institute
State p-well and constitute the first Zener diode, the p-well and second with the n-type doping region in first groove and the N-type polycrystalline silicon
N-type doping region and the N-type polycrystalline silicon in groove constitute the second Zener diode.
2. Transient Voltage Suppressor as claimed in claim 1, it is characterised in that：The n-type doping region is formed uniformly in institute
The n-type doping region stated in first groove and the second groove surface, the first groove is sandwiched in the first groove
Between the N-type polycrystalline silicon in it, the n-type doping region in the second groove is sandwiched in the second groove and its
Between the interior N-type polycrystalline silicon.
3. Transient Voltage Suppressor as claimed in claim 1, it is characterised in that：The first groove and the second groove
Size is identical.
4. Transient Voltage Suppressor as claimed in claim 1, it is characterised in that：Top of the p-well away from the N-type substrate
The top surface of top surface and the N-type polycrystalline silicon away from the N-type substrate of face, the n-type doping region away from the N-type substrate
Concordantly.
5. Transient Voltage Suppressor as claimed in claim 1, it is characterised in that：It is first input electrode, described second defeated
The thickness for entering electrode and the output electrode is equal.
6. a kind of preparation method of Transient Voltage Suppressor, it comprises the following steps：
N-type substrate is provided, N-type epitaxy layer is formed in the N-type substrate, oxide layer is prepared on the N-type epitaxy layer surface, it is right
The oxide layer carries out first time photoetching, two injection windows of dry etching formation；
The p-type ion implanting of at least three times different-energies is carried out in the corresponding N-type epitaxy layer of described two injection windows；
High annealing is carried out, the p-type ion of described two injection window injections diffuses to form p-well；
Using the oxide layer as mask, dry etching is carried out using described two injection windows, is formed and is located in the p-well
First groove and second groove, bottom of the bottom away from the p-well of the first groove and the second groove has predetermined
Distance；
Carry out N-type thermal diffusion so that the first groove forms n-type doping region with the second groove surface；
Remove the oxide layer；
In the first groove and the second groove and n-type doping region surface formation N-type polycrystalline silicon；And
The first input electrode is formed in the N-type polycrystalline silicon of the first groove, the shape in the N-type polycrystalline silicon of the second groove
Into the second input electrode, output electrode is formed in the p-well between the first groove and the second groove,
Wherein, the p-well constitutes the first Zener diode, institute with the n-type doping region in first groove and the N-type polycrystalline silicon
State p-well and constitute the second Zener diode with the n-type doping region in second groove and the N-type polycrystalline silicon.
7. the preparation method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：Three p-type ions note
The energy entered gradually increases.
8. the preparation method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：It is described to remove the oxide layer
The step of include carrying out wet etching removing the oxide layer.
9. the preparation method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：Methods described also includes：
The N-type epitaxy layer, the p-well, N-type polycrystalline silicon layer is formed on the n-type doping region, carry out dry etching and remove the N
Type epitaxial layer, the p-well, the part N-type polycrystalline silicon of the n-type doping region surface, the first groove and second ditch
N-type polycrystalline silicon in groove retains to form the N-type polycrystalline silicon.
10. the preparation method of Transient Voltage Suppressor as claimed in claim 6, it is characterised in that：Methods described also includes：
The N-type epitaxy layer, the p-well, the n-type doping region and the N-type polycrystalline silicon surface prepare metal level, to the metal
Layer carries out second of photoetching, dry or wet etch and rapid thermal annealing, forms first input electrode, the second input electrode
And output electrode.
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