CN109360823A - Groove-shaped Transient Voltage Suppressor and preparation method thereof - Google Patents
Groove-shaped Transient Voltage Suppressor and preparation method thereof Download PDFInfo
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- CN109360823A CN109360823A CN201811167802.6A CN201811167802A CN109360823A CN 109360823 A CN109360823 A CN 109360823A CN 201811167802 A CN201811167802 A CN 201811167802A CN 109360823 A CN109360823 A CN 109360823A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
The present invention discloses a kind of groove-shaped Transient Voltage Suppressor and preparation method thereof, the production method is performed etching and is heat-treated by the second substrate of the first substrate and the second conduction type to the first conduction type to form bonding semiconductor structure, the bonding semiconductor structure includes at least three semiconductor columns of bonding setting, and the conduction type of two adjacent semiconductor columns is opposite；At least three semiconductor column includes the first connecting column for connecting with the first metal layer and the second connecting column for connecting with second metal layer, and the spacer column between first connecting column and second connecting column.Groove-shaped Transient Voltage Suppressor of the present invention includes the diode including at least two series connection and docking, to have the function of bidirectional protective.The PN junction boundary defect of the bonding semiconductor structure is few, so that the groove-shaped Transient Voltage Suppressor electric leakage is small, effectively promotes the protection feature and reliability of the groove-shaped Transient Voltage Suppressor.
Description
Technical field
The present invention relates to technical field of semiconductors, especially a kind of groove-shaped Transient Voltage Suppressor and preparation method thereof.
Background technique
Static discharge (Electro-Static Discharge, ESD) and other occur at random in the form of voltage surge
Transient voltage be typically found in various electronic devices.Various voltage surges can induce transient state from static discharge to lightning etc.
Current spike.As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to electricity
The influence for pressing surge, even results in fatal harm.
Transient Voltage Suppressor (TransientVoltage Suppressor, TVS) is based on diode as a kind of
Protection device, protect against the impacts of various forms of high voltage transients commonly used to protection sensitive circuit.Based on different
Using Transient Voltage Suppressor can be made by changing the clamping voltag of surge discharge path and itself to play circuit protection
With.
In order to save chip area and obtain higher Surge handling capability, groove-shaped Transient Voltage Suppressor is ground extensively
Study carefully.The junction of groove-shaped Transient Voltage Suppressor is formed in the side wall of longitudinal groove, in this way, under identical chip area,
It has more effective junction areas, i.e., stronger discharge capability.Currently used groove-shaped Transient Voltage Suppressor can only be realized
Unidirectional protection is needed multiple Transient Voltage Suppressor serial or parallel connections together if necessary to carry out bidirectional protective, but in this way
It will increase device area and manufacturing cost.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of groove-shaped transient state electricity of low cost, achievable bidirectional protective
Press suppressor.
In order to solve the above technical problems, the present invention adopts the following technical solutions: the groove-shaped Transient Voltage Suppressor includes:
The first metal layer and second metal layer；Bonding semiconductor structure, the bonding semiconductor structure include at least the three of bonding setting
A semiconductor column, and the conduction type of two adjacent semiconductor columns is opposite；At least three semiconductor column includes using
In the first connecting column connecting with the first metal layer and the second connecting column for connecting with second metal layer, and it is located at described the
Spacer column between one connecting column and second connecting column.
Groove-shaped Transient Voltage Suppressor of the present invention includes the two kind semiconductor column staggered rows opposite by conduction type
The bonding semiconductor structure of cloth composition, and the semiconductor column for constituting the bonding semiconductor structure is divided into the first connection again
Column, the second connecting column and the spacer column between the first connecting column and the second connecting column, so that the groove-shaped transient voltage
Suppressor includes at least the diode of two series connection and docking, to have the function of bidirectional protective.The groove-shaped transient voltage
Diode in suppressor is made of the semiconductor in the bonding semiconductor structure, and the semiconductor is bonding setting
Together, so that the PN junction boundary defect of the diode is few, and then the groove-shaped Transient Voltage Suppressor electric leakage is small, effectively
Promote the protection feature and reliability of the groove-shaped Transient Voltage Suppressor.Meanwhile groove-shaped transient voltage of the present invention
Suppressor can also realize two pole of multiple groups by adjusting position and the quantity of first connecting column and second connecting column
Pipe is in parallel, meets the two-way protection demand of multichannel.
Correspondingly, the present invention also provides the production method of the groove-shaped Transient Voltage Suppressor, the groove-shaped transient states
The production method of voltage suppressor the following steps are included:
S1: providing the first substrate of the first conduction type, etches first substrate from the upper surface of first substrate
And form at least two first grooves and at least one first semiconductor column between the first groove；
S2: providing the second substrate of the second conduction type, etches second substrate simultaneously from the front of second substrate
Corresponding first semiconductor column of formation and second groove compatible with first semiconductor column and corresponding first ditch
Slot and the second semiconductor column compatible with the first groove；
S3: so that the front of second substrate is directed at the upper surface of first substrate, first semiconductor column is enabled
Enter the first groove into the second groove, second semiconductor column thus by first substrate and described second
Substrate combination is together；
S4: first time high-temperature heat treatment is carried out, so that first semiconductor column is bonded in second semiconductor column
Together and bonding semiconductor structure is formed, the bonding semiconductor structure is including the first connecting column, the second connecting column and is located at institute
State the spacer column between the first connecting column and second connecting column；First connecting column is by first semiconductor column or institute
The second semiconductor column composition is stated, second connecting column is made of first semiconductor column or second semiconductor column, institute
Spacer column is stated to be made of first semiconductor column and/or second semiconductor column；
S5: forming the first metal layer for connecting first connecting column and connects the second metal of second connecting column
Layer.
The production method of groove-shaped Transient Voltage Suppressor of the present invention passes through the first substrate to the first conduction type
It performs etching and is heat-treated with the second substrate of the second conduction type to form bonding semiconductor structure, without extension and repeatedly
Injection technology, so that process simplification, reduces the cost of manufacture of the groove-shaped Transient Voltage Suppressor.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the schematic diagram of the section structure for the groove-shaped Transient Voltage Suppressor that one embodiment of the invention provides；
Fig. 2 is the flow diagram of the production method for the groove-shaped Transient Voltage Suppressor that one embodiment of the invention provides；
Fig. 3 to Figure 11 is the section knot of the forming process for the groove-shaped Transient Voltage Suppressor that one embodiment of the invention provides
Structure schematic diagram；
Figure 12 is the equivalent circuit diagram for inventing the groove-shaped Transient Voltage Suppressor that an embodiment provides.
Description of symbols:
10: the first metal layer；101: first part；102: second part；20: second metal layer；201: Part III；
202: Part IV；30: bonding semiconductor structure；30a: the first connecting column；30b: the second connecting column；30c: spacer column；31: the
One substrate；31a: upper surface；31b: lower surface；311: first groove；312: the first semiconductor columns；313: the first O +ion implanteds
Area；314: the first substrate layers；315: the first silicon oxide layers；316: the first contact holes；32: the second substrates；32a: front；32b: back
Face；321: second groove；322: the second semiconductor columns；323: the second O +ion implanted areas；324: the second substrate layers；325: the second
Silicon oxide layer；326: the second contact holes；41: first diode；42: the second diodes；43: third diode；44: the four two poles
Pipe；45: the five diodes；46: the six diodes.
Specific embodiment
Big, system that present invention is generally directed to the areas of the conventional groove-shaped Transient Voltage Suppressor with bidirectional protective function
Make problem at high cost and a solution is provided.
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Referring to Fig. 1, a kind of groove-shaped Transient Voltage Suppressor comprising:
The first metal layer 10 and second metal layer 20；
Bonding semiconductor structure 30 comprising be bonded at least three semiconductor columns of setting, and adjacent two described half
The conduction type of conductor pin is opposite；At least three semiconductor column includes the first connection for connecting with the first metal layer 10
Column 30a and the second connecting column 30b for being connect with second metal layer 20, and it is located at the first connecting column 30a and described the
Spacer column 30c between two connecting column 30b.
Groove-shaped Transient Voltage Suppressor of the present invention includes the two kind semiconductor column staggered rows opposite by conduction type
The bonding semiconductor structure 30 of cloth composition, and the semiconductor column for constituting the bonding semiconductor structure 30 is divided into the first company again
Column 30a, the second connecting column 30b and the spacer column 30c between the first connecting column 30a and the second connecting column 30b are met, so that institute
Groove-shaped Transient Voltage Suppressor is stated including at least the diode of two series connection and docking, to have the function of bidirectional protective.Institute
The diode stated in groove-shaped Transient Voltage Suppressor is made of the semiconductor in the bonding semiconductor structure 30, and institute
It states semiconductor to be set together for bonding, so that the PN junction boundary defect of the diode is few, and then the groove-shaped transient state electricity
It presses suppressor electric leakage small, effectively promotes the protection feature and reliability of the groove-shaped Transient Voltage Suppressor.Meanwhile the present invention
The groove-shaped Transient Voltage Suppressor can also be by adjusting the first connecting column 30a's and the second connecting column 30b
Position and quantity realize multiple groups diodes in parallel, meet the two-way protection demand of multichannel.
Referring to Fig. 2, a kind of production method of groove-shaped Transient Voltage Suppressor comprising following steps:
S1: providing the first substrate 31 of the first conduction type, from the upper surface 31a of first substrate etching described first
Substrate 31 simultaneously forms at least two first grooves 311 and at least one first semiconductor between the first groove 311
Column 312；
S2: providing the second substrate 32 of the second conduction type, from the positive 32a of second substrate etching second lining
Bottom 32 and form corresponding first semiconductor column 312 and second groove 321 compatible with first semiconductor column 312 and
The corresponding first groove 311 and second semiconductor column 312 compatible with the first groove 311；
S3: so that the positive 32a of second substrate is directed at the upper surface 31a of first substrate, described the first half are enabled
Conductor pin 312 will enter the second groove 321, second semiconductor column 322 enters the first groove 311 thus will be described
First substrate 31 is combined with second substrate 32；
S4: carrying out first time high-temperature heat treatment, so that first semiconductor column 312 and second semiconductor column 322
It is bonded together and forms bonding semiconductor structure 30, the bonding semiconductor structure 30 includes the first connecting column 30a, the second company
Meet the column 30b and spacer column 30c between the first connecting column 30a and the second connecting column 30b；First connection
Column 30a is made of first semiconductor column 312 or second semiconductor column 322, and the second connecting column 30b is by described
Semiconductor column 312 or second semiconductor column 322 are constituted, the spacer column 30c by first semiconductor column 312 and/
Or second semiconductor column 322 is constituted.
S5: for forming the first metal layer 10 for connecting the first connecting column 30a and connecting the second connecting column 30b
Two metal layers 20.
The production method of groove-shaped Transient Voltage Suppressor of the present invention passes through the first substrate to the first conduction type
It performs etching and is heat-treated with the second substrate of the second conduction type to form bonding semiconductor structure, without extension and repeatedly
Injection technology, so that process simplification, reduces the cost of manufacture of the groove-shaped Transient Voltage Suppressor.
With reference to the accompanying drawings, described groove-shaped Transient Voltage Suppressor and preparation method thereof is elaborated.
Special to illustrate herein for convenience of subsequent description: first conduction type can be N-type, then, described second leads
Electric type is p-type, conversely, first conduction type may be p-type, correspondingly, second conduction type is N-type.?
In next embodiment, retouched so that first conduction type is N-type and second conduction type is p-type as an example
It states, but is defined not to this.
Fig. 3 to Fig. 5 is please referred to, step S1 is executed: the first substrate 31 is provided.First substrate 31 has upper surface 31a
With lower surface 31b, the upper surface 31a is opposite with the lower surface 31b.In the present embodiment, first substrate 31 is preferred
For silicon substrate.Silicon can effectively reduce cost and promote yield as most common, cheap and stable performance semiconductor material.
In other embodiments, the material of first substrate 31 can also be silicon carbide, germanium or germanium silicon etc..In detail, described
First substrate 31 is the first conduction type.In the present embodiment, first conduction type is N-type, therefore first substrate
31 be N-type semiconductor.In other embodiments, first conduction type may be p-type, therefore, first substrate 31
As P-type semiconductor.First substrate of N-type 31 can adulterate the elements such as phosphorus, arsenic, antimony by silicon and be formed, and be not limited thereto.
Further, first substrate 31 is etched from the upper surface 31a, and forms first groove 311 and the first half and leads
Scapus 312, the first groove 311 are located in first substrate 31, the quantity at least two of the first groove 311,
First semiconductor column 312 is formed between the first groove 311, it will be understood that the number of first semiconductor column 312
Amount is at least one, and first semiconductor column 312 is arranged alternately with the first groove 311.It is appreciated that described first
The composition and conduction type of semiconductor column 312 are consistent with the composition of first substrate 31 and conduction type, in first lining
When bottom 31 is the first conduction type, first semiconductor column 312 is also the first conduction type.In the present embodiment, described
One substrate 31 is N-type semiconductor, then first semiconductor column 312 is also N-type semiconductor column.More specifically, in the present embodiment
In, first substrate 31 is etched from the upper surface 31a and forms four first grooves 311, at described four first
First semiconductor column 312 there are three being formed between groove 311.It should be noted that when forming multiple first grooves
311 and when multiple first semiconductor columns 312, the size of each first groove 311 can be equal or unequal, respectively
The size of first semiconductor column 312 can be equal or unequal.In the present embodiment, preferably described four the first ditches
The size of slot 311 is equal, and the size of three first semiconductor columns 312 is equal.
Specifically, the first groove 311 and first semiconductor column 312 are formed the following steps are included: described
The upper surface 31a of one substrate 31 is laid with photoresist layer (not shown)；The photoresist layer is exposed, then is developed,
Form the window (not shown) for running through the photoresist layer；Using the photoresist layer as exposure mask, passed through by the way of etching
The window performs etching to first substrate 31 and is formed the first groove 311 and first semiconductor column 312,
During etching, the depth of etching is less than the thickness of first substrate 31, to guarantee that it is described that the first groove 311 is located at
In first substrate 31.In detail, the method for the etching includes dry etching and wet etching.In the present embodiment, it preferably adopts
With the method for dry etching.The etching agent of the dry etching is plasma, using plasma and is etched substance reaction,
Volatile materials is formed, or directly bombards the substance that is etched and is allowed to be corroded, can be realized anisotropic etching, consequently facilitating
Ensure shape, the precision of positions and dimensions of the first groove 311 and first semiconductor column 312.In addition, the dry method
Etching easily realizes that automation, treatment process are not introduced into pollution, cleannes height.Produce the first groove 311 and described first
After semiconductor column 312, the photoresist layer is first removed using cleaning solution.
Further, O +ion implanted is carried out to first substrate 31 from the lower surface 31b, and is formed positioned at described
The first O +ion implanted area 313 in first substrate 31, first O +ion implanted area 313 far from the lower surface 31b and
Connect the first groove 311 and first semiconductor column 312.Meanwhile it is described outside first O +ion implanted area 313
First substrate 31 constitutes the first substrate layer 314, and the lower surface 31b is located on first substrate layer 314.
Fig. 6 to Fig. 8 is please referred to, step S2 is executed: the second substrate 32 is provided.Second substrate 32 have front 32a with
Back side 32b, the front 32a are opposite with the back side 32b.In the present embodiment, second substrate 32 is preferably silicon substrate.
Silicon can effectively reduce cost and promote yield as most common, cheap and stable performance semiconductor material.In other implementations
In mode, the material of second substrate 32 can also be silicon carbide, germanium or germanium silicon etc..In detail, second substrate 32
For the second conduction type.In the present embodiment, second conduction type is p-type, therefore second substrate 32 is that p-type is partly led
Body.In other embodiments, second conduction type may be N-type, and therefore, second substrate 32 is that N-type is partly led
Body.Second substrate of p-type 32 can adulterate the elements such as boron, indium, gallium by silicon and be formed, and be not limited thereto.
Further, second substrate 32 is etched from the front 32a, and forms second groove 321 and the second semiconductor
Column 322, the second groove 321 are located in second substrate 32, and the quantity of the second groove 321 is at least one, institute
It states the second semiconductor column 322 and is formed in 321 two sides of second groove, it will be understood that the quantity of second semiconductor column 322
At least two, and second semiconductor column 322 is arranged alternately with the second groove 321.It is appreciated that described the second half
The composition and conduction type of conductor pin 322 are consistent with the composition of second substrate 32 and conduction type, in second substrate
32 be the second conduction type when, second semiconductor column 322 also be the second conduction type.In detail, the second groove 321
It is corresponding with first semiconductor column 312, and the second groove 321 is adapted with first semiconductor column 312.Described
Two grooves 321 quantity that can be understood as the second groove 321 corresponding with first semiconductor column 312 and described the first half
Conductor pin 312 is equal, and the position of the second groove 321 is corresponding with the position of first semiconductor column 312.Described
Two semiconductor columns 322 are corresponding with the first groove 311, and second semiconductor column 322 and 311 phase of first groove are suitable
Match.Second semiconductor column 322 number that can be understood as second semiconductor column 322 corresponding with the first groove 311
Amount is equal with the quantity of the first groove 311, and the position of second semiconductor column 322 and the first groove 311
Position is corresponding.In the present embodiment, second substrate 32 is N-type semiconductor, then second semiconductor column 322 is also N
Type semiconductor column.More specifically, in the present embodiment, etching second substrate 32 from the front 32a and forming three institutes
Second groove 321 is stated, there are four second semiconductor columns 322 for formation in the two sides of three second grooves 311.It needs
It is bright, when forming multiple second grooves 321 and multiple second semiconductor columns 322, each second groove 321
Size can be equal or unequal, the size of each second semiconductor column 322 can be equal or unequal.?
In the present embodiment, the size of preferably described three second grooves 321 is equal, the size of four second semiconductor columns 322
It is equal.In detail, the size of the second groove 321 and the size of first semiconductor column 312 are equal, and described second
The size of semiconductor column 322 is equal sized with the first groove 311.
Specifically, the second groove 321 and second semiconductor column 322 are formed the following steps are included: described
The front 32a of two substrates 32 is laid with photoresist layer (not shown)；The photoresist layer is exposed, then is developed, shape
At the window (not shown) for running through the photoresist layer；Using the photoresist layer as exposure mask, pass through institute by the way of etching
It states window and the second groove 321 and second semiconductor column 322 is performed etching and formed to second substrate 32, carving
During erosion, the depth of etching is less than the thickness of second substrate 32, to guarantee that the second groove 321 is located at described the
In two substrates 32.In detail, the method for the etching includes dry etching and wet etching.In the present embodiment, it is preferred to use
The method of dry etching.The etching agent of the dry etching is plasma, utilizes plasma and the substance reaction that is etched, shape
It at volatile materials, or directly bombards the substance that is etched and is allowed to be corroded, can be realized anisotropic etching, consequently facilitating really
Protect shape, the precision of positions and dimensions of the second groove 321 and second semiconductor column 322.In addition, the dry method is carved
Erosion easily realizes that automation, treatment process are not introduced into pollution, cleannes height.Produce the second groove 321 and described the second half
After conductor pin 322, the photoresist layer is first removed using cleaning solution.
Further, O +ion implanted is carried out to second substrate 32 from the back side 32b, and is formed and is located at described the
The second O +ion implanted area 323 in two substrates 32, second O +ion implanted area 323 is far from the back side 32b and connection
The second groove 321 and second semiconductor column 322.Meanwhile described second outside second O +ion implanted area 323
Substrate 32 constitutes the second substrate layer 324, back side 32b connection second substrate layer 324.
Referring to Fig. 9, executing step S3: overturning second substrate 32, so that the front of second substrate 32
32a is directed at the upper surface 31a of first substrate 31.It certainly, in other embodiments can also be by overturning described the
One substrate 31 makes the front 32a be directed at the upper surface 31a.The front 32a is directed at the upper surface 31a and refers to institute
It states positive 32a and the upper surface 31a is corresponding each other, and the second groove 321 and first semiconductor column 312 1 are a pair of
Together, second semiconductor column 322 is aligned one by one with the first groove 311.
Further, first substrate 31 and second substrate 32 are combined.Specifically, described the first half are enabled
Conductor pin 312 enters the second groove 321, second semiconductor column 322 enters the first groove 311, thus by institute
The first substrate 31 is stated to combine with second substrate 32.In summary, it will be understood that in first substrate 31 and institute
It states after the second substrate 32 combines, including at least one described first semiconductor column 312 and at least two described the second half
Conductor pin 322 is combined, and first semiconductor column 312 and second semiconductor column 322 are staggered.In this reality
It is staggered with three the first semiconductor columns 312 and combine for four the second semiconductor columns 322 in applying.
Referring to Fig. 10, execute step S4: carry out first time high-temperature heat treatment so that first semiconductor column 312 with
Second semiconductor column 322 is bonded together, and forms bonding semiconductor structure 30.As stated above, it is understood that the key
Closing semiconductor structure 30 includes at least one described first semiconductor column 312 and at least two second semiconductor column, 322 keys
It is combined, and first semiconductor column 312 and second semiconductor column 322 are staggered.It in detail, can will be described
First semiconductor column 312 is referred to as semiconductor column with second semiconductor column 322, then the bonding semiconductor structure 30 includes
At least three semiconductor columns being bonded together.Further, since first semiconductor column 312 is the first conductive-type
Type, second semiconductor column 322 are the second conduction type, first semiconductor column 312 and second semiconductor column 322
It is staggered, then the conduction type of two semiconductor columns adjacent in the bonding semiconductor structure 30 is opposite.Specifically,
In the present embodiment, the bonding semiconductor structure 30 is that four the second semiconductor columns 322 and three the first semiconductor columns 312 are handed over
Mistake is arranged and is bonded together.
In more detail, first semiconductor column 312 and described the second half for constituting the bonding semiconductor structure 30 are led
Scapus 322 can also be divided into the first connecting column 30a, the second connecting column 30b and spacer column 30c, wherein described spacer column 30c
Between the first connecting column 30a and the second connecting column 30b, be used to be isolated the first connecting column 30a with it is described
Second connecting column 30b.
The first connecting column 30a can be first semiconductor column 312, be also possible to second semiconductor column
322.The quantity of the first connecting column 30a is either one or more.In the present embodiment, first connecting column
The quantity of 30a is one, and the first connecting column 30a is first semiconductor column 312.It should be noted that at it
In his embodiment, when the first connecting column 30a is multiple, conduction type between each first connecting column 30a can be with
It is identical to may be reversed, but the single first connecting column 30a must only be a kind of semiconductor column of conduction type.Example
Such as, in one embodiment, when the quantity of the first connecting column 30a is two, wherein first the first connecting column 30a is
One first semiconductor column 312, second the first connecting column 30a can be first semiconductor column 312, can also
Think second semiconductor column 322, is not limited thereto.
Similar with the first connecting column 30a, the second connecting column 30b can be first semiconductor column 312,
It can be second semiconductor column 322.The quantity of the second connecting column 30b is either one or more.At this
In embodiment, the quantity of the second connecting column 30b is two, and two the second connecting column 30b are described the second half
Conductor pin 322.It should be noted that in other embodiments, can also two the second connecting column 30b be described first
Semiconductor column 312, can with one in two the second connecting column 30b be first semiconductor column 312 and another
For second semiconductor column 322, it is not limited thereto.
Different from the first connecting column 30a and the second connecting column 30b, the spacer column 30c can be by the key
Close first semiconductor in semiconductor structure 30 in addition to constituting the first connecting column 30a and the second connecting column 30b
Column 312 or/and second semiconductor column 322 are constituted；I.e. when the spacer column 30c can be by first semiconductor column
312 or second semiconductor column 322 constitute, can also by the first semiconductor column 312 described at least one and at least
One second semiconductor column 322 is constituted.The quantity of the spacer column 30c is either one or more, when described
When the quantity of spacer column 30c is multiple, the composition of each spacer column 30c can be the same or different, and be not limited thereto.
In the present embodiment, the bonding semiconductor structure 30 includes two spacer column 30c, and the single spacer column 30c is equal
First semiconductor column 312 and second semiconductor column 322 including being bonded together.
Specifically, the first time high-temperature heat treatment includes pretreatment and the processing of short annealing twice.In detail, described pre-
Processing is to carry out under 500-900 DEG C of nitrogen atmosphere, and pretreatment time is 600min or more；It is quickly moved back twice later
Fire, in annealing process, annealing temperature is 1200 DEG C, and heating rate is greater than 75 DEG C/s, and rate of temperature fall is greater than 60 DEG C/s, when annealing
Between be 30-45s.First semiconductor column 312 and second semiconductor column are realized by the first time high-temperature heat treatment
322 are bonded together.In the first time high-temperature heat treatment process, the temperature and time by the way that heat treatment is rationally arranged can be with
It realizes bonded interface reparation, and reduces the defect bonded together to form.
Further, second of high-temperature heat treatment is carried out.Second of high-temperature heat treatment includes thermal anneal process, is passed through
First O +ion implanted area 313 is converted to the first silicon oxide layer 315 by the thermal anneal process, by second oxonium ion
Injection region 323 is converted to the second silicon oxide layer 325.It is appreciated that first silicon oxide layer 315 is led with described the first half simultaneously
Scapus 312 is connected with one end of second semiconductor column 322, and second silicon oxide layer 325 is led with described the first half simultaneously
Scapus 312 is connected with the other end of second semiconductor column 322 namely the bonding semiconductor structure 30 is located at described first
Between silicon oxide layer 315 and second silicon oxide layer 325, and the both ends of the semiconductor column 31 are separately connected first oxygen
SiClx layer 315 and second silicon oxide layer 325.In addition, first silicon oxide layer 315 also with first substrate layer 314
Connection, first substrate layer 314 are located at relatively described first semiconductor column 312 of first silicon oxide layer 315 and described the
The side of two semiconductor columns 322；Second silicon oxide layer 325 is also connect with second substrate layer 324, second substrate
Layer 324 is located at the one of relatively described second semiconductor column 312 of second silicon oxide layer 325 and second semiconductor column 322
Side.
Figure 11 is please referred to, step S5 is executed: forming the first metal layer 10 and second metal layer 20.In the present embodiment, institute
It states the first metal layer 10 and is connect with the bonding semiconductor structure 30 with the second metal layer 20, and be located at the key
Close the two sides of semiconductor structure 30.The first metal layer 10 is connect with first substrate layer 314, and is located at first lining
One side surface of the relatively described bonding semiconductor structure 30 of bottom 314；The second metal layer 20 and second substrate layer 324
Connection, and it is located at a side surface of the relatively described bonding semiconductor structure 30 of second substrate layer 324.In other embodiments
In, the first metal layer 10 can also be located at the same side of the bonding semiconductor structure 30 with the second metal layer 20,
It should be each other when the first metal layer 10 is located at the same side of the bonding semiconductor structure 30 with the second metal layer 20
Keep independent.
In detail, the first metal layer 10 connects with the first connecting column 30a in the bonding semiconductor structure 30
It connects.Specifically, in the present embodiment, the step of forming the first metal layer 10 includes: from described in lower surface 31b etching
First substrate layer 314 and first silicon oxide layer 315 run through first substrate layer 314 and first oxygen to be formed
First contact hole 316 of SiClx layer 315.First contact hole 316 can also further extend to the first connecting column 30a
And it is connect with the first connecting column 30a.In the present embodiment, the quantity of the first connecting column 30a is one, then described the
The quantity of one contact hole 316 is also one.Further, in first contact hole 316 and described in lower surface 31b growth
The first metal layer 10, it will be understood that the first metal layer 10 includes the first part in first contact hole 316
101 and positioned at the lower surface 31b second part 102.
The second metal layer 20 is connect with the second connecting column 30b in the bonding semiconductor structure 30.At this
In embodiment, the step of forming second metal layer 20 includes: to etch 324 He of the second substrate layer from the back side 32b
Second silicon oxide layer 325, to form second through second substrate layer 324 and second silicon oxide layer 325
Contact hole 326.Second contact hole 326 can also further extend to the second connecting column 30b and connect with described second
Connect column 30b connection.In the present embodiment, the quantity of the second connecting column 30b is two, then second contact hole 326
Quantity is also two.It further, can in second contact hole 326 and the back side 32b grows the second metal layer 20
To understand, the second metal layer 20 includes the Part III 201 in second contact hole 326 and is located at the back side
The Part IV 202 of 32b.
Incorporated by reference to Figure 11 and Figure 12, in the present embodiment, the first metal layer 10 and the second metal layer 20 can be with
Respectively as the input terminal and output end of the Transient Voltage Suppressor.In energization, electric current is from the first metal layer
10 flow into, and flow out from the second metal layer 20, wherein electric current is flowed into from the first metal layer 20, then by being located at
First connecting column 30a of the centre of the bonding semiconductor structure 30, then to the left followed by the spacer column 30c, described
Second connecting column 30b, then flowed out from the second metal layer 20, to constitute the first equivalent circuit, meanwhile, electric current is from described the
One metal layer 10 flows into, then by being located at the first connecting column 30a of the centre of the bonding semiconductor structure 30, then to the right
Followed by the spacer column 30c, the second connecting column 30b, then from the second metal layer 20 outflow, so that it is equivalent to constitute second
Circuit, second equivalent circuit and first equivalent circuit parallel relationship each other.
In the present embodiment, first conduction type is N-type, and second conduction type is p-type, then described the first half
Conductor pin 312 is N-type semiconductor, and second semiconductor column 322 is P-type semiconductor.In the present embodiment, first connection
Column 30a is first semiconductor column 312, and the quantity of the second connecting column 30b is two, and two second connections
Column 30b is second semiconductor column 322, and the spacer column 30c includes first semiconductor being bonded together
Column 312 and second semiconductor column 322.Therefore, in first equivalent circuit, the first connecting column 30a with
One reversed PN junction of formation between second semiconductor column 322 of the spacer column 30c is constituted, that is, forms reversed the one or two
Pole pipe 41；The spacer column 30c forms a positive PN junction, that is, forms the second positive diode 42；Constitute the spacer column
A reversed PN junction is formed between first semiconductor column 312 of 30c and the second connecting column 30b, that is, is formed reversely
Third diode 43；The first diode 41, second diode 42 and the third diode 43 are sequentially connected in series and right
It connects.In second equivalent circuit, the first connecting column 30a and second semiconductor for constituting the spacer column 30c
A reversed PN junction is formed between column 322, that is, forms the 4th reversed diode 44；The spacer column 30c forms a forward direction
PN junction forms the 5th positive diode 45；Constitute first semiconductor column 312 and described the of the spacer column 30c
A reversed PN junction is formed between two connecting column 30b, that is, forms the 6th reversed diode 46；4th diode 44, institute
It states the 5th diode 45 and the 6th diode 46 is sequentially connected in series and docks.In conclusion transient voltage described in the present embodiment
Suppressor has two equivalent circuits in parallel, and each equivalent circuit includes the diode of three series connection, docking, because
This, which has the function of multichannel bidirectional protective, it can be achieved that multiple circuits while protecting in application process.
The foregoing is merely one embodiment of the present of invention, are not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of groove-shaped Transient Voltage Suppressor characterized by comprising
The first metal layer and second metal layer；
Bonding semiconductor structure comprising be bonded at least three semiconductor columns of setting, and two adjacent semiconductor columns
Conduction type it is opposite；At least three semiconductor column include the first connecting column for being connect with the first metal layer and
The second connecting column for being connect with the second metal layer, and between first connecting column and second connecting column
Spacer column.
2. groove-shaped Transient Voltage Suppressor according to claim 1, which is characterized in that the groove-shaped transient voltage suppression
Device processed further includes the first silicon oxide layer and the second silicon oxide layer, and first silicon oxide layer and second silicon oxide layer distinguish position
In the two sides of the bonding semiconductor structure, and the both ends of the semiconductor column respectively with first silicon oxide layer and described
Silicon dioxide layer connection.
3. groove-shaped Transient Voltage Suppressor according to claim 2, which is characterized in that the groove-shaped transient voltage suppression
Device processed further includes the first substrate layer and the second substrate layer, and first substrate layer is located at the relatively described key of first silicon oxide layer
Close a side surface of semiconductor structure；Second substrate layer is located at the relatively described bonding semiconductor knot of second silicon oxide layer
One side surface of structure.
4. groove-shaped Transient Voltage Suppressor according to claim 3, which is characterized in that the first metal layer is located at institute
A side surface of relatively described first silicon oxide layer of the first substrate layer is stated, the second metal layer is located at the second substrate layer phase
To a side surface of second silicon oxide layer.
5. groove-shaped Transient Voltage Suppressor according to claim 1, which is characterized in that first connecting column with it is described
Second connecting column is opposite conduction type, and the spacer column includes semiconductor column described in even number.
6. a kind of production method of groove-shaped Transient Voltage Suppressor, which comprises the following steps:
S1: providing the first substrate of the first conduction type, etches first substrate and shape from the upper surface of first substrate
At at least two first grooves and at least one first semiconductor column between the first groove；
S2: providing the second substrate of the second conduction type, etches second substrate from the front of second substrate and is formed
Corresponding first semiconductor column and second groove compatible with first semiconductor column and the corresponding first groove and
The second semiconductor column compatible with the first groove；
S3: so that the front of second substrate is directed at the upper surface of first substrate, first semiconductor column is enabled to enter
The second groove, second semiconductor column enter the first groove thus by first substrate and second substrate
It combines；
S4: first time high-temperature heat treatment is carried out, so that first semiconductor column is bonded together with second semiconductor column
And bonding semiconductor structure is formed, the bonding semiconductor structure includes the first connecting column, the second connecting column and is located at described the
Spacer column between one connecting column and second connecting column；First connecting column is by first semiconductor column or described
Two semiconductor columns are constituted, and second connecting column is made of first semiconductor column or second semiconductor column, between described
Spacer post is made of first semiconductor column and/or second semiconductor column；
S5: forming the first metal layer for connecting first connecting column and connects the second metal layer of second connecting column.
7. the production method of groove-shaped Transient Voltage Suppressor according to claim 5, which is characterized in that S1 further include from
The lower surface of first substrate carries out O +ion implanted, and is formed in first substrate and connect the first groove and institute
State the first O +ion implanted area of the first semiconductor column；S2 further includes carrying out O +ion implanted from the back side of second substrate,
And the second O +ion implanted area of the connection second groove and second semiconductor column is formed in second substrate；S4
Also packet carries out second of high-temperature heat treatment, and first O +ion implanted area and second O +ion implanted area are converted respectively
At the first silicon oxide layer and the second silicon oxide layer.
8. the production method of groove-shaped Transient Voltage Suppressor according to claim 7, which is characterized in that form described the
The specific steps of one metal layer include: to etch first substrate layer and first silicon oxide layer from the lower surface, are formed
Connect the first contact hole of first connecting column；First metal is grown in the lower surface and first contact hole
Layer；
The specific steps for forming the second metal layer include: from the second substrate layer described in the back-etching and second oxygen
SiClx layer forms the second contact hole for connecting second connecting column；Institute is grown in the back side and second contact hole
State second metal layer.
9. the production method of groove-shaped Transient Voltage Suppressor according to claim 5, which is characterized in that the first time
High-temperature heat treatment is included in pretreatment 600min or more under 500-900 DEG C of nitrogen atmosphere, then carries out short annealing twice, anneals
1200 DEG C of temperature, heating rate is greater than 75 DEG C/s, and rate of temperature fall is greater than 60 DEG C/s, annealing time 30-45s.
10. the production method of groove-shaped Transient Voltage Suppressor according to claim 5, which is characterized in that described first
Connecting column is the first semiconductor column, and second connecting column is the second semiconductor column, and the spacer column includes one described first
Semiconductor column and second semiconductor column.
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| US20120012974A1 (en) * | 2010-07-15 | 2012-01-19 | Che-Hao Chuang | Lateral transient voltage suppressor for low-voltage applications |
| CN103887338A (en) * | 2012-12-21 | 2014-06-25 | 微机电科技香港有限公司 | Junction terminal applied to deep-groove super-junction device and manufacturing method thereof |
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