CN109065541B - Bidirectional transient voltage suppressor and preparation method thereof - Google Patents
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000009792 diffusion process Methods 0.000 claims abstract description 46
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Abstract
The invention discloses a bidirectional transient voltage suppressor, which comprises: a substrate of a first conductivity type; a first epitaxial layer of a second conductivity type formed on the upper surface of the substrate; a first trench formed on the first epitaxial layer; a second epitaxial layer of the first conductivity type formed within the first trench; a second trench formed on the first epitaxial layer; a third epitaxial layer of the second conductivity type formed in the second trench, the doping concentration of the third epitaxial layer being greater than the doping concentration of the first epitaxial layer; a third groove formed on the second epitaxial layer, a fourth groove formed on the third epitaxial layer, and a diffusion region formed on the inner walls of the third groove and the fourth groove; a dielectric layer formed on the first epitaxial layer; a first electrode penetrating the dielectric layer and connected to the diffusion region; and a second electrode connected to the lower surface of the substrate. The invention also discloses a preparation method of the bidirectional transient voltage suppressor. Which can solve the problem that a single voltage suppressor cannot perform bidirectional protection.
Description
Technical Field
The invention relates to the technical field of semiconductor device preparation, in particular to a bidirectional transient voltage suppressor and a preparation method thereof.
Background
The Transient Voltage Suppressor (TVS) is a solid semiconductor device specially designed for protecting sensitive semiconductor devices from transient voltage surge damage, and has the advantages of small clamping coefficient, small size, fast response, small leakage current, high reliability and the like, thus being widely applied to voltage transient and surge protection. Based on different applications, the transient voltage suppressor can play a circuit protection role by changing the surge discharge path and the clamping voltage of the transient voltage suppressor.
The conventional trench transient voltage suppressor can only realize unidirectional protection, and if bidirectional protection is required, a plurality of trench transient voltage suppressors are required to be connected in series or in parallel, so that the area of a device is increased, and the manufacturing cost is increased.
Disclosure of Invention
To overcome the disadvantages of the prior art, it is an object of the present invention to provide a bi-directional transient voltage suppressor without increasing the device area and manufacturing cost.
The second objective of the present invention is to provide a method for manufacturing a bi-directional transient voltage suppressor.
One of the purposes of the invention is realized by adopting the following technical scheme:
a bi-directional transient voltage suppressor, characterized by: it includes:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type formed on the upper surface of the substrate;
a first trench formed on the first epitaxial layer;
a second epitaxial layer of the first conductivity type formed within the first trench;
a second trench formed on the first epitaxial layer;
a third epitaxial layer of the second conductivity type formed in the second trench, the doping concentration of the third epitaxial layer being greater than the doping concentration of the first epitaxial layer;
the first epitaxial layer is formed on the first epitaxial layer, the second epitaxial layer is formed on the second epitaxial layer, the third epitaxial layer is formed on the second epitaxial layer, the fourth epitaxial layer is formed on the third epitaxial layer, and the diffusion regions are formed on the inner walls of the third trenches and the fourth trenches and have the first conductivity type, and the doping concentration of the diffusion regions is greater than that of the second epitaxial layer;
wherein the second conductivity type forms a forward PN junction with the first conductivity type;
a dielectric layer formed on the first epitaxial layer;
a first electrode penetrating through the dielectric layer and connected with the diffusion region;
and the second electrode is connected with the lower surface of the substrate.
Preferably, the substrate is an N-type substrate, the first epitaxial layer is a P-type epitaxial layer, the second epitaxial layer is an N-type epitaxial layer, the third epitaxial layer is a P + epitaxial layer, and the diffusion region is an N + type epitaxial layer.
Preferably, the bi-directional transient voltage suppressor further comprises a first metal layer disposed on the dielectric layer, the first metal layer extends to the diffusion region, and the first electrode is electrically connected to the first metal layer.
Preferably, the first metal layer is divided into three sections, and all the three sections of the first metal layer extend into the third trench to be in contact with the diffusion region.
Preferably, the bi-directional transient voltage suppressor further comprises a second metal layer formed on the lower surface of the substrate, and the second electrode is electrically connected to the second metal layer.
Preferably, there are two of the first grooves, one of the second grooves, and the second groove is disposed between the two first grooves.
Preferably, the second epitaxial layer is provided with a third trench, and the third epitaxial layer is provided with two fourth trenches.
The second purpose of the invention is realized by adopting the following technical scheme:
a preparation method of the bidirectional transient voltage suppressor comprises the following steps:
s1, providing a substrate of a first conduction type;
s2, preparing a first epitaxial layer of a second conduction type on the upper surface of the substrate, and forming a first groove on the first epitaxial layer;
s3, forming a second epitaxial layer of the first conduction type on the first groove and the first epitaxial layer;
s4, removing the second epitaxial layer on the first epitaxial layer, and reserving the second epitaxial layer in the first groove;
s5, forming a second groove on the first epitaxial layer;
s6, forming a third epitaxial layer of the second conductivity type on the second trench, the second epitaxial layer and the first epitaxial layer, wherein the doping concentration of the third epitaxial layer is greater than that of the first epitaxial layer;
s7, removing the second epitaxial layer and the third epitaxial layer on the first epitaxial layer, reserving the third epitaxial layer in the second groove, forming a third groove on the second epitaxial layer, and forming a fourth groove on the third epitaxial layer;
s8, diffusing on the inner walls of the third trench and the fourth trench to form a diffusion region of a first conductivity type, wherein the doping concentration of the diffusion region is greater than that of the second epitaxial layer;
s9, forming a dielectric layer on the first epitaxial layer, and forming a first electrode penetrating through the dielectric layer and connected with the diffusion region;
and S10, forming a second electrode on the lower surface of the substrate.
Further, the preparation method further includes step S11: and forming a first metal layer on the dielectric layer, wherein the first metal layer extends to the diffusion region, and the first electrode is electrically connected with the first metal layer.
Further, the preparation method further includes step S12: and forming a second metal layer on the lower surface of the substrate, wherein the second electrode is electrically connected with the second metal layer.
Compared with the prior art, the invention has the beneficial effects that:
if the first conduction type is an N-type conduction type and the second conduction type is a P-type conduction type, after current flows into the diffusion region from the first electrode, the current in the third groove flows through the second epitaxial layer, and when the current is ready to enter the first epitaxial layer from the second epitaxial layer, the second epitaxial layer and the first epitaxial layer form a reverse PN junction because the second epitaxial layer is the first conduction type and the first epitaxial layer is the second conduction type, so that the current cannot enter the first epitaxial layer when the current is cut off, and the current flowing into the fourth groove is cut off because the diffusion region and the third epitaxial layer form a reverse PN junction; when current reversely flows into the substrate from the second electrode, the substrate and the first epitaxial layer form a reverse PN junction, so that the current is cut off and cannot flow through the first epitaxial layer, and vice versa. Therefore, the bidirectional transient voltage suppressor can prevent bidirectional current from flowing in and has a bidirectional protection function, so that a plurality of transient voltage suppressors do not need to be connected in series or in parallel for bidirectional protection, and the area and the manufacturing cost of a device are reduced.
Drawings
FIG. 1 is a schematic diagram of a bi-directional transient voltage suppressor according to the present invention;
FIG. 2 is an equivalent circuit diagram of the bi-directional TVS of the present invention;
FIG. 3 is a flow chart of a method of making a bi-directional transient voltage suppressor according to the present invention;
fig. 4 is a schematic process flow diagram of the bidirectional transient voltage suppressor manufacturing method of the present invention.
In the figure: 1. a bi-directional transient voltage suppressor; 10. a substrate; 20. a first epitaxial layer; 21. a first trench; 22. a second trench; 30. a second epitaxial layer; 31. a third trench; 32. a fourth trench; 40. a third epitaxial layer; 50. a diffusion region; 60. a first metal layer; 61. a first electrode; 70. a dielectric layer; 80. a second metal layer; 81. a second electrode; 91. a first diode; 92. a second diode; 93. a third diode; 94. a fourth diode; 95. and a fifth diode.
Detailed Description
The invention will be further described with reference to the accompanying drawings and the detailed description below:
a bi-directional transient voltage suppressor 1(TVS) as shown in fig. 1, comprising: a substrate 10 of a first conductivity type; a first epitaxial layer 20 of a second conductivity type formed on an upper surface of the substrate 10; a first trench 21 formed on the first epitaxial layer 20; a second epitaxial layer 30 of the first conductivity type formed within the first trench 21; a second trench 22 formed on the first epitaxial layer 10; a third epitaxial layer 40 of the second conductivity type formed in the second trench 22, the doping concentration of the third epitaxial layer 40 being greater than the doping concentration of the first epitaxial layer 10; a third trench 31 formed on the second epitaxial layer 30, a fourth trench 32 formed on the third epitaxial layer 40, and a diffusion region 50 of the first conductivity type formed on the inner walls of the third trench 31 and the fourth trench 32, wherein the doping concentration of the diffusion region 50 is greater than that of the second epitaxial layer 30; a dielectric layer 70 formed on the first epitaxial layer 10; a first electrode 61 connected to the diffusion region 50 through the dielectric layer 70; and a second electrode 81 connected to the lower surface of the substrate 10.
In the above embodiment, if the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type, when a current flows from the first electrode 61 into the diffusion region 50, a current in the third trench 31 flows through the second epitaxial layer 30, and when a current is ready to enter the first epitaxial layer 20 from the second epitaxial layer 30, since the second epitaxial layer 30 is the first conductivity type and the first epitaxial layer 20 is the second conductivity type, the second epitaxial layer 30 and the first epitaxial layer 20 form a reverse PN junction, so that a current is not allowed to enter the first epitaxial layer 20, and similarly, a current flowing into the fourth trench 32 is blocked because the diffusion region 50 and the third epitaxial layer 40 form a reverse PN junction; when a current flows in a reverse direction from the second electrode 81 into the substrate 10, the substrate 10 forms a reverse PN junction with the first epitaxial layer 20, and thus the current is cut off and cannot flow through the first epitaxial layer 20.
If the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type, after a current flows into the diffusion region 50 from the first electrode 61, the current in the third trench 31 flows through the second epitaxial layer 30, the current enters the first epitaxial layer 20 from the second epitaxial layer 30, when the current is ready to enter the substrate 10, the current cannot enter the substrate 10 and is cut off because the first epitaxial layer 20 and the substrate 10 form a reverse PN junction, and similarly, the current flowing into the fourth trench 32 enters the third epitaxial layer 40 and then enters the first epitaxial layer 20 from the third epitaxial layer 40, and when the current is ready to enter the substrate 10, the current cannot enter the substrate 10 and is cut off because the first epitaxial layer 20 and the substrate 10 form a reverse PN junction; when a current reversely flows into the substrate 10 from the second electrode 81, the current flows into the first epitaxial layer 20 from the substrate 10, and the current is ready to flow into the second epitaxial layer 30 in the third trench 31, the current is cut off because the first epitaxial layer 20 and the second epitaxial layer 30 form a reverse PN junction, and the current flowing into the fourth trench 32 flows into the third epitaxial layer 40, and the current is cut off and cannot flow into the diffusion region 50 because the third epitaxial layer 40 and the diffusion region 50 form a reverse PN junction.
Therefore, the bidirectional transient voltage suppressor 1 can prevent bidirectional current from flowing in, and has a bidirectional protection function, so that a plurality of transient voltage suppressors do not need to be connected in series or in parallel for bidirectional protection, and the device area and the manufacturing cost are reduced.
When the voltage between the first metal layer 60 and the substrate 10 is large, the bidirectional transient voltage suppressor 1 is broken down to become a resistor, and functions as a step-down protection external device. Therefore, the bidirectional transient voltage suppressor 1 can prevent bidirectional current from flowing in and has a bidirectional protection function. In addition, the resistance of the diffusion region 50 is less than the resistance of the second epitaxial layer 30, and the resistance of the third epitaxial layer 40 is less than the resistance of the first epitaxial layer 20.
As shown in fig. 1, preferably, the bi-directional transient voltage suppressor 1 further includes a first metal layer 60, the first metal layer 60 is disposed on the dielectric layer 70, the first metal layer 60 extends to the diffusion region 50, and the first electrode 61 is electrically connected to the first metal layer 60. The first metal layer 60 is divided into three segments, and all the three segments of the first metal layer 60 extend into the third trench 31 to contact with the diffusion region 50. The bi-directional transient voltage suppressor 1 further comprises a second metal layer 80 formed on the lower surface of the substrate 10, and the second electrode 81 is electrically connected to the second metal layer 80.
As shown in fig. 1-2, the three first metal layers 60 divide the P-type epitaxial layer into three parts, the first metal layer 60 of each part is in contact with the diffusion regions 50 in the third trench 31 and the fourth trench 32, and the first pin 61 can be disposed on the first metal layer 60 of each part, which corresponds to dividing the present bi-directional transient voltage suppressor 1 into three "chips", each "chip" is electrically connected to the outside through the first pin 61, each "chip" is separated by the dielectric layer 70, each chip includes the diffusion region 50, the second epitaxial layer 30 or the third epitaxial layer 40, the first epitaxial layer 20, the substrate 10, the second metal layer 80 and the second pin 81, when the voltage is too high and the reverse PN junction is broken down, the current of each chip passes through the first pin 61 and flows into the diffusion region 50 through the first metal layers 60 of each part, then into the second epitaxial layer 30 or the third epitaxial layer 40, then into the first epitaxial layer 20, the substrate 10 and the second metal layer 80 together, and finally out of the second lead 81, and vice versa when the current is reversed. The first lead 61 and the second lead 81 are both convenient for electrically connecting to an external device, and the dielectric layer 70 is preferably a silicon oxide layer. The voltages experienced by the three "chips" may be the same and the currents eventually flow together from the second pin 81 so that the three "chips" may be seen in parallel. In addition, the first metal layer 60 and the second metal layer 80 are both favorable for heat dissipation.
In order to reduce the power of the bi-directional transient voltage suppressor 1, the formula P is U2Where P is power, U is voltage applied to the chip, and R is total chip resistance, it can be seen that the higher the chip resistance is, the lower the power is. Thus, two first trenches 21, one second trench 22, and the second trench 22 are disposed between the two first trenches 21, two third trenches 31 are disposed on the N-type epitaxial layer, and two fourth trenches 32 are disposed on the P + epitaxial layer, so that the number of trenches is increased to increase the resistance of the device, thereby reducing the power of the bi-directional transient voltage suppressor 1.
As shown in fig. 1-2, if PN is equivalent to a diode, it is assumed that current flows from the first electrode 61, the substrate 10 is an N-type substrate, the first epitaxial layer 20 is a P-type epitaxial layer, the second epitaxial layer 30 is an N-type epitaxial layer, the third epitaxial layer 40 is a P + epitaxial layer, and the diffusion region 50 is an N + epitaxial layer. The second epitaxial layer 30 on the left side of the bidirectional transient voltage suppressor 1 forms a reverse PN junction with the first epitaxial layer 20, similar to the first diode 91 in fig. 2, the second epitaxial layer 30 on the right side forms a reverse PN junction with the first epitaxial layer 20, similar to the fourth diode 94 in fig. 2, and the reverse PN junctions on the left and right sides are connected in parallel, similar to the first diode 91 and the fourth diode 94 in fig. 2; the two diffusion regions 50 in the middle of the bidirectional transient voltage suppressor 1 form reverse PN junctions with the third epitaxial layer 40, respectively, and the two reverse PN junctions are connected in parallel, similarly to the second diode 92 and the third diode 93 connected in parallel in fig. 2; since the above four reverse PN junctions are connected in parallel, the first diode 91, the second diode 92, the third diode 93, and the fourth diode 94 are connected in parallel similarly to fig. 2; the first epitaxial layer 20 at the lower end of the bi-directional tvs 1 forms a forward PN junction with the substrate 10, similar to the forward fifth diode 95 in fig. 2, and the fifth diode 95 is connected in series with the four parallel reverse diodes, so that the bi-directional tvs 1 can be equivalent to the circuit shown in fig. 2.
In addition, as shown in fig. 1-2, since the diffusion regions 50 on both sides of the bidirectional tvs 1 can be respectively connected to the first electrodes 61, the first electrodes 61 can be connected to both the first diode 91 and the fourth diode 94 in fig. 2, so that the bidirectional tvs 1 can be connected to three sets of circuits, thereby respectively protecting the three sets of circuits.
It is understood that in other embodiments, the substrate 10 in the present bi-directional tvs 1 may be a P-type substrate, and meanwhile, the first epitaxial layer 20 may be an N-type epitaxial layer, the second epitaxial layer 30 may be a P-type epitaxial layer, the third epitaxial layer 40 may be an N + epitaxial layer, and the diffusion region 50 is a P + epitaxial layer, which operate in the same manner.
As shown in fig. 2 to 3, the present invention also discloses a method for preparing the bidirectional transient voltage suppressor 1, which comprises the following steps:
s1, providing a substrate 10 of a first conductivity type;
s2, preparing a first epitaxial layer 20 of a second conductivity type on the upper surface of the substrate 10, and forming a first trench 21 on the first epitaxial layer 20;
s3, forming a second epitaxial layer 30 of the first conductivity type on the first trenches 21 and the first epitaxial layer 20;
s4, removing the second epitaxial layer 30 on the first epitaxial layer 20, and remaining the second epitaxial layer 30 in the first trench 21;
s5, forming a second trench 22 on the first epitaxial layer 20;
s6, forming a third epitaxial layer 40 of the second conductivity type on the second trench 22, the second epitaxial layer 30 and the first epitaxial layer 20, wherein the doping concentration of the third epitaxial layer 40 is greater than the doping concentration of the first epitaxial layer 20;
s7, removing the second epitaxial layer 30 and the third epitaxial layer 40 on the first epitaxial layer 20, leaving the third epitaxial layer 40 in the second trench 22, forming a third trench 31 on the second epitaxial layer 30, and forming a fourth trench 32 on the third epitaxial layer 40;
s8, forming a diffusion region 50 of the first conductivity type by diffusing on the inner walls of the third trench 31 and the fourth trench 32, wherein the doping concentration of the third epitaxial layer 40 is greater than that of the first epitaxial layer 20;
s9, forming a dielectric layer 70 on the first epitaxial layer 20, and forming a first electrode 61 penetrating the dielectric layer 70 and connected to the diffusion region 50;
s10, forming a second electrode 81 on the lower surface of the substrate 10.
In the above embodiment, the first trench 21, the second trench 22, and the third trench 31 may all be formed by dry etching, the epitaxial layer to be removed in the process may be removed by a photoresist, and in the preparation process, only the epitaxial layers or the trenches are sequentially provided with the epitaxial layers and the dielectric layer 70, which has no high difficulty, and can be prepared in a conventional semiconductor process, and the preparation method thereof is simple and easy.
Further, in order to facilitate the bidirectional transient voltage suppressor 1 to electrically connect external devices and improve heat dissipation efficiency, the manufacturing method further includes step S11: a first metal layer 60 is formed on the dielectric layer 70, the first metal layer 60 extends to the diffusion region 50, and the first electrode 61 is electrically connected to the first metal layer 60. Similarly, the preparation method further includes step S12: a second metal layer 80 is formed on the lower surface of the substrate 10, and the second electrode 81 is electrically connected to the second metal layer 80.
In summary, when the bidirectional Transient Voltage Suppressor (TVS)1 passes forward and reverse currents, a reverse PN junction can be formed inside the TVS to prevent the current from passing through the TVS, so that a multi-path bidirectional protection function is realized, and the power of the TVS is low. In addition, the preparation method is simple, and the production cost of the bidirectional transient voltage suppressor 1 is also reduced.
The foregoing illustrates and describes the principles, general features, and advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are given by way of illustration of the principles of the present invention, and that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A bi-directional transient voltage suppressor, characterized by: it includes:
a substrate of a first conductivity type;
a first epitaxial layer of a second conductivity type formed on the upper surface of the substrate;
a first trench formed on the first epitaxial layer;
a second epitaxial layer of the first conductivity type formed within the first trench;
a second trench formed on the first epitaxial layer;
a third epitaxial layer of the second conductivity type formed in the second trench, the doping concentration of the third epitaxial layer being greater than the doping concentration of the first epitaxial layer;
the first epitaxial layer is formed on the first epitaxial layer, the second epitaxial layer is formed on the second epitaxial layer, the third epitaxial layer is formed on the second epitaxial layer, the fourth epitaxial layer is formed on the third epitaxial layer, and the diffusion regions of the first conductivity type are formed on the inner walls of the third trenches and the fourth trenches, wherein the doping concentration of the diffusion regions is greater than that of the second epitaxial layer;
a dielectric layer formed on the first epitaxial layer;
a first electrode penetrating through the dielectric layer and connected with the diffusion region;
and the second electrode is connected with the lower surface of the substrate.
2. The bi-directional transient voltage suppressor of claim 1, wherein: the substrate is an N-type substrate, the first epitaxial layer is a P-type epitaxial layer, the second epitaxial layer is an N-type epitaxial layer, the third epitaxial layer is a P + epitaxial layer, and the diffusion region is an N + type epitaxial layer.
3. The bi-directional transient voltage suppressor of claim 1, wherein: the bidirectional transient voltage suppressor further comprises a first metal layer, the first metal layer is arranged on the dielectric layer, the first metal layer extends to the diffusion region, and the first electrode is electrically connected with the first metal layer.
4. The bi-directional transient voltage suppressor of claim 3, wherein: the first metal layer is divided into three sections, and the three sections of the first metal layer extend into the third groove and are in contact with the diffusion region.
5. The bi-directional transient voltage suppressor of claim 4, wherein: the bidirectional transient voltage suppressor further comprises a second metal layer formed on the lower surface of the substrate, and the second electrode is electrically connected with the second metal layer.
6. The bi-directional transient voltage suppressor of claim 1, wherein: the number of the first grooves is two, the number of the second grooves is one, and the second grooves are located between the two first grooves.
7. The bi-directional transient voltage suppressor of claim 1, wherein: and each second epitaxial layer is provided with a third groove, and the third epitaxial layer is provided with two fourth grooves.
8. A preparation method of a bidirectional transient voltage suppressor is characterized by comprising the following steps:
s1, providing a substrate of a first conduction type;
s2, preparing a first epitaxial layer of a second conduction type on the upper surface of the substrate, and forming a first groove on the first epitaxial layer;
s3, forming a second epitaxial layer of the first conduction type on the first groove and the first epitaxial layer;
s4, removing the second epitaxial layer on the first epitaxial layer, and reserving the second epitaxial layer in the first groove;
s5, forming a second groove on the first epitaxial layer;
s6, forming a third epitaxial layer of the second conductivity type on the second trench, the second epitaxial layer and the first epitaxial layer, wherein the doping concentration of the third epitaxial layer is greater than that of the first epitaxial layer;
s7, removing the second epitaxial layer and the third epitaxial layer on the first epitaxial layer, reserving the third epitaxial layer in the second groove, forming a third groove on the second epitaxial layer, and forming a fourth groove on the third epitaxial layer;
s8, diffusing on the inner walls of the third trench and the fourth trench to form a diffusion region of a first conductivity type, wherein the doping concentration of the diffusion region is greater than that of the second epitaxial layer;
s9, forming a dielectric layer on the first epitaxial layer, and forming a first electrode penetrating through the dielectric layer and connected with the diffusion region;
and S10, forming a second electrode on the lower surface of the substrate.
9. The method for preparing the bi-directional transient voltage suppressor according to claim 8, wherein said method further comprises step S11: and forming a first metal layer on the dielectric layer, wherein the first metal layer extends to the diffusion region, and the first electrode is electrically connected with the first metal layer.
10. The method for preparing the bi-directional transient voltage suppressor according to claim 8, wherein said method further comprises step S12: and forming a second metal layer on the lower surface of the substrate, wherein the second electrode is electrically connected with the second metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810780548.0A CN109065541B (en) | 2018-07-17 | 2018-07-17 | Bidirectional transient voltage suppressor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810780548.0A CN109065541B (en) | 2018-07-17 | 2018-07-17 | Bidirectional transient voltage suppressor and preparation method thereof |
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| CN109950326A (en) * | 2019-04-15 | 2019-06-28 | 深圳市槟城电子有限公司 | A kind of bilateral diode and preparation method thereof, overvoltage protection |
| CN111584480B (en) * | 2020-04-17 | 2023-10-31 | 深圳方正微电子有限公司 | Semiconductor device and method for manufacturing the same |
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