JP5405029B2 - TRIAC - Google Patents

Description

  The present invention relates to a triac, and more particularly to an improvement for improving a withstand voltage characteristic of a triac, particularly a lightning surge characteristic.

  The triac is an AC control element that has one gate terminal and a pair of main terminals, and can perform turn-on control between the main terminals using the gate terminals. Triac is also called a bidirectional thyristor because it can perform turn-on control in both directions between the main terminals using a common gate terminal, and is a control circuit for AC power supplies, for example, power control circuits such as motors and heaters. (For example, Patent Documents 1 and 2).

  FIG. 8 is a plan view showing an example of the configuration of the conventional triac 102. 9 and 11 are cross-sectional views of the triac 102 shown in FIG. 8 cut along the line EE and FIG. 10 along the line FF.

  When a high voltage exceeding 1 kV is applied between the main terminals T1 and T2 of the triac 102 during a lightning strike, a leak current flows in the triac 102, and the triac 102 is turned on by this leak current. In the case of the illustrated mesa structure triac 102, if a high voltage is applied in the off state, electric field concentration occurs in the vicinity of the mesa groove 11, and leakage from the vicinity of the wall surface of the mesa groove 11 to the main terminal T1 or T2 having a low potential. Current flows. When this leakage current flows laterally in the p-type semiconductor layer 31 or 32, a voltage drop occurs in the p-type semiconductor layers 31 and 32, and the triac 102 is turned on.

  FIG. 9 and FIG. 10 are diagrams showing a state when a high voltage exceeding 1 kV is applied between the main terminals T1 and T2 with the gate terminal Tg being opened and the main terminal T2 being positive (positive potential). The path of the leakage current at that time is shown. The leakage current flows from the vicinity of the mesa groove 11 across the p-type semiconductor layer 31 to the main terminal T1. At this time, a voltage drop is caused by the resistance of the p-type semiconductor layer 31, and this potential difference is used as a trigger to turn on the triac 102. That is, the triac 102 is turned on based on the same principle as that of the turn-on in the I mode.

  In FIG. 9 (EE cut surface), the resistance value is high in the thin p-type semiconductor layer 31 immediately below the n-type semiconductor layer 41. When a leak current flows through this pinch resistor, the pn junction J3 between the semiconductor layers 31 and 41 is forward-biased by the voltage drop, and electrons are transferred from the n-type semiconductor layer 41 through the p-type semiconductor layer 31 to the n-type semiconductor layer 30. Is injected. As a result, the potential of the n-type semiconductor layer 30 is lower than that of the p-type semiconductor layer 32, the pn junction J2 between the semiconductor layers 30 and 32 is also forward biased, and the holes in the p-type semiconductor layer 32 are transferred to the n-type semiconductor layer 30. The triac 102 is turned on. Therefore, in this drawing, the vicinity of the right end of the n-type semiconductor layer 41 is first turned on, and then the on-state spreads to the left, and finally the entire n-type semiconductor layer 41 reaches the on-state. .

  Similarly, in FIG. 10 (FF cut view), a leak current that causes a voltage drop in the p-type semiconductor layer 31 passes through the p-type semiconductor layer 31 below the n-type semiconductor layer 41 and passes through the left mesa groove. The current flows from around 11 to the main terminal T1. However, the current path in FIG. 10 has a smaller width of the n-type semiconductor layer 41 than the current path in FIG. 9, so that the pinch resistance is small and the voltage drop generated in the p-type semiconductor layer 31 is also small. Accordingly, it can be seen that the right end of the n-type semiconductor layer 41 in FIG. 9 is turned on earlier than the left end of the n-type semiconductor layer 41 in FIG.

  FIG. 11 (EE cutaway view) shows a state when a high voltage exceeding 1 kV is applied between the main terminals T1 and T2 with the main terminal T1 being positive (positive potential) when the gate terminal Tg is opened. The path of the leakage current at that time is shown. The leak current flows from the vicinity of the mesa groove 11 across the p-type semiconductor layer 32 to the main terminal T2. At this time, a voltage drop is caused by the resistance of the p-type semiconductor layer 32, and this potential difference serves as a trigger to turn on the triac 102.

  The thin p-type semiconductor layer 32 on the n-type semiconductor layer 42 has a high resistance value. When a leak current flows through this pinch resistor, the pn junction J4 between the semiconductor layers 32 and 42 is forward-biased due to the voltage drop, and from the n-type semiconductor layer 42 to the n-type semiconductor layer 30 through the p-type semiconductor layer 32. Electrons are injected. As a result, the potential of the n-type semiconductor layer 30 is lower than that of the p-type semiconductor layer 31, the pn junction J1 between the semiconductor layers 30 and 31 is also forward biased, and the holes in the p-type semiconductor layer 31 are transferred to the n-type semiconductor layer 30. The triac 102 is turned on. Therefore, in this figure, the vicinity of the right end of the overlapping region of the main terminal T1 and the n-type semiconductor layer 42 is turned on first, and then the ON state spreads to the left, and finally the entire overlapping region is ON. It becomes.

  As described with reference to FIGS. 8 to 11, when a surge voltage is applied between the main terminals T <b> 1 and T <b> 2, a position where a large voltage drop is caused by a leak current in the p-type semiconductor layer 31 or the p-type semiconductor layer 32. It is thought that the turn-on occurs first in, and then the on-state spreads. That is, in the triac 102 to which the surge voltage is applied, any one point is first turned on, and then the on state is spread.

  Therefore, a large current flows immediately after the surge voltage is applied to the local region that is first turned on. The lightning surge voltage of the triac 102 is determined by the characteristics of this local region, and there is a problem that it is not easy to greatly improve the lightning surge voltage.

Various methods for improving the surge resistance of a semiconductor rectifier have been proposed (for example, Patent Documents 3 and 4). Patent Document 3 discloses a method of suppressing a surge withstand phenomenon caused by uncertain turn-on operation by eliminating surface reactive current in a two-terminal bidirectional thyristor. Further, in Patent Document 4, in a semiconductor surge preventing element in which a thyristor and a diode are connected in antiparallel, one of the thyristor and the diode is arranged at the center and the other is arranged at the outer peripheral portion, and one heat is absorbed by the other. A method for improving the surge withstand capability is described. However, such a conventional method has a problem that it is not easy to greatly improve the lightning surge characteristics.
JP 2005-26262 A Japanese Patent Laid-Open No. 10-256530 JP-A-5-275687 JP-A-10-98202

  This invention is made | formed in view of said situation, and it aims at improving the lightning surge characteristic of a triac and providing a highly reliable triac.

A triac according to a first aspect of the present invention includes a first semiconductor layer and a second semiconductor layer having a second conductivity type formed by diffusing impurities from both main surfaces of a first conductivity type semiconductor substrate, and a first semiconductor layer And selectively diffusing the impurities from the surface of the second semiconductor layer, and the third and fourth semiconductor layers of the first conductivity type formed so as not to overlap each other. A first conductive type fifth semiconductor layer formed in a planar region not overlapping with the third semiconductor layer, a first main terminal formed on the first and third semiconductor layers, and on the first and fourth semiconductor layers; a gate terminal formed on, and a second main terminal formed on the second and fifth semiconductor layers, third and fifth semiconductor layers, respectively formed in a planar area to be symmetrical, fifth The semiconductor layer is formed so as to be surrounded by the third and fourth semiconductor layers. To have.

With such a configuration, two or more different local regions in the triac can be turned on at the initial turn-on stage when applying a surge voltage. Therefore, current concentration at turn-on can be reduced. Moreover, current concentration at turn-on can be alleviated regardless of the direction of the surge voltage applied between the main terminals. Further, it is possible to form both of them symmetrically while ensuring the necessary areas as the regions of the third and fourth semiconductor layers without significantly increasing the chip area.

In the triac according to the second aspect of the present invention, the fifth semiconductor layer is formed as a substantially square region, the fourth semiconductor layer is formed on a diagonal line of the fifth semiconductor layer, and the third semiconductor layer is symmetric with respect to the diagonal line. The shape becomes.

  According to the present invention, the third and fifth semiconductor layers are respectively formed in symmetrical plane regions, so that two or more different local regions in the triac are turned on at the initial stage of turn-on. For this reason, current concentration at the time of turn-on can be reduced. Therefore, the lightning surge characteristic of the triac can be greatly improved, and a highly reliable triac can be realized.

Embodiment 1 FIG.
FIG. 1 is a plan view showing a configuration example of a triac 100 according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view of the triac 100 of FIG. 1 taken along the line AA. If this triac 100 is compared with the conventional triac 102, its planar layout is different. In particular, the n-type semiconductor layers 41 and 42 are different in that the planar shapes thereof are line symmetric.

  First, the cross-sectional structure of the triac 100 will be described. The triac 100 has a pnp structure in which p-type semiconductor layers 31 and 32 are formed on both surfaces of an n-type semiconductor substrate 10 and the n-type semiconductor layer 30 is sandwiched between the p-type semiconductor layers 31 and 32. Further, n-type semiconductor layers 41 to 43 are further formed in the p-type semiconductor layers 31 and 32. The n-type semiconductor layers 41 and 43 are formed in the p-type semiconductor layer 31 as regions separated from each other, and the n-type semiconductor layer 42 is formed as a region that does not overlap with the n-type semiconductor layers 41 and 43 on the plane. Formed in layer 32.

  The triac 100 includes a pair of main terminals T1 and T2 and a gate terminal Tg. The main terminal T1 and the gate terminal Tg are both formed on the upper surface of the semiconductor substrate 10. The main terminal T1 is electrically connected to the n-type semiconductor layer 41 and the p-type semiconductor layer 31, and the gate terminal Tg is connected to the n-type semiconductor layer 43. The p-type semiconductor layer 31 is electrically connected. The main terminal T <b> 2 is formed on the lower surface of the semiconductor substrate 10 and is electrically connected to the n-type semiconductor layer 42 and the p-type semiconductor layer 32. The mesa groove 11 is an annular groove formed on the upper surface of the semiconductor substrate 10, and the p-type semiconductor layer 31 is separated by the mesa groove 11.

  Next, the planar layout of the triac 100 will be described. The triac 100 is formed in a substantially square semiconductor substrate 10, and mesa grooves 11 are formed in the vicinity of the outer edge of the semiconductor substrate 10. The mesa groove 11 has a substantially square annular shape, and a substantially square mesa region 13 is formed inside thereof. In the mesa region 13, n-type semiconductor layers 41 to 43, a main terminal T1, a gate terminal Tg, and the like are arranged.

  The n-type semiconductor layer 42 is disposed substantially at the center of the mesa region 13, and the n-type semiconductor layers 41 and 43 are disposed so as to surround the outside of the n-type semiconductor layer 42. The n-type semiconductor layer 43 and the gate terminal Tg are arranged on the diagonal line of the n-type semiconductor layer 42, that is, at the corner of the mesa region 13, and the n-type semiconductor layer 41 is n n except the vicinity of the corner. A region that substantially surrounds the n-type semiconductor layer 42 is formed along the outer edge of the n-type semiconductor layer 42.

  Both the gate terminal Tg and the n-type semiconductor layer 43 are formed as diagonal lines of the mesa region 13, that is, as regions that are symmetric with respect to the n-type semiconductor layer 42. The gate terminal Tg has a substantially square shape, and the region on the center side of the mesa region 13 is disposed in the region of the n-type semiconductor layer 43. On the other hand, a region that does not overlap with the n-type semiconductor layer 43 remains on the peripheral side of the mesa region 13 of the gate terminal Tg.

  The n-type semiconductor layer 43 is arranged so that the center side of the mesa region 13 protrudes from the gate terminal Tg and the end side does not overlap the gate terminal Tg. On the other hand, a notch is formed around the mesa region 13 of the n-type semiconductor layer 43, leaving at least a region of the gate terminal Tg that does not overlap with the n-type semiconductor layer 43. In this example, the n-type semiconductor layer 43 has a “<” shape formed along two adjacent sides of the gate terminal Tg, and a part of the n-type semiconductor layer 43 is located on the center side of the mesa region 13 from the gate terminal Tg. It is arranged so that it protrudes. That is, the n-type semiconductor layer 43 is bent at 90 degrees so as to protrude toward the n-type semiconductor layer 42, and the outer corner side thereof is disposed so as to protrude from the gate terminal Tg to the center side of the mesa region 13.

  The main terminal T1 is formed on the upper surface of the semiconductor substrate 10 so as to overlap the n-type semiconductor layers 41 and 42. Further, it is formed as a “<”-shaped region so as not to overlap with the corner gate terminal Tg and the n-type semiconductor layer 43. The main terminal T <b> 2 is disposed over the entire lower surface of the semiconductor substrate 10, i.e., inside and outside the mesa region 13.

  Further, the n-type semiconductor layers 41 and 42 are arranged with a predetermined interval d, and the | dv / dt | c withstand capability of the triac 100 is ensured. For example, when using with an inductive load, the phase of the current lags behind the voltage, and a sudden reverse voltage is applied at the moment of turn-off. At this time, carriers remain in the depletion layer in the n-type semiconductor layer 30, and a malfunction occurs in which the remaining carriers cannot be turned off if holes move. Therefore, if the n-type semiconductor layers 41 and 42 are arranged at a predetermined interval d, the recombination of carriers can be promoted to quickly turn off the element, and such a malfunction can be prevented.

  3 and 4 are explanatory diagrams showing the operation when a surge voltage is applied to the triac 100. FIG. In the triac 100, by devising the planar layout of the n-type semiconductor layers 41 and 42, two or more different local regions in the triac 100 are turned on in the initial stage of turn-on, and current concentration at the time of turn-on is reduced. ing. Moreover, regardless of the direction of the surge voltage applied between the main terminals T1 and T2, two or more local regions are turned on in the initial turn-on stage.

  FIG. 3 is a diagram illustrating a state when a surge voltage is applied in which the main terminal T2 is positive (positive potential) and the main terminal T1 is negative (negative potential). FIG. FIG. 5B is a cross-sectional view taken along the line BB. When a positive voltage is applied to the main terminal T2, electrons are transferred from the p-type semiconductor layer 31 to the n-type semiconductor layer 30 due to a voltage drop caused by the pinch resistance of the p-type semiconductor layer 31 below the n-type semiconductor layer 41. It is injected and turned on. That is, turn-on starts from the end of the n-type semiconductor layer 41 where the pinch resistance is the largest.

  In the triac 100, the n-type semiconductor layer 41 is formed to be a long and thin line-symmetric region on a plane. For this reason, at the time of turn-on, first, the local regions 51 near both ends of the n-type semiconductor layer 41 are turned on, and thereafter, as time passes, the on-region extends from each of these local regions 51 to the entire region of the n-type semiconductor layer 41. And spread. That is, since there are two local regions 51 that are turned on in the initial stage of turn-on, current concentration in the local region can be reduced. In addition, since the ON region expands from each of these local regions 51, the ON region can be expanded quickly, and the time for current to concentrate in the local region can be shortened. In this manner, local current concentration in the triac 100 at the time of turn-on is dispersed at an early stage, so that the device is not easily destroyed when a surge voltage is applied, and lightning surge resistance can be improved.

  FIG. 4 is a diagram showing a state in which a surge voltage is applied in which the main terminal T1 is positive (positive potential) and the main terminal T2 is negative (negative potential), and (a) in FIG. FIG. 4B is a cross-sectional view taken along the line CC. When a positive voltage is applied to the main terminal T1, electrons are injected from the p-type semiconductor layer 32 to the n-type semiconductor layer 30 due to the pinch resistance of the p-type semiconductor layer 32 on the n-type semiconductor layer 42 and turned on. It becomes a state. That is, the turn-on starts from the end of the n-type semiconductor layer 42 where the pinch resistance is the largest.

  In the triac 100, the n-type semiconductor layer 42 is formed as a substantially square region. For this reason, at the time of turn-on, first, the local regions 52 located near the four vertices of the n-type semiconductor layer 42 are turned on, and the on-state spreads from these local regions 52 as time passes. That is, since there are four local regions 52 that are turned on in the initial stage of turn-on, current concentration in the local region can be reduced. Further, since the ON region spreads from each of these local regions 52, the ON region can be quickly expanded, and the time for current to concentrate in the local region can be shortened. In this way, by dispersing the current concentration in the triac 100 at the time of turn-on at an early stage, the device is less likely to be destroyed when a surge voltage is applied, and the lightning surge resistance can be improved.

  In the conventional triac 102, there is only one local region that is turned on at turn-on. On the other hand, in the triac 100 according to the present invention, two or more different local regions are turned on in the initial stage of turn-on by devising the shape of the planar regions of the n-type semiconductor layers 41 and 42. For this reason, current concentration in the initial stage of turn-on can be alleviated, and the on-state region can be quickly widened to shorten the time during which current concentration occurs in the local region. Therefore, the lightning surge voltage can be increased as compared with the conventional triac 102.

  FIG. 5 is an explanatory diagram for explaining an example of the manufacturing method of the triac according to the present embodiment, and shows an AA section at the time of manufacturing. An n-type silicon wafer is used as the semiconductor substrate 10. An impurity such as boron (B) is selectively and deeply diffused from both surfaces of the semiconductor substrate 10, and a separation p-type semiconductor layer 33 extending from one main surface to the other main surface is formed. It is formed. Next, p-type impurities such as gallium (Ga) and boron (B) are diffused from both sides of the entire region separated by the p-type semiconductor layer 33 so that the n-type semiconductor layer 30 is interposed therebetween. Layers 31 and 32 are formed.

  Next, n-type impurities such as phosphorus (P) are selectively diffused from the surfaces of the p-type semiconductor layers 31 and 32 to form n-type semiconductor layers 41 to 43. Thereafter, a mesa groove 11 reaching the junction J1 of the semiconductor layers 30 and 31 is formed on the upper surface of the semiconductor substrate 10, an insulating material 12 such as glass is embedded in the mesa groove 11, and the p-type semiconductor layer 31 is formed into the mesa. It is separated by the groove 11. The main terminals T1 and T2 and the gate terminal Tg are formed by depositing a metal film on the surface of the semiconductor substrate 10. The main terminal T1 is formed over the p-type semiconductor layer 31 and the n-type semiconductor layer 41, the main terminal T2 is formed over the p-type semiconductor layer 32 and the n-type semiconductor layer 42, and the gate terminal Tg is defined as p It is formed across the type semiconductor layer 31 and the n-type semiconductor layer 43. Finally, the semiconductor substrate 10 is diced by the cutting line LL in the p-type semiconductor layer 33, whereby the triac 100 shown in FIGS. 1 and 2 is obtained.

  FIG. 6 is a diagram showing the lightning surge voltage of the triac 100 according to the present invention in comparison with the conventional triac 102. In the figure, 71 is the lightning surge voltage of the triac 100 according to the present embodiment, and 72 is the lightning surge voltage of the conventional triac 102. The triacs 100 and 102 differ only in the planar layout.

  In general, the triac surge capability is expressed as a lightning surge voltage. The lightning surge voltage is monotonously increased in 1 μsec with the gate terminal Tg opened, and the device is not destroyed when a surge voltage that monotonously decreases in 50 μsec is applied between the main terminals T1 and T2 of the triac. Measured as maximum voltage. The I mode is a mode in which a voltage with the main terminal T2 being positive is applied, and the III mode is a mode in which a voltage with the main terminal T1 being positive is applied.

  The lightning surge voltage of the conventional triac 102 is 3 kV in the I mode and 2 kV in the III mode, whereas the lightning surge voltage of the triac 100 according to the present embodiment is 5 kV in the I mode and 4 kV in the III mode. Therefore, it can be seen that the lightning surge voltage is approximately doubled only by changing the plane layout, and the surge resistance is greatly improved.

  According to the present embodiment, by making the planar region of the n-type semiconductor layer 41 symmetrical, two or more local regions that are different in the initial stage of turn-on when a surge voltage with a positive main terminal T2 is applied. Is turned on. Therefore, the ON region can be expanded quickly, and element breakdown due to current concentration can be suppressed. As a result, it is possible to increase the withstand capability against a surge voltage at which the main terminal T2 is positive.

  Similarly, by making the planar region of the n-type semiconductor layer 42 symmetrical, when a surge voltage with a positive main terminal T1 is applied, two or more different local regions are turned on at the initial stage of turn-on. Can do. Therefore, it is possible to increase the withstand capability against a surge voltage that is positive at the main terminal T1.

  Further, by arranging one of the n-type semiconductor layers 41 and 42 so as to substantially surround the other, the area of the n-type semiconductor layers 41 and 42 is secured while ensuring a necessary area. Is formed. For this reason, even if it is a case where either of main terminal T1, T2 is made into plus, the tolerance with respect to a surge voltage can be increased.

  In particular, the n-type semiconductor layers 41 and 42 are formed in line-symmetrical shapes by arranging the n-type semiconductor layer 41 in a non-annular shape and arranging the n-type semiconductor layer 42 so as to be surrounded by the n-type semiconductor layers 41 and 43, respectively. can do. Accordingly, it is possible to increase the tolerance to surge voltage without significantly degrading the performance in normal operation.

  Here, an example in which the formation regions of the n-type semiconductor layers 41 and 42 are line-symmetrical shapes has been described, but the present invention is not limited to such a case. For example, the formation region of the n-type semiconductor layers 41 and 42 may have a point-symmetric shape. Further, even if the shape is not symmetrical, it is needless to say that the same effect can be obtained if the on-state is generated in two or more different local regions in the initial stage of turn-on.

Embodiment 2. FIG.
FIGS. 7A and 7B are plan views showing one configuration example of the triac 101 according to the second embodiment of the present invention. FIG. 7A is a plan view of the triac 101, and FIG. 7B is a DD cut line. A cross-sectional view is shown. The triac 101 is different from the triac 100 (Embodiment 1) shown in FIGS. 1 and 2 in that a large number of small holes 61 and 62 are formed in the n-type semiconductor layers 41 and 42, respectively.

  The small hole 61 is a small region (short emitter) of the p-type semiconductor layer 31 formed in the n-type semiconductor layer 41. The small holes 61 are small regions in the n-type semiconductor layer 41 where n-type impurities are not diffused when the n-type semiconductor layer 41 is formed, and are formed so as to penetrate the n-type semiconductor layer 41 from the upper surface of the semiconductor substrate 10. ing. When such small holes 61 are formed in the n-type semiconductor layer 41, the pinch resistance of the p-type semiconductor layer 31 becomes a set of small resistances separated by the small holes 61, and the small holes 61 are not formed. Compared to the above, pinch resistance can be reduced.

  If the capacitance of the depletion layer formed at the time of reverse bias of the junction surfaces (pn junction J1) of the semiconductor layers 30 and 31 is C, and the steep voltage change applied to the triac 100 is dv / dt, the current I = C ( dv / dt) flows through the pinch resistor. Therefore, if the pinch resistance is R, the voltage drop when the current I flows is RC (dv / dt). It is known that when this voltage drop exceeds the diffusion potential of the pn junction J1 (0.7V in the case of silicon), it is turned on by the voltage change and the triac 100 malfunctions. Such a malfunction can be suppressed by providing a small hole 61 in the n-type semiconductor layer 41 to reduce the pinch resistance R.

  In exactly the same manner, the small hole 62 is a small region (short emitter) of the p-type semiconductor layer 32 formed in the n-type semiconductor layer 42. The small holes 62 are small regions in the n-type semiconductor layer 42 where n-type impurities are not diffused when the n-type semiconductor layer 42 is formed, and are formed so as to penetrate the n-type semiconductor layer 42 from the lower surface of the semiconductor substrate 10. ing. By forming such small holes 62 in the n-type semiconductor layer 42, the pinch resistance of the p-type semiconductor layer 32 becomes a set of small resistances separated by the small holes 62, and the small holes 62 are not formed. Compared to the above, pinch resistance can be reduced.

  In the present embodiment, an example in which the semiconductor substrate 10, the mesa groove 11, the mesa region 13, and the n-type semiconductor layer 42 are square has been described. However, the present invention is not limited to such a case. For example, these shapes can be triangular, rectangular, other polygons, ellipses, and circles. Further, the mesa region 13 may be rectangular and the n-type semiconductor layer 42 may be circular.

  In this embodiment, an example in which the n-type semiconductor layer 41 is disposed so as to surround the n-type semiconductor layer 42 has been described, but the present invention is not limited to such a case. For example, the n-type semiconductor layer 42 can be disposed so as to surround the n-type semiconductor layer 41.

  In the present embodiment, an example in which each of the n-type semiconductor layers 41 and 42 is formed as one continuous region has been described. However, the present invention is not limited to such a case. For example, even if the n-type semiconductor layer 41 is divided into two or more regions, it may be formed so that two or more different local regions can be turned on in the initial turn-on stage.

It is the top view which showed the example of 1 structure of the triac 100 by Embodiment 1 of this invention. It is sectional drawing at the time of cut | disconnecting the triac 100 of FIG. 1 by the AA cut line. It is the figure which showed the mode when the surge voltage from which the main terminal T2 becomes plus was applied. It is the figure which showed the mode when the surge voltage from which the main terminal T1 becomes plus was applied. It is explanatory drawing for demonstrating an example of the manufacturing method of the triac by this Embodiment, and the AA cross section at the time of manufacture is shown. It is the figure which showed the lightning surge voltage of the triac 100 by this invention compared with the conventional triac 102. FIG. It is the top view which showed one structural example of the triac 101 by Embodiment 2 of this invention. It is the top view which showed the example of 1 structure of the conventional triac 102. It is the figure which showed the EE cut surface when the surge voltage from which the main terminal T2 becomes plus is applied. It is the figure which showed the FF cut surface when the surge voltage from which the main terminal T2 becomes plus is applied. It is the figure which showed the EE cut surface when the surge voltage from which the main terminal T1 becomes plus is applied.

Explanation of symbols

10 n-type semiconductor substrate 11 mesa groove 13 mesa region 30, 31 p-type semiconductor layer 41-43 n-type semiconductor layer 51, 52 local region 61, 62 small hole 100-102 triac d predetermined interval J1-J5 pn junction T1, T2 Main terminal Tg Gate terminal

Claims (2)

A first semiconductor layer and a second semiconductor layer made of a second conductivity type formed by diffusing impurities from both main surfaces of the first conductivity type semiconductor substrate;
A third semiconductor layer and a fourth semiconductor layer of a first conductivity type formed by selectively diffusing impurities from the surface of the first semiconductor layer so as not to overlap each other;
A fifth semiconductor layer of a first conductivity type that selectively diffuses impurities from the surface of the second semiconductor layer and is formed in a planar region that does not overlap with the third semiconductor layer;
A first main terminal formed on the first and third semiconductor layers;
A gate terminal formed on the first and fourth semiconductor layers;
A second main terminal formed on the second and fifth semiconductor layers,
Third and fifth semiconductor layers are respectively formed in the plane regions that are symmetrical ,
A triac , wherein the fifth semiconductor layer is formed so as to be surrounded by the third and fourth semiconductor layers . The fifth semiconductor layer is formed as a substantially square region;
A fourth semiconductor layer is formed on a diagonal line of the fifth semiconductor layer;
The triac according to claim 1 , wherein the third semiconductor layer has a shape that is symmetric with respect to the diagonal line.

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